MIPS: Move gic.h to include/linux/irqchip/mips-gic.h

Now that the MIPS GIC irqchip lives in drivers/irqchip/, move
its header over to include/linux/irqchip/.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8129/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
deleted file mode 100644 (file)
index 285944c..0000000
--- a/arch/mips/include/asm/gic.h
+++ /dev/null
@@ -1,325 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000, 07 MIPS Technologies, Inc.
- *
- * GIC Register Definitions
- *
- */
-#ifndef _ASM_GICREGS_H
-#define _ASM_GICREGS_H
-
-#include <linux/bitmap.h>
-#include <linux/threads.h>
-
-#include <irq.h>
-
-#define GIC_MAX_INTRS                  256
-
-/* Constants */
-#define GIC_POL_POS                    1
-#define GIC_POL_NEG                    0
-#define GIC_TRIG_EDGE                  1
-#define GIC_TRIG_LEVEL                 0
-#define GIC_TRIG_DUAL_ENABLE           1
-#define GIC_TRIG_DUAL_DISABLE          0
-
-#define MSK(n) ((1 << (n)) - 1)
-
-/* Accessors */
-#define GIC_REG(segment, offset) (segment##_##SECTION_OFS + offset##_##OFS)
-
-/* GIC Address Space */
-#define SHARED_SECTION_OFS             0x0000
-#define SHARED_SECTION_SIZE            0x8000
-#define VPE_LOCAL_SECTION_OFS          0x8000
-#define VPE_LOCAL_SECTION_SIZE         0x4000
-#define VPE_OTHER_SECTION_OFS          0xc000
-#define VPE_OTHER_SECTION_SIZE         0x4000
-#define USM_VISIBLE_SECTION_OFS                0x10000
-#define USM_VISIBLE_SECTION_SIZE       0x10000
-
-/* Register Map for Shared Section */
-
-#define GIC_SH_CONFIG_OFS              0x0000
-
-/* Shared Global Counter */
-#define GIC_SH_COUNTER_31_00_OFS       0x0010
-#define GIC_SH_COUNTER_63_32_OFS       0x0014
-#define GIC_SH_REVISIONID_OFS          0x0020
-
-/* Interrupt Polarity */
-#define GIC_SH_POL_31_0_OFS            0x0100
-#define GIC_SH_POL_63_32_OFS           0x0104
-#define GIC_SH_POL_95_64_OFS           0x0108
-#define GIC_SH_POL_127_96_OFS          0x010c
-#define GIC_SH_POL_159_128_OFS         0x0110
-#define GIC_SH_POL_191_160_OFS         0x0114
-#define GIC_SH_POL_223_192_OFS         0x0118
-#define GIC_SH_POL_255_224_OFS         0x011c
-
-/* Edge/Level Triggering */
-#define GIC_SH_TRIG_31_0_OFS           0x0180
-#define GIC_SH_TRIG_63_32_OFS          0x0184
-#define GIC_SH_TRIG_95_64_OFS          0x0188
-#define GIC_SH_TRIG_127_96_OFS         0x018c
-#define GIC_SH_TRIG_159_128_OFS                0x0190
-#define GIC_SH_TRIG_191_160_OFS                0x0194
-#define GIC_SH_TRIG_223_192_OFS                0x0198
-#define GIC_SH_TRIG_255_224_OFS                0x019c
-
-/* Dual Edge Triggering */
-#define GIC_SH_DUAL_31_0_OFS           0x0200
-#define GIC_SH_DUAL_63_32_OFS          0x0204
-#define GIC_SH_DUAL_95_64_OFS          0x0208
-#define GIC_SH_DUAL_127_96_OFS         0x020c
-#define GIC_SH_DUAL_159_128_OFS                0x0210
-#define GIC_SH_DUAL_191_160_OFS                0x0214
-#define GIC_SH_DUAL_223_192_OFS                0x0218
-#define GIC_SH_DUAL_255_224_OFS                0x021c
-
-/* Set/Clear corresponding bit in Edge Detect Register */
-#define GIC_SH_WEDGE_OFS               0x0280
-
-/* Reset Mask - Disables Interrupt */
-#define GIC_SH_RMASK_31_0_OFS          0x0300
-#define GIC_SH_RMASK_63_32_OFS         0x0304
-#define GIC_SH_RMASK_95_64_OFS         0x0308
-#define GIC_SH_RMASK_127_96_OFS                0x030c
-#define GIC_SH_RMASK_159_128_OFS       0x0310
-#define GIC_SH_RMASK_191_160_OFS       0x0314
-#define GIC_SH_RMASK_223_192_OFS       0x0318
-#define GIC_SH_RMASK_255_224_OFS       0x031c
-
-/* Set Mask (WO) - Enables Interrupt */
-#define GIC_SH_SMASK_31_0_OFS          0x0380
-#define GIC_SH_SMASK_63_32_OFS         0x0384
-#define GIC_SH_SMASK_95_64_OFS         0x0388
-#define GIC_SH_SMASK_127_96_OFS                0x038c
-#define GIC_SH_SMASK_159_128_OFS       0x0390
-#define GIC_SH_SMASK_191_160_OFS       0x0394
-#define GIC_SH_SMASK_223_192_OFS       0x0398
-#define GIC_SH_SMASK_255_224_OFS       0x039c
-
-/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
-#define GIC_SH_MASK_31_0_OFS           0x0400
-#define GIC_SH_MASK_63_32_OFS          0x0404
-#define GIC_SH_MASK_95_64_OFS          0x0408
-#define GIC_SH_MASK_127_96_OFS         0x040c
-#define GIC_SH_MASK_159_128_OFS                0x0410
-#define GIC_SH_MASK_191_160_OFS                0x0414
-#define GIC_SH_MASK_223_192_OFS                0x0418
-#define GIC_SH_MASK_255_224_OFS                0x041c
-
-/* Pending Global Interrupts (RO) */
-#define GIC_SH_PEND_31_0_OFS           0x0480
-#define GIC_SH_PEND_63_32_OFS          0x0484
-#define GIC_SH_PEND_95_64_OFS          0x0488
-#define GIC_SH_PEND_127_96_OFS         0x048c
-#define GIC_SH_PEND_159_128_OFS                0x0490
-#define GIC_SH_PEND_191_160_OFS                0x0494
-#define GIC_SH_PEND_223_192_OFS                0x0498
-#define GIC_SH_PEND_255_224_OFS                0x049c
-
-#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
-
-/* Maps Interrupt X to a Pin */
-#define GIC_SH_MAP_TO_PIN(intr)                (4 * (intr))
-
-#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
-
-/* Maps Interrupt X to a VPE */
-#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
-       ((32 * (intr)) + (((vpe) / 32) * 4))
-#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
-
-/* Convert an interrupt number to a byte offset/bit for multi-word registers */
-#define GIC_INTR_OFS(intr) (((intr) / 32)*4)
-#define GIC_INTR_BIT(intr) ((intr) % 32)
-
-/* Polarity : Reset Value is always 0 */
-#define GIC_SH_SET_POLARITY_OFS                0x0100
-
-/* Triggering : Reset Value is always 0 */
-#define GIC_SH_SET_TRIGGER_OFS         0x0180
-
-/* Dual edge triggering : Reset Value is always 0 */
-#define GIC_SH_SET_DUAL_OFS            0x0200
-
-/* Mask manipulation */
-#define GIC_SH_SMASK_OFS               0x0380
-#define GIC_SH_RMASK_OFS               0x0300
-
-/* Register Map for Local Section */
-#define GIC_VPE_CTL_OFS                        0x0000
-#define GIC_VPE_PEND_OFS               0x0004
-#define GIC_VPE_MASK_OFS               0x0008
-#define GIC_VPE_RMASK_OFS              0x000c
-#define GIC_VPE_SMASK_OFS              0x0010
-#define GIC_VPE_WD_MAP_OFS             0x0040
-#define GIC_VPE_COMPARE_MAP_OFS                0x0044
-#define GIC_VPE_TIMER_MAP_OFS          0x0048
-#define GIC_VPE_FDC_MAP_OFS            0x004c
-#define GIC_VPE_PERFCTR_MAP_OFS                0x0050
-#define GIC_VPE_SWINT0_MAP_OFS         0x0054
-#define GIC_VPE_SWINT1_MAP_OFS         0x0058
-#define GIC_VPE_OTHER_ADDR_OFS         0x0080
-#define GIC_VPE_WD_CONFIG0_OFS         0x0090
-#define GIC_VPE_WD_COUNT0_OFS          0x0094
-#define GIC_VPE_WD_INITIAL0_OFS                0x0098
-#define GIC_VPE_COMPARE_LO_OFS         0x00a0
-#define GIC_VPE_COMPARE_HI_OFS         0x00a4
-
-#define GIC_VPE_EIC_SHADOW_SET_BASE_OFS        0x0100
-#define GIC_VPE_EIC_SS(intr)           (4 * (intr))
-
-#define GIC_VPE_EIC_VEC_BASE_OFS       0x0800
-#define GIC_VPE_EIC_VEC(intr)          (4 * (intr))
-
-#define GIC_VPE_TENABLE_NMI_OFS                0x1000
-#define GIC_VPE_TENABLE_YQ_OFS         0x1004
-#define GIC_VPE_TENABLE_INT_31_0_OFS   0x1080
-#define GIC_VPE_TENABLE_INT_63_32_OFS  0x1084
-
-/* User Mode Visible Section Register Map */
-#define GIC_UMV_SH_COUNTER_31_00_OFS   0x0000
-#define GIC_UMV_SH_COUNTER_63_32_OFS   0x0004
-
-/* Masks */
-#define GIC_SH_CONFIG_COUNTSTOP_SHF    28
-#define GIC_SH_CONFIG_COUNTSTOP_MSK    (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
-
-#define GIC_SH_CONFIG_COUNTBITS_SHF    24
-#define GIC_SH_CONFIG_COUNTBITS_MSK    (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
-
-#define GIC_SH_CONFIG_NUMINTRS_SHF     16
-#define GIC_SH_CONFIG_NUMINTRS_MSK     (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
-
-#define GIC_SH_CONFIG_NUMVPES_SHF      0
-#define GIC_SH_CONFIG_NUMVPES_MSK      (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
-
-#define GIC_SH_WEDGE_SET(intr)         (intr | (0x1 << 31))
-#define GIC_SH_WEDGE_CLR(intr)         (intr & ~(0x1 << 31))
-
-#define GIC_MAP_TO_PIN_SHF             31
-#define GIC_MAP_TO_PIN_MSK             (MSK(1) << GIC_MAP_TO_PIN_SHF)
-#define GIC_MAP_TO_NMI_SHF             30
-#define GIC_MAP_TO_NMI_MSK             (MSK(1) << GIC_MAP_TO_NMI_SHF)
-#define GIC_MAP_TO_YQ_SHF              29
-#define GIC_MAP_TO_YQ_MSK              (MSK(1) << GIC_MAP_TO_YQ_SHF)
-#define GIC_MAP_SHF                    0
-#define GIC_MAP_MSK                    (MSK(6) << GIC_MAP_SHF)
-
-/* GIC_VPE_CTL Masks */
-#define GIC_VPE_CTL_FDC_RTBL_SHF       4
-#define GIC_VPE_CTL_FDC_RTBL_MSK       (MSK(1) << GIC_VPE_CTL_FDC_RTBL_SHF)
-#define GIC_VPE_CTL_SWINT_RTBL_SHF     3
-#define GIC_VPE_CTL_SWINT_RTBL_MSK     (MSK(1) << GIC_VPE_CTL_SWINT_RTBL_SHF)
-#define GIC_VPE_CTL_PERFCNT_RTBL_SHF   2
-#define GIC_VPE_CTL_PERFCNT_RTBL_MSK   (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
-#define GIC_VPE_CTL_TIMER_RTBL_SHF     1
-#define GIC_VPE_CTL_TIMER_RTBL_MSK     (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
-#define GIC_VPE_CTL_EIC_MODE_SHF       0
-#define GIC_VPE_CTL_EIC_MODE_MSK       (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
-
-/* GIC_VPE_PEND Masks */
-#define GIC_VPE_PEND_WD_SHF            0
-#define GIC_VPE_PEND_WD_MSK            (MSK(1) << GIC_VPE_PEND_WD_SHF)
-#define GIC_VPE_PEND_CMP_SHF           1
-#define GIC_VPE_PEND_CMP_MSK           (MSK(1) << GIC_VPE_PEND_CMP_SHF)
-#define GIC_VPE_PEND_TIMER_SHF         2
-#define GIC_VPE_PEND_TIMER_MSK         (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
-#define GIC_VPE_PEND_PERFCOUNT_SHF     3
-#define GIC_VPE_PEND_PERFCOUNT_MSK     (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
-#define GIC_VPE_PEND_SWINT0_SHF                4
-#define GIC_VPE_PEND_SWINT0_MSK                (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
-#define GIC_VPE_PEND_SWINT1_SHF                5
-#define GIC_VPE_PEND_SWINT1_MSK                (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
-
-/* GIC_VPE_RMASK Masks */
-#define GIC_VPE_RMASK_WD_SHF           0
-#define GIC_VPE_RMASK_WD_MSK           (MSK(1) << GIC_VPE_RMASK_WD_SHF)
-#define GIC_VPE_RMASK_CMP_SHF          1
-#define GIC_VPE_RMASK_CMP_MSK          (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
-#define GIC_VPE_RMASK_TIMER_SHF                2
-#define GIC_VPE_RMASK_TIMER_MSK                (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
-#define GIC_VPE_RMASK_PERFCNT_SHF      3
-#define GIC_VPE_RMASK_PERFCNT_MSK      (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
-#define GIC_VPE_RMASK_SWINT0_SHF       4
-#define GIC_VPE_RMASK_SWINT0_MSK       (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
-#define GIC_VPE_RMASK_SWINT1_SHF       5
-#define GIC_VPE_RMASK_SWINT1_MSK       (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
-
-/* GIC_VPE_SMASK Masks */
-#define GIC_VPE_SMASK_WD_SHF           0
-#define GIC_VPE_SMASK_WD_MSK           (MSK(1) << GIC_VPE_SMASK_WD_SHF)
-#define GIC_VPE_SMASK_CMP_SHF          1
-#define GIC_VPE_SMASK_CMP_MSK          (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
-#define GIC_VPE_SMASK_TIMER_SHF                2
-#define GIC_VPE_SMASK_TIMER_MSK                (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
-#define GIC_VPE_SMASK_PERFCNT_SHF      3
-#define GIC_VPE_SMASK_PERFCNT_MSK      (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
-#define GIC_VPE_SMASK_SWINT0_SHF       4
-#define GIC_VPE_SMASK_SWINT0_MSK       (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
-#define GIC_VPE_SMASK_SWINT1_SHF       5
-#define GIC_VPE_SMASK_SWINT1_MSK       (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
-
-/* GIC nomenclature for Core Interrupt Pins. */
-#define GIC_CPU_INT0           0 /* Core Interrupt 2 */
-#define GIC_CPU_INT1           1 /* .                */
-#define GIC_CPU_INT2           2 /* .                */
-#define GIC_CPU_INT3           3 /* .                */
-#define GIC_CPU_INT4           4 /* .                */
-#define GIC_CPU_INT5           5 /* Core Interrupt 7 */
-
-/* Add 2 to convert GIC CPU pin to core interrupt */
-#define GIC_CPU_PIN_OFFSET     2
-
-/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
-#define GIC_CPU_TO_VEC_OFFSET  (2)
-
-/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
-#define GIC_PIN_TO_VEC_OFFSET  (1)
-
-/* Local GIC interrupts. */
-#define GIC_LOCAL_INT_WD       0 /* GIC watchdog */
-#define GIC_LOCAL_INT_COMPARE  1 /* GIC count and compare timer */
-#define GIC_LOCAL_INT_TIMER    2 /* CPU timer interrupt */
-#define GIC_LOCAL_INT_PERFCTR  3 /* CPU performance counter */
-#define GIC_LOCAL_INT_SWINT0   4 /* CPU software interrupt 0 */
-#define GIC_LOCAL_INT_SWINT1   5 /* CPU software interrupt 1 */
-#define GIC_LOCAL_INT_FDC      6 /* CPU fast debug channel */
-#define GIC_NUM_LOCAL_INTRS    7
-
-/* Convert between local/shared IRQ number and GIC HW IRQ number. */
-#define GIC_LOCAL_HWIRQ_BASE   0
-#define GIC_LOCAL_TO_HWIRQ(x)  (GIC_LOCAL_HWIRQ_BASE + (x))
-#define GIC_HWIRQ_TO_LOCAL(x)  ((x) - GIC_LOCAL_HWIRQ_BASE)
-#define GIC_SHARED_HWIRQ_BASE  GIC_NUM_LOCAL_INTRS
-#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
-#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
-
-#include <linux/clocksource.h>
-#include <linux/irq.h>
-
-extern unsigned int gic_present;
-extern unsigned int gic_frequency;
-
-extern void gic_init(unsigned long gic_base_addr,
-       unsigned long gic_addrspace_size, unsigned int cpu_vec,
-       unsigned int irqbase);
-extern void gic_clocksource_init(unsigned int);
-extern cycle_t gic_read_count(void);
-extern unsigned int gic_get_count_width(void);
-extern cycle_t gic_read_compare(void);
-extern void gic_write_compare(cycle_t cnt);
-extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
-extern void gic_send_ipi(unsigned int intr);
-extern unsigned int plat_ipi_call_int_xlate(unsigned int);
-extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
-extern unsigned int gic_get_timer_pending(void);
-extern int gic_get_c0_compare_int(void);
-extern int gic_get_c0_perfcount_int(void);
-#endif /* _ASM_GICREGS_H */

diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h
index 38b06a0..987ff58 100644 (file)
--- a/arch/mips/include/asm/mips-boards/maltaint.h
+++ b/arch/mips/include/asm/mips-boards/maltaint.h
@@ -10,7 +10,7 @@
 #ifndef _MIPS_MALTAINT_H
 #define _MIPS_MALTAINT_H
 
-#include <asm/gic.h>
+#include <linux/irqchip/mips-gic.h>
 
 /*
  * Interrupts 0..15 are used for Malta ISA compatible interrupts

diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h
index 59d6c32..8932c7d 100644 (file)
--- a/arch/mips/include/asm/mips-boards/sead3int.h
+++ b/arch/mips/include/asm/mips-boards/sead3int.h
@@ -10,7 +10,7 @@
 #ifndef _MIPS_SEAD3INT_H
 #define _MIPS_SEAD3INT_H
 
-#include <asm/gic.h>
+#include <linux/irqchip/mips-gic.h>
 
 /* SEAD-3 GIC address space definitions. */
 #define GIC_BASE_ADDR          0x1b1c0000

diff --git a/arch/mips/kernel/cevt-gic.c b/arch/mips/kernel/cevt-gic.c
index 4f9262a..9caa68a 100644 (file)
--- a/arch/mips/kernel/cevt-gic.c
+++ b/arch/mips/kernel/cevt-gic.c
@@ -10,9 +10,9 @@
 #include <linux/percpu.h>
 #include <linux/smp.h>
 #include <linux/irq.h>
+#include <linux/irqchip/mips-gic.h>
 
 #include <asm/time.h>
-#include <asm/gic.h>
 #include <asm/mips-boards/maltaint.h>
 
 DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);

diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index fd0ef8d..6acaad0 100644 (file)
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -11,10 +11,10 @@
 #include <linux/percpu.h>
 #include <linux/smp.h>
 #include <linux/irq.h>
+#include <linux/irqchip/mips-gic.h>
 
 #include <asm/time.h>
 #include <asm/cevt-r4k.h>
-#include <asm/gic.h>
 
 static int mips_next_event(unsigned long delta,
                           struct clock_event_device *evt)

diff --git a/arch/mips/kernel/csrc-gic.c b/arch/mips/kernel/csrc-gic.c
index ab615c6..0bf28e6 100644 (file)
--- a/arch/mips/kernel/csrc-gic.c
+++ b/arch/mips/kernel/csrc-gic.c
@@ -6,10 +6,9 @@
  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
  */
 #include <linux/init.h>
+#include <linux/irqchip/mips-gic.h>
 #include <linux/time.h>
 
-#include <asm/gic.h>
-
 static cycle_t gic_hpt_read(struct clocksource *cs)
 {
        return gic_read_count();

diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
index fc8a515..1e0a93c 100644 (file)
--- a/arch/mips/kernel/smp-cmp.c
+++ b/arch/mips/kernel/smp-cmp.c
@@ -24,6 +24,7 @@
 #include <linux/cpumask.h>
 #include <linux/interrupt.h>
 #include <linux/compiler.h>
+#include <linux/irqchip/mips-gic.h>
 
 #include <linux/atomic.h>
 #include <asm/cacheflush.h>
@@ -37,7 +38,6 @@
 #include <asm/mipsmtregs.h>
 #include <asm/mips_mt.h>
 #include <asm/amon.h>
-#include <asm/gic.h>
 
 static void cmp_init_secondary(void)
 {

diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index cd20aca..bed7590 100644 (file)
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -9,13 +9,13 @@
  */
 
 #include <linux/io.h>
+#include <linux/irqchip/mips-gic.h>
 #include <linux/sched.h>
 #include <linux/slab.h>
 #include <linux/smp.h>
 #include <linux/types.h>
 
 #include <asm/bcache.h>
-#include <asm/gic.h>
 #include <asm/mips-cm.h>
 #include <asm/mips-cpc.h>
 #include <asm/mips_mt.h>

diff --git a/arch/mips/kernel/smp-gic.c b/arch/mips/kernel/smp-gic.c
index 3b21a96..5f0ab5b 100644 (file)
--- a/arch/mips/kernel/smp-gic.c
+++ b/arch/mips/kernel/smp-gic.c
@@ -12,9 +12,9 @@
  * option) any later version.
  */
 
+#include <linux/irqchip/mips-gic.h>
 #include <linux/printk.h>
 
-#include <asm/gic.h>
 #include <asm/mips-cpc.h>
 #include <asm/smp-ops.h>
 

diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index d60475f..ad86951 100644 (file)
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -21,6 +21,7 @@
 #include <linux/sched.h>
 #include <linux/cpumask.h>
 #include <linux/interrupt.h>
+#include <linux/irqchip/mips-gic.h>
 #include <linux/compiler.h>
 #include <linux/smp.h>
 
@@ -34,7 +35,6 @@
 #include <asm/mipsregs.h>
 #include <asm/mipsmtregs.h>
 #include <asm/mips_mt.h>
-#include <asm/gic.h>
 
 static void __init smvp_copy_vpe_config(void)
 {

diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index a058e0b..d1392f8 100644 (file)
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -18,6 +18,7 @@
 #include <linux/smp.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
+#include <linux/irqchip/mips-gic.h>
 #include <linux/kernel_stat.h>
 #include <linux/kernel.h>
 #include <linux/random.h>
@@ -33,7 +34,6 @@
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/msc01_pci.h>
 #include <asm/msc01_ic.h>
-#include <asm/gic.h>
 #include <asm/setup.h>
 #include <asm/rtlx.h>
 

diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index 39f3902..608655f 100644 (file)
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -24,6 +24,7 @@
 #include <linux/sched.h>
 #include <linux/spinlock.h>
 #include <linux/interrupt.h>
+#include <linux/irqchip/mips-gic.h>
 #include <linux/timex.h>
 #include <linux/mc146818rtc.h>
 
@@ -37,7 +38,6 @@
 #include <asm/time.h>
 #include <asm/mc146818-time.h>
 #include <asm/msc01_ic.h>
-#include <asm/gic.h>
 
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/maltaint.h>

diff --git a/arch/mips/mti-sead3/sead3-ehci.c b/arch/mips/mti-sead3/sead3-ehci.c
index 4ddaa0f..014dd7b 100644 (file)
--- a/arch/mips/mti-sead3/sead3-ehci.c
+++ b/arch/mips/mti-sead3/sead3-ehci.c
@@ -9,8 +9,8 @@
 #include <linux/irq.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
+#include <linux/irqchip/mips-gic.h>
 
-#include <asm/gic.h>
 #include <asm/mips-boards/sead3int.h>
 
 struct resource ehci_resources[] = {

diff --git a/arch/mips/mti-sead3/sead3-int.c b/arch/mips/mti-sead3/sead3-int.c
index 02bf0db..e31e17f 100644 (file)
--- a/arch/mips/mti-sead3/sead3-int.c
+++ b/arch/mips/mti-sead3/sead3-int.c
@@ -7,9 +7,9 @@
  */
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/irqchip/mips-gic.h>
 #include <linux/io.h>
 
-#include <asm/gic.h>
 #include <asm/irq_cpu.h>
 #include <asm/setup.h>
 

diff --git a/arch/mips/mti-sead3/sead3-net.c b/arch/mips/mti-sead3/sead3-net.c
index c9f728a..46176b8 100644 (file)
--- a/arch/mips/mti-sead3/sead3-net.c
+++ b/arch/mips/mti-sead3/sead3-net.c
@@ -7,10 +7,10 @@
  */
 #include <linux/module.h>
 #include <linux/irq.h>
+#include <linux/irqchip/mips-gic.h>
 #include <linux/platform_device.h>
 #include <linux/smsc911x.h>
 
-#include <asm/gic.h>
 #include <asm/mips-boards/sead3int.h>
 
 static struct smsc911x_platform_config sead3_smsc911x_data = {

diff --git a/arch/mips/mti-sead3/sead3-platform.c b/arch/mips/mti-sead3/sead3-platform.c
index d9661eb..53ee6f1 100644 (file)
--- a/arch/mips/mti-sead3/sead3-platform.c
+++ b/arch/mips/mti-sead3/sead3-platform.c
@@ -7,9 +7,9 @@
  */
 #include <linux/module.h>
 #include <linux/init.h>
+#include <linux/irqchip/mips-gic.h>
 #include <linux/serial_8250.h>
 
-#include <asm/gic.h>
 #include <asm/mips-boards/sead3int.h>
 
 #define UART(base)                                                     \

diff --git a/arch/mips/mti-sead3/sead3-time.c b/arch/mips/mti-sead3/sead3-time.c
index fd40de3..ec1dd24 100644 (file)
--- a/arch/mips/mti-sead3/sead3-time.c
+++ b/arch/mips/mti-sead3/sead3-time.c
@@ -6,9 +6,9 @@
  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
  */
 #include <linux/init.h>
+#include <linux/irqchip/mips-gic.h>
 
 #include <asm/cpu.h>
-#include <asm/gic.h>
 #include <asm/setup.h>
 #include <asm/time.h>
 #include <asm/irq.h>

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 88086d7..bf0f7c9 100644 (file)
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -9,13 +9,13 @@
 #include <linux/bitmap.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/irqchip/mips-gic.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/irq.h>
 #include <linux/clocksource.h>
 
 #include <asm/io.h>
-#include <asm/gic.h>
 #include <asm/setup.h>
 #include <asm/traps.h>
 #include <linux/hardirq.h>

diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h
new file mode 100644 (file)
index 0000000..285944c
--- /dev/null
+++ b/include/linux/irqchip/mips-gic.h
@@ -0,0 +1,325 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000, 07 MIPS Technologies, Inc.
+ *
+ * GIC Register Definitions
+ *
+ */
+#ifndef _ASM_GICREGS_H
+#define _ASM_GICREGS_H
+
+#include <linux/bitmap.h>
+#include <linux/threads.h>
+
+#include <irq.h>
+
+#define GIC_MAX_INTRS                  256
+
+/* Constants */
+#define GIC_POL_POS                    1
+#define GIC_POL_NEG                    0
+#define GIC_TRIG_EDGE                  1
+#define GIC_TRIG_LEVEL                 0
+#define GIC_TRIG_DUAL_ENABLE           1
+#define GIC_TRIG_DUAL_DISABLE          0
+
+#define MSK(n) ((1 << (n)) - 1)
+
+/* Accessors */
+#define GIC_REG(segment, offset) (segment##_##SECTION_OFS + offset##_##OFS)
+
+/* GIC Address Space */
+#define SHARED_SECTION_OFS             0x0000
+#define SHARED_SECTION_SIZE            0x8000
+#define VPE_LOCAL_SECTION_OFS          0x8000
+#define VPE_LOCAL_SECTION_SIZE         0x4000
+#define VPE_OTHER_SECTION_OFS          0xc000
+#define VPE_OTHER_SECTION_SIZE         0x4000
+#define USM_VISIBLE_SECTION_OFS                0x10000
+#define USM_VISIBLE_SECTION_SIZE       0x10000
+
+/* Register Map for Shared Section */
+
+#define GIC_SH_CONFIG_OFS              0x0000
+
+/* Shared Global Counter */
+#define GIC_SH_COUNTER_31_00_OFS       0x0010
+#define GIC_SH_COUNTER_63_32_OFS       0x0014
+#define GIC_SH_REVISIONID_OFS          0x0020
+
+/* Interrupt Polarity */
+#define GIC_SH_POL_31_0_OFS            0x0100
+#define GIC_SH_POL_63_32_OFS           0x0104
+#define GIC_SH_POL_95_64_OFS           0x0108
+#define GIC_SH_POL_127_96_OFS          0x010c
+#define GIC_SH_POL_159_128_OFS         0x0110
+#define GIC_SH_POL_191_160_OFS         0x0114
+#define GIC_SH_POL_223_192_OFS         0x0118
+#define GIC_SH_POL_255_224_OFS         0x011c
+
+/* Edge/Level Triggering */
+#define GIC_SH_TRIG_31_0_OFS           0x0180
+#define GIC_SH_TRIG_63_32_OFS          0x0184
+#define GIC_SH_TRIG_95_64_OFS          0x0188
+#define GIC_SH_TRIG_127_96_OFS         0x018c
+#define GIC_SH_TRIG_159_128_OFS                0x0190
+#define GIC_SH_TRIG_191_160_OFS                0x0194
+#define GIC_SH_TRIG_223_192_OFS                0x0198
+#define GIC_SH_TRIG_255_224_OFS                0x019c
+
+/* Dual Edge Triggering */
+#define GIC_SH_DUAL_31_0_OFS           0x0200
+#define GIC_SH_DUAL_63_32_OFS          0x0204
+#define GIC_SH_DUAL_95_64_OFS          0x0208
+#define GIC_SH_DUAL_127_96_OFS         0x020c
+#define GIC_SH_DUAL_159_128_OFS                0x0210
+#define GIC_SH_DUAL_191_160_OFS                0x0214
+#define GIC_SH_DUAL_223_192_OFS                0x0218
+#define GIC_SH_DUAL_255_224_OFS                0x021c
+
+/* Set/Clear corresponding bit in Edge Detect Register */
+#define GIC_SH_WEDGE_OFS               0x0280
+
+/* Reset Mask - Disables Interrupt */
+#define GIC_SH_RMASK_31_0_OFS          0x0300
+#define GIC_SH_RMASK_63_32_OFS         0x0304
+#define GIC_SH_RMASK_95_64_OFS         0x0308
+#define GIC_SH_RMASK_127_96_OFS                0x030c
+#define GIC_SH_RMASK_159_128_OFS       0x0310
+#define GIC_SH_RMASK_191_160_OFS       0x0314
+#define GIC_SH_RMASK_223_192_OFS       0x0318
+#define GIC_SH_RMASK_255_224_OFS       0x031c
+
+/* Set Mask (WO) - Enables Interrupt */
+#define GIC_SH_SMASK_31_0_OFS          0x0380
+#define GIC_SH_SMASK_63_32_OFS         0x0384
+#define GIC_SH_SMASK_95_64_OFS         0x0388
+#define GIC_SH_SMASK_127_96_OFS                0x038c
+#define GIC_SH_SMASK_159_128_OFS       0x0390
+#define GIC_SH_SMASK_191_160_OFS       0x0394
+#define GIC_SH_SMASK_223_192_OFS       0x0398
+#define GIC_SH_SMASK_255_224_OFS       0x039c
+
+/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
+#define GIC_SH_MASK_31_0_OFS           0x0400
+#define GIC_SH_MASK_63_32_OFS          0x0404
+#define GIC_SH_MASK_95_64_OFS          0x0408
+#define GIC_SH_MASK_127_96_OFS         0x040c
+#define GIC_SH_MASK_159_128_OFS                0x0410
+#define GIC_SH_MASK_191_160_OFS                0x0414
+#define GIC_SH_MASK_223_192_OFS                0x0418
+#define GIC_SH_MASK_255_224_OFS                0x041c
+
+/* Pending Global Interrupts (RO) */
+#define GIC_SH_PEND_31_0_OFS           0x0480
+#define GIC_SH_PEND_63_32_OFS          0x0484
+#define GIC_SH_PEND_95_64_OFS          0x0488
+#define GIC_SH_PEND_127_96_OFS         0x048c
+#define GIC_SH_PEND_159_128_OFS                0x0490
+#define GIC_SH_PEND_191_160_OFS                0x0494
+#define GIC_SH_PEND_223_192_OFS                0x0498
+#define GIC_SH_PEND_255_224_OFS                0x049c
+
+#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
+
+/* Maps Interrupt X to a Pin */
+#define GIC_SH_MAP_TO_PIN(intr)                (4 * (intr))
+
+#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
+
+/* Maps Interrupt X to a VPE */
+#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
+       ((32 * (intr)) + (((vpe) / 32) * 4))
+#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
+
+/* Convert an interrupt number to a byte offset/bit for multi-word registers */
+#define GIC_INTR_OFS(intr) (((intr) / 32)*4)
+#define GIC_INTR_BIT(intr) ((intr) % 32)
+
+/* Polarity : Reset Value is always 0 */
+#define GIC_SH_SET_POLARITY_OFS                0x0100
+
+/* Triggering : Reset Value is always 0 */
+#define GIC_SH_SET_TRIGGER_OFS         0x0180
+
+/* Dual edge triggering : Reset Value is always 0 */
+#define GIC_SH_SET_DUAL_OFS            0x0200
+
+/* Mask manipulation */
+#define GIC_SH_SMASK_OFS               0x0380
+#define GIC_SH_RMASK_OFS               0x0300
+
+/* Register Map for Local Section */
+#define GIC_VPE_CTL_OFS                        0x0000
+#define GIC_VPE_PEND_OFS               0x0004
+#define GIC_VPE_MASK_OFS               0x0008
+#define GIC_VPE_RMASK_OFS              0x000c
+#define GIC_VPE_SMASK_OFS              0x0010
+#define GIC_VPE_WD_MAP_OFS             0x0040
+#define GIC_VPE_COMPARE_MAP_OFS                0x0044
+#define GIC_VPE_TIMER_MAP_OFS          0x0048
+#define GIC_VPE_FDC_MAP_OFS            0x004c
+#define GIC_VPE_PERFCTR_MAP_OFS                0x0050
+#define GIC_VPE_SWINT0_MAP_OFS         0x0054
+#define GIC_VPE_SWINT1_MAP_OFS         0x0058
+#define GIC_VPE_OTHER_ADDR_OFS         0x0080
+#define GIC_VPE_WD_CONFIG0_OFS         0x0090
+#define GIC_VPE_WD_COUNT0_OFS          0x0094
+#define GIC_VPE_WD_INITIAL0_OFS                0x0098
+#define GIC_VPE_COMPARE_LO_OFS         0x00a0
+#define GIC_VPE_COMPARE_HI_OFS         0x00a4
+
+#define GIC_VPE_EIC_SHADOW_SET_BASE_OFS        0x0100
+#define GIC_VPE_EIC_SS(intr)           (4 * (intr))
+
+#define GIC_VPE_EIC_VEC_BASE_OFS       0x0800
+#define GIC_VPE_EIC_VEC(intr)          (4 * (intr))
+
+#define GIC_VPE_TENABLE_NMI_OFS                0x1000
+#define GIC_VPE_TENABLE_YQ_OFS         0x1004
+#define GIC_VPE_TENABLE_INT_31_0_OFS   0x1080
+#define GIC_VPE_TENABLE_INT_63_32_OFS  0x1084
+
+/* User Mode Visible Section Register Map */
+#define GIC_UMV_SH_COUNTER_31_00_OFS   0x0000
+#define GIC_UMV_SH_COUNTER_63_32_OFS   0x0004
+
+/* Masks */
+#define GIC_SH_CONFIG_COUNTSTOP_SHF    28
+#define GIC_SH_CONFIG_COUNTSTOP_MSK    (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
+
+#define GIC_SH_CONFIG_COUNTBITS_SHF    24
+#define GIC_SH_CONFIG_COUNTBITS_MSK    (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
+
+#define GIC_SH_CONFIG_NUMINTRS_SHF     16
+#define GIC_SH_CONFIG_NUMINTRS_MSK     (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
+
+#define GIC_SH_CONFIG_NUMVPES_SHF      0
+#define GIC_SH_CONFIG_NUMVPES_MSK      (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
+
+#define GIC_SH_WEDGE_SET(intr)         (intr | (0x1 << 31))
+#define GIC_SH_WEDGE_CLR(intr)         (intr & ~(0x1 << 31))
+
+#define GIC_MAP_TO_PIN_SHF             31
+#define GIC_MAP_TO_PIN_MSK             (MSK(1) << GIC_MAP_TO_PIN_SHF)
+#define GIC_MAP_TO_NMI_SHF             30
+#define GIC_MAP_TO_NMI_MSK             (MSK(1) << GIC_MAP_TO_NMI_SHF)
+#define GIC_MAP_TO_YQ_SHF              29
+#define GIC_MAP_TO_YQ_MSK              (MSK(1) << GIC_MAP_TO_YQ_SHF)
+#define GIC_MAP_SHF                    0
+#define GIC_MAP_MSK                    (MSK(6) << GIC_MAP_SHF)
+
+/* GIC_VPE_CTL Masks */
+#define GIC_VPE_CTL_FDC_RTBL_SHF       4
+#define GIC_VPE_CTL_FDC_RTBL_MSK       (MSK(1) << GIC_VPE_CTL_FDC_RTBL_SHF)
+#define GIC_VPE_CTL_SWINT_RTBL_SHF     3
+#define GIC_VPE_CTL_SWINT_RTBL_MSK     (MSK(1) << GIC_VPE_CTL_SWINT_RTBL_SHF)
+#define GIC_VPE_CTL_PERFCNT_RTBL_SHF   2
+#define GIC_VPE_CTL_PERFCNT_RTBL_MSK   (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
+#define GIC_VPE_CTL_TIMER_RTBL_SHF     1
+#define GIC_VPE_CTL_TIMER_RTBL_MSK     (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
+#define GIC_VPE_CTL_EIC_MODE_SHF       0
+#define GIC_VPE_CTL_EIC_MODE_MSK       (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
+
+/* GIC_VPE_PEND Masks */
+#define GIC_VPE_PEND_WD_SHF            0
+#define GIC_VPE_PEND_WD_MSK            (MSK(1) << GIC_VPE_PEND_WD_SHF)
+#define GIC_VPE_PEND_CMP_SHF           1
+#define GIC_VPE_PEND_CMP_MSK           (MSK(1) << GIC_VPE_PEND_CMP_SHF)
+#define GIC_VPE_PEND_TIMER_SHF         2
+#define GIC_VPE_PEND_TIMER_MSK         (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
+#define GIC_VPE_PEND_PERFCOUNT_SHF     3
+#define GIC_VPE_PEND_PERFCOUNT_MSK     (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
+#define GIC_VPE_PEND_SWINT0_SHF                4
+#define GIC_VPE_PEND_SWINT0_MSK                (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
+#define GIC_VPE_PEND_SWINT1_SHF                5
+#define GIC_VPE_PEND_SWINT1_MSK                (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
+
+/* GIC_VPE_RMASK Masks */
+#define GIC_VPE_RMASK_WD_SHF           0
+#define GIC_VPE_RMASK_WD_MSK           (MSK(1) << GIC_VPE_RMASK_WD_SHF)
+#define GIC_VPE_RMASK_CMP_SHF          1
+#define GIC_VPE_RMASK_CMP_MSK          (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
+#define GIC_VPE_RMASK_TIMER_SHF                2
+#define GIC_VPE_RMASK_TIMER_MSK                (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
+#define GIC_VPE_RMASK_PERFCNT_SHF      3
+#define GIC_VPE_RMASK_PERFCNT_MSK      (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
+#define GIC_VPE_RMASK_SWINT0_SHF       4
+#define GIC_VPE_RMASK_SWINT0_MSK       (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
+#define GIC_VPE_RMASK_SWINT1_SHF       5
+#define GIC_VPE_RMASK_SWINT1_MSK       (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
+
+/* GIC_VPE_SMASK Masks */
+#define GIC_VPE_SMASK_WD_SHF           0
+#define GIC_VPE_SMASK_WD_MSK           (MSK(1) << GIC_VPE_SMASK_WD_SHF)
+#define GIC_VPE_SMASK_CMP_SHF          1
+#define GIC_VPE_SMASK_CMP_MSK          (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
+#define GIC_VPE_SMASK_TIMER_SHF                2
+#define GIC_VPE_SMASK_TIMER_MSK                (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
+#define GIC_VPE_SMASK_PERFCNT_SHF      3
+#define GIC_VPE_SMASK_PERFCNT_MSK      (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
+#define GIC_VPE_SMASK_SWINT0_SHF       4
+#define GIC_VPE_SMASK_SWINT0_MSK       (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
+#define GIC_VPE_SMASK_SWINT1_SHF       5
+#define GIC_VPE_SMASK_SWINT1_MSK       (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
+
+/* GIC nomenclature for Core Interrupt Pins. */
+#define GIC_CPU_INT0           0 /* Core Interrupt 2 */
+#define GIC_CPU_INT1           1 /* .                */
+#define GIC_CPU_INT2           2 /* .                */
+#define GIC_CPU_INT3           3 /* .                */
+#define GIC_CPU_INT4           4 /* .                */
+#define GIC_CPU_INT5           5 /* Core Interrupt 7 */
+
+/* Add 2 to convert GIC CPU pin to core interrupt */
+#define GIC_CPU_PIN_OFFSET     2
+
+/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
+#define GIC_CPU_TO_VEC_OFFSET  (2)
+
+/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
+#define GIC_PIN_TO_VEC_OFFSET  (1)
+
+/* Local GIC interrupts. */
+#define GIC_LOCAL_INT_WD       0 /* GIC watchdog */
+#define GIC_LOCAL_INT_COMPARE  1 /* GIC count and compare timer */
+#define GIC_LOCAL_INT_TIMER    2 /* CPU timer interrupt */
+#define GIC_LOCAL_INT_PERFCTR  3 /* CPU performance counter */
+#define GIC_LOCAL_INT_SWINT0   4 /* CPU software interrupt 0 */
+#define GIC_LOCAL_INT_SWINT1   5 /* CPU software interrupt 1 */
+#define GIC_LOCAL_INT_FDC      6 /* CPU fast debug channel */
+#define GIC_NUM_LOCAL_INTRS    7
+
+/* Convert between local/shared IRQ number and GIC HW IRQ number. */
+#define GIC_LOCAL_HWIRQ_BASE   0
+#define GIC_LOCAL_TO_HWIRQ(x)  (GIC_LOCAL_HWIRQ_BASE + (x))
+#define GIC_HWIRQ_TO_LOCAL(x)  ((x) - GIC_LOCAL_HWIRQ_BASE)
+#define GIC_SHARED_HWIRQ_BASE  GIC_NUM_LOCAL_INTRS
+#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
+#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
+
+#include <linux/clocksource.h>
+#include <linux/irq.h>
+
+extern unsigned int gic_present;
+extern unsigned int gic_frequency;
+
+extern void gic_init(unsigned long gic_base_addr,
+       unsigned long gic_addrspace_size, unsigned int cpu_vec,
+       unsigned int irqbase);
+extern void gic_clocksource_init(unsigned int);
+extern cycle_t gic_read_count(void);
+extern unsigned int gic_get_count_width(void);
+extern cycle_t gic_read_compare(void);
+extern void gic_write_compare(cycle_t cnt);
+extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
+extern void gic_send_ipi(unsigned int intr);
+extern unsigned int plat_ipi_call_int_xlate(unsigned int);
+extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
+extern unsigned int gic_get_timer_pending(void);
+extern int gic_get_c0_compare_int(void);
+extern int gic_get_c0_perfcount_int(void);
+#endif /* _ASM_GICREGS_H */