arm64: dts: uniphier: use clock/reset controllers
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Mon, 29 Aug 2016 22:50:50 +0000 (07:50 +0900)
committerMasahiro Yamada <yamada.masahiro@socionext.com>
Tue, 30 Aug 2016 20:28:44 +0000 (05:28 +0900)
The UniPhier reset controller driver has been merged.  Enable it.
Also, replace the fixed-rate clocks with the dedicated clock
drivers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi

index 852feab..305223e 100644 (file)
                        #clock-cells = <0>;
                        clock-frequency = <25000000>;
                };
-
-               uart_clk: uart_clk {
-                       #clock-cells = <0>;
-                       compatible = "fixed-clock";
-                       clock-frequency = <58820000>;
-               };
-
-               i2c_clk: i2c_clk {
-                       #clock-cells = <0>;
-                       compatible = "fixed-clock";
-                       clock-frequency = <50000000>;
-               };
        };
 
        timer {
                        interrupts = <0 33 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_uart0>;
-                       clocks = <&uart_clk>;
+                       clocks = <&peri_clk 0>;
                };
 
                serial1: serial@54006900 {
                        interrupts = <0 35 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_uart1>;
-                       clocks = <&uart_clk>;
+                       clocks = <&peri_clk 1>;
                };
 
                serial2: serial@54006a00 {
                        interrupts = <0 37 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_uart2>;
-                       clocks = <&uart_clk>;
+                       clocks = <&peri_clk 2>;
                };
 
                serial3: serial@54006b00 {
                        interrupts = <0 177 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_uart3>;
-                       clocks = <&uart_clk>;
+                       clocks = <&peri_clk 3>;
                };
 
                i2c0: i2c@58780000 {
                        interrupts = <0 41 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_i2c0>;
-                       clocks = <&i2c_clk>;
+                       clocks = <&peri_clk 4>;
                        clock-frequency = <100000>;
                };
 
                        interrupts = <0 42 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_i2c1>;
-                       clocks = <&i2c_clk>;
+                       clocks = <&peri_clk 5>;
                        clock-frequency = <100000>;
                };
 
                        #address-cells = <1>;
                        #size-cells = <0>;
                        interrupts = <0 43 4>;
-                       clocks = <&i2c_clk>;
+                       clocks = <&peri_clk 6>;
                        clock-frequency = <400000>;
                };
 
                        interrupts = <0 44 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_i2c3>;
-                       clocks = <&i2c_clk>;
+                       clocks = <&peri_clk 7>;
                        clock-frequency = <100000>;
                };
 
                        interrupts = <0 45 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_i2c4>;
-                       clocks = <&i2c_clk>;
+                       clocks = <&peri_clk 8>;
                        clock-frequency = <100000>;
                };
 
                        #address-cells = <1>;
                        #size-cells = <0>;
                        interrupts = <0 25 4>;
-                       clocks = <&i2c_clk>;
+                       clocks = <&peri_clk 9>;
                        clock-frequency = <400000>;
                };
 
                        reg = <0x59801000 0x400>;
                };
 
+               mioctrl@59810000 {
+                       compatible = "socionext,uniphier-mioctrl",
+                                    "simple-mfd", "syscon";
+                       reg = <0x59810000 0x800>;
+
+                       mio_clk: clock {
+                               compatible = "socionext,uniphier-ld20-mio-clock";
+                               #clock-cells = <1>;
+                       };
+
+                       mio_rst: reset {
+                               compatible = "socionext,uniphier-ld20-mio-reset";
+                               #reset-cells = <1>;
+                       };
+               };
+
+               perictrl@59820000 {
+                       compatible = "socionext,uniphier-perictrl",
+                                    "simple-mfd", "syscon";
+                       reg = <0x59820000 0x200>;
+
+                       peri_clk: clock {
+                               compatible = "socionext,uniphier-ld20-peri-clock";
+                               #clock-cells = <1>;
+                       };
+
+                       peri_rst: reset {
+                               compatible = "socionext,uniphier-ld20-peri-reset";
+                               #reset-cells = <1>;
+                       };
+               };
+
                soc-glue@5f800000 {
                        compatible = "simple-mfd", "syscon";
                        reg = <0x5f800000 0x2000>;
                        #interrupt-cells = <3>;
                        interrupts = <1 9 4>;
                };
+
+               sysctrl@61840000 {
+                       compatible = "socionext,uniphier-sysctrl",
+                                    "simple-mfd", "syscon";
+                       reg = <0x61840000 0x4000>;
+
+                       sys_clk: clock {
+                               compatible = "socionext,uniphier-ld20-clock";
+                               #clock-cells = <1>;
+                       };
+
+                       sys_rst: reset {
+                               compatible = "socionext,uniphier-ld20-reset";
+                               #reset-cells = <1>;
+                       };
+               };
        };
 };