tile PCI RC: tilepro conflict with PCI and RAM addresses

Fix a bug in the tilepro PCI resource allocation code that could make
the bootmem allocator unhappy if 4GB is installed on mshim 0.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>

diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c
index 68b5426..676e155 100644 (file)
--- a/arch/tile/kernel/setup.c
+++ b/arch/tile/kernel/setup.c
@@ -614,11 +614,12 @@ static void __init setup_bootmem_allocator_node(int i)
        /*
         * Throw away any memory aliased by the PCI region.
         */
-       if (pci_reserve_start_pfn < end && pci_reserve_end_pfn > start)
-               reserve_bootmem(PFN_PHYS(pci_reserve_start_pfn),
-                               PFN_PHYS(pci_reserve_end_pfn -
-                                        pci_reserve_start_pfn),
+       if (pci_reserve_start_pfn < end && pci_reserve_end_pfn > start) {
+               start = max(pci_reserve_start_pfn, start);
+               end = min(pci_reserve_end_pfn, end);
+               reserve_bootmem(PFN_PHYS(start), PFN_PHYS(end - start),
                                BOOTMEM_EXCLUSIVE);
+       }
 #endif
 }