PCI: rockchip: Improve the deassert sequence of four reset pins

Per TRM, we need to deassert the four reset pins simultaneously.  Currently
the reset framework doesn't support that so we did it one by one.  It seems
no side effect found but it does impact the state machine of controller, so
sometimes the change speed bit is not set when sending training sequence
from recover state.  After the silicon RTL review from SoC guys, we don't
need to do the sequence recommended by TRM, and could just move the
deassert of mgmt_sticky_rst to the first place.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 91f6fa2..43b765e 100644 (file)
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -449,21 +449,25 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
                return err;
        }
 
-       err = reset_control_deassert(rockchip->core_rst);
+       /*
+        * Please don't reorder the deassert sequence of the following
+        * four reset pins.
+        */
+       err = reset_control_deassert(rockchip->mgmt_sticky_rst);
        if (err) {
-               dev_err(dev, "deassert core_rst err %d\n", err);
+               dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
                return err;
        }
 
-       err = reset_control_deassert(rockchip->mgmt_rst);
+       err = reset_control_deassert(rockchip->core_rst);
        if (err) {
-               dev_err(dev, "deassert mgmt_rst err %d\n", err);
+               dev_err(dev, "deassert core_rst err %d\n", err);
                return err;
        }
 
-       err = reset_control_deassert(rockchip->mgmt_sticky_rst);
+       err = reset_control_deassert(rockchip->mgmt_rst);
        if (err) {
-               dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
+               dev_err(dev, "deassert mgmt_rst err %d\n", err);
                return err;
        }