sh: add AT_HWCAP flag for J-Core cas.l instruction

The J-Core cpu has, as an ISA extension, an atomic compare-and-swap
instruction cas.l which applications need to use (instead the imask or
gusa atomic models, which are fundamentally limited to UP) for
synchronization in order to be compatible with SMP systems. Provide a
hwcap flag so that it's possible to do runtime selection and support
both.

Signed-off-by: Rich Felker <dalias@libc.org>

diff --git a/arch/sh/include/uapi/asm/cpu-features.h b/arch/sh/include/uapi/asm/cpu-features.h
index 694abe4..2f1bc85 100644 (file)
--- a/arch/sh/include/uapi/asm/cpu-features.h
+++ b/arch/sh/include/uapi/asm/cpu-features.h
@@ -22,5 +22,6 @@
 #define CPU_HAS_L2_CACHE       0x0080  /* Secondary cache / URAM */
 #define CPU_HAS_OP32           0x0100  /* 32-bit instruction support */
 #define CPU_HAS_PTEAEX         0x0200  /* PTE ASID Extension support */
+#define CPU_HAS_CAS_L          0x0400  /* cas.l atomic compare-and-swap */
 
 #endif /* __ASM_SH_CPU_FEATURES_H */

diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c
index 1521840..4205f6d 100644 (file)
--- a/arch/sh/kernel/cpu/sh2/probe.c
+++ b/arch/sh/kernel/cpu/sh2/probe.c
@@ -57,6 +57,8 @@ void __ref cpu_probe(void)
        boot_cpu_data.dcache.entry_shift        = 5;
        boot_cpu_data.dcache.linesz             = 32;
        boot_cpu_data.dcache.flags              = 0;
+
+       boot_cpu_data.flags |= CPU_HAS_CAS_L;
 #else
        /*
         * SH-2 doesn't have separate caches