ath9k_hw: Enable hw PLL power save for AR9565
authorRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Thu, 25 Oct 2012 11:46:51 +0000 (17:16 +0530)
committerJohn W. Linville <linville@tuxdriver.com>
Mon, 29 Oct 2012 19:30:31 +0000 (15:30 -0400)
This reduced the power consumption to half in full and network sleep.

Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/ar9003_hw.c
drivers/net/wireless/ath/ath9k/ar9565_1p0_initvals.h

index 0a6b7a3..0693cd9 100644 (file)
@@ -328,9 +328,9 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
                               ar9565_1p0_Modes_lowest_ob_db_tx_gain_table);
 
                INIT_INI_ARRAY(&ah->iniPcieSerdes,
-                              ar9565_1p0_pciephy_pll_on_clkreq_disable_L1);
+                              ar9565_1p0_pciephy_clkreq_disable_L1);
                INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
-                              ar9565_1p0_pciephy_pll_on_clkreq_disable_L1);
+                              ar9565_1p0_pciephy_clkreq_disable_L1);
 
                INIT_INI_ARRAY(&ah->iniModesFastClock,
                                ar9565_1p0_modes_fast_clock);
index 843e79f..0c2ac0c 100644 (file)
@@ -768,9 +768,9 @@ static const u32 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table[][5] = {
        {0x00016054, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
 };
 
-static const u32 ar9565_1p0_pciephy_pll_on_clkreq_disable_L1[][2] = {
+static const u32 ar9565_1p0_pciephy_clkreq_disable_L1[][2] = {
        /* Addr      allmodes  */
-       {0x00018c00, 0x18212ede},
+       {0x00018c00, 0x18213ede},
        {0x00018c04, 0x000801d8},
        {0x00018c08, 0x0003780c},
 };