Merge tag 'drm-intel-next-2016-03-30' of git://anongit.freedesktop.org/drm-intel...

- VBT code refactor for a clean split between parsing&using of firmware
  information (Jani)
- untangle the pll computation code, and splitting up the monster
  i9xx_crtc_compute_clocks (Ander)
- dsi support for bxt (Jani, Shashank Sharma and others)
- color manager (i.e. de-gamma, color conversion matrix & gamma support) from
  Lionel Landwerlin
- Vulkan hsw support in the command parser (Jordan Justen)
- large-scale renaming of intel_engine_cs variables/parameters to avoid the epic
  ring vs. engine confusion introduced in gen8 (Tvrtko Ursulin)
- few atomic patches from Maarten&Matt, big one is two-stage wm programming on ilk-bdw
- refactor driver load and add infrastructure to inject load failures for
  testing, from Imre
- various small things all over

* tag 'drm-intel-next-2016-03-30' of git://anongit.freedesktop.org/drm-intel: (179 commits)
  drm/i915: Update DRIVER_DATE to 20160330
  drm/i915: Call intel_dp_mst_resume() before resuming displays
  drm/i915: Fix races on fbdev
  drm/i915: remove unused dev_priv->render_reclock_avail
  drm/i915: move sdvo mappings to vbt data
  drm/i915: move edp low vswing config to vbt data
  drm/i915: use a substruct in vbt data for edp
  drm/i915: replace for_each_engine()
  drm/i915: introduce for_each_engine_id()
  drm/i915/bxt: Fix DSI HW state readout
  drm/i915: Remove vblank wait from hsw_enable_ips, v2.
  drm/i915: Tidy aliasing_gtt_bind_vma()
  drm/i915: Split PNV version of crtc_compute_clock()
  drm/i915: Split g4x_crtc_compute_clock()
  drm/i915: Split i8xx_crtc_compute_clock()
  drm/i915: Split CHV and VLV specific crtc_compute_clock() hooks
  drm/i915: Merge ironlake_compute_clocks() and ironlake_crtc_compute_clock()
  drm/i915: Move fp divisor calculation into ironlake_compute_dpll()
  drm/i915: Pass crtc_state->dpll directly to ->find_dpll()
  drm/i915: Simplify ironlake_crtc_compute_clock() CPU eDP case
  ...

diff --combined drivers/gpu/drm/i915/i915_drv.c
index 4c0dd35,f73b4f7..349e17c
--- 1/drivers/gpu/drm/i915/i915_drv.c
--- 2/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@@ -66,6 -66,11 +66,11 @@@ static struct drm_driver driver
  #define IVB_CURSOR_OFFSETS \
        .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  
+ #define BDW_COLORS \
+       .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
+ #define CHV_COLORS \
+       .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
+ 
  static const struct intel_device_info intel_i830_info = {
        .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
        .has_overlay = 1, .overlay_needs_physical = 1,
@@@ -288,24 -293,28 +293,28 @@@ static const struct intel_device_info i
        .is_mobile = 1,
  };
  
+ #define BDW_FEATURES \
+       HSW_FEATURES, \
+       BDW_COLORS
+ 
  static const struct intel_device_info intel_broadwell_d_info = {
-       HSW_FEATURES,
+       BDW_FEATURES,
        .gen = 8,
  };
  
  static const struct intel_device_info intel_broadwell_m_info = {
-       HSW_FEATURES,
+       BDW_FEATURES,
        .gen = 8, .is_mobile = 1,
  };
  
  static const struct intel_device_info intel_broadwell_gt3d_info = {
-       HSW_FEATURES,
+       BDW_FEATURES,
        .gen = 8,
        .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
  };
  
  static const struct intel_device_info intel_broadwell_gt3m_info = {
-       HSW_FEATURES,
+       BDW_FEATURES,
        .gen = 8, .is_mobile = 1,
        .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
  };
@@@ -318,16 -327,17 +327,17 @@@ static const struct intel_device_info i
        .display_mmio_offset = VLV_DISPLAY_BASE,
        GEN_CHV_PIPEOFFSETS,
        CURSOR_OFFSETS,
+       CHV_COLORS,
  };
  
  static const struct intel_device_info intel_skylake_info = {
-       HSW_FEATURES,
+       BDW_FEATURES,
        .is_skylake = 1,
        .gen = 9,
  };
  
  static const struct intel_device_info intel_skylake_gt3_info = {
-       HSW_FEATURES,
+       BDW_FEATURES,
        .is_skylake = 1,
        .gen = 9,
        .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
@@@ -345,17 -355,18 +355,18 @@@ static const struct intel_device_info i
        .has_fbc = 1,
        GEN_DEFAULT_PIPEOFFSETS,
        IVB_CURSOR_OFFSETS,
+       BDW_COLORS,
  };
  
  static const struct intel_device_info intel_kabylake_info = {
-       HSW_FEATURES,
+       BDW_FEATURES,
        .is_preliminary = 1,
        .is_kabylake = 1,
        .gen = 9,
  };
  
  static const struct intel_device_info intel_kabylake_gt3_info = {
-       HSW_FEATURES,
+       BDW_FEATURES,
        .is_preliminary = 1,
        .is_kabylake = 1,
        .gen = 9,
@@@ -504,6 -515,7 +515,7 @@@ void intel_detect_pch(struct drm_devic
                                WARN_ON(!IS_SKYLAKE(dev) &&
                                        !IS_KABYLAKE(dev));
                        } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
+                                  (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
                                   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
                                    pch->subsystem_vendor == 0x1af4 &&
                                    pch->subsystem_device == 0x1100)) {
@@@ -758,10 -770,10 +770,10 @@@ static int i915_drm_resume(struct drm_d
                dev_priv->display.hpd_irq_setup(dev);
        spin_unlock_irq(&dev_priv->irq_lock);
  
-       intel_display_resume(dev);
- 
        intel_dp_mst_resume(dev);
  
+       intel_display_resume(dev);
+ 
        /*
         * ... but also need to make sure that hotplug processing
         * doesn't cause havoc. Like in the driver load code we don't
@@@ -881,7 -893,7 +893,7 @@@ int i915_reset(struct drm_device *dev
  
        simulated = dev_priv->gpu_error.stop_rings != 0;
  
-       ret = intel_gpu_reset(dev);
+       ret = intel_gpu_reset(dev, ALL_ENGINES);
  
        /* Also reset the gpu hangman. */
        if (simulated) {
@@@ -1742,8 -1754,10 +1754,8 @@@ static int __init i915_init(void
        if (i915.modeset == 0)
                driver.driver_features &= ~DRIVER_MODESET;
  
 -#ifdef CONFIG_VGA_CONSOLE
        if (vgacon_text_force() && i915.modeset == -1)
                driver.driver_features &= ~DRIVER_MODESET;
 -#endif
  
        if (!(driver.driver_features & DRIVER_MODESET)) {
                /* Silently fail loading to not upset userspace. */

diff --combined drivers/gpu/drm/i915/i915_gem_userptr.c
index 6be40f3,54088a4..291a939
--- 1/drivers/gpu/drm/i915/i915_gem_userptr.c
--- 2/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@@ -503,11 -503,11 +503,11 @@@ __i915_gem_userptr_get_pages_worker(str
  
                down_read(&mm->mmap_sem);
                while (pinned < npages) {
 -                      ret = get_user_pages(work->task, mm,
 -                                           obj->userptr.ptr + pinned * PAGE_SIZE,
 -                                           npages - pinned,
 -                                           !obj->userptr.read_only, 0,
 -                                           pvec + pinned, NULL);
 +                      ret = get_user_pages_remote(work->task, mm,
 +                                      obj->userptr.ptr + pinned * PAGE_SIZE,
 +                                      npages - pinned,
 +                                      !obj->userptr.read_only, 0,
 +                                      pvec + pinned, NULL);
                        if (ret < 0)
                                break;
  
@@@ -758,6 -758,13 +758,13 @@@ i915_gem_userptr_ioctl(struct drm_devic
        int ret;
        u32 handle;
  
+       if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) {
+               /* We cannot support coherent userptr objects on hw without
+                * LLC and broken snooping.
+                */
+               return -ENODEV;
+       }
+ 
        if (args->flags & ~(I915_USERPTR_READ_ONLY |
                            I915_USERPTR_UNSYNCHRONIZED))
                return -EINVAL;