--- /dev/null
+* Abilis TB10x GPIO controller
+
+Required Properties:
+- compatible: Should be "abilis,tb10x-gpio"
+- reg: Address and length of the register set for the device
+- gpio-controller: Marks the device node as a gpio controller.
+- #gpio-cells: Should be <2>. The first cell is the pin number and the
+ second cell is used to specify optional parameters:
+ - bit 0 specifies polarity (0 for normal, 1 for inverted).
+- abilis,ngpio: the number of GPIO pins this driver controls.
+
+Optional Properties:
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Should be <1>. Interrupts are triggered on both edges.
+- interrupts: Defines the interrupt line connecting this GPIO controller to
+ its parent interrupt controller.
+- interrupt-parent: Defines the parent interrupt controller.
+
+GPIO ranges are specified as described in
+Documentation/devicetree/bindings/gpio/gpio.txt
+
+Example:
+
+ gpioa: gpio@FF140000 {
+ compatible = "abilis,tb10x-gpio";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&tb10x_ictl>;
+ interrupts = <27 2>;
+ reg = <0xFF140000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ abilis,ngpio = <3>;
+ gpio-ranges = <&iomux 0 0 0>;
+ gpio-ranges-group-names = "gpioa_pins";
+ };
contains information structures as follows:
gpio-range-list ::= <single-gpio-range> [gpio-range-list]
- single-gpio-range ::=
+ single-gpio-range ::= <numeric-gpio-range> | <named-gpio-range>
+ numeric-gpio-range ::=
<pinctrl-phandle> <gpio-base> <pinctrl-base> <count>
+ named-gpio-range ::= <pinctrl-phandle> <gpio-base> '<0 0>'
gpio-phandle : phandle to pin controller node.
gpio-base : Base GPIO ID in the GPIO controller
pinctrl-base : Base pinctrl pin ID in the pin controller
The "pin controller node" mentioned above must conform to the bindings
described in ../pinctrl/pinctrl-bindings.txt.
+In case named gpio ranges are used (ranges with both <pinctrl-base> and
+<count> set to 0), the property gpio-ranges-group-names contains one string
+for every single-gpio-range in gpio-ranges:
+ gpiorange-names-list ::= <gpiorange-name> [gpiorange-names-list]
+ gpiorange-name : Name of the pingroup associated to the GPIO range in
+ the respective pin controller.
+
+Elements of gpiorange-names-list corresponding to numeric ranges contain
+the empty string. Elements of gpiorange-names-list corresponding to named
+ranges contain the name of a pin group defined in the respective pin
+controller. The number of pins/GPIOs in the range is the number of pins in
+that pin group.
+
Previous versions of this binding required all pin controller nodes that
were referenced by any gpio-ranges property to contain a property named
#gpio-range-cells with value <3>. This requirement is now deprecated.
compatibility reasons, and would still be required even in new device
trees that need to be compatible with older software.
-Example:
+Example 1:
qe_pio_e: gpio-controller@1460 {
#gpio-cells = <2>;
Here, a single GPIO controller has GPIOs 0..9 routed to pin controller
pinctrl1's pins 20..29, and GPIOs 10..19 routed to pin controller pinctrl2's
pins 50..59.
+
+Example 2:
+
+ gpio_pio_i: gpio-controller@14B0 {
+ #gpio-cells = <2>;
+ compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
+ reg = <0x1480 0x18>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl1 0 20 10>,
+ <&pinctrl2 10 0 0>,
+ <&pinctrl1 15 0 10>,
+ <&pinctrl2 25 0 0>;
+ gpio-ranges-group-names = "",
+ "foo",
+ "",
+ "bar";
+ };
+
+Here, three GPIO ranges are defined wrt. two pin controllers. pinctrl1 GPIO
+ranges are defined using pin numbers whereas the GPIO ranges wrt. pinctrl2
+are named "foo" and "bar".
--- /dev/null
+Abilis Systems TB10x pin controller
+===================================
+
+Required properties
+-------------------
+
+- compatible: should be "abilis,tb10x-iomux";
+- reg: should contain the physical address and size of the pin controller's
+ register range.
+
+
+Function definitions
+--------------------
+
+Functions are defined (and referenced) by sub-nodes of the pin controller.
+Every sub-node defines exactly one function (implying a set of pins).
+Every function is associated to one named pin group inside the pin controller
+driver and these names are used to associate pin group predefinitions to pin
+controller sub-nodes.
+
+Required function definition subnode properties:
+ - abilis,function: should be set to the name of the function's pin group.
+
+The following pin groups are available:
+ - GPIO ports: gpioa, gpiob, gpioc, gpiod, gpioe, gpiof, gpiog,
+ gpioh, gpioi, gpioj, gpiok, gpiol, gpiom, gpion
+ - Serial TS input ports: mis0, mis1, mis2, mis3, mis4, mis5, mis6, mis7
+ - Parallel TS input ports: mip1, mip3, mip5, mip7
+ - Serial TS output ports: mos0, mos1, mos2, mos3
+ - Parallel TS output port: mop
+ - CI+ port: ciplus
+ - CableCard (Mcard) port: mcard
+ - Smart card ports: stc0, stc1
+ - UART ports: uart0, uart1
+ - SPI ports: spi1, spi3
+ - JTAG: jtag
+
+All other ports of the chip are not multiplexed and thus not managed by this
+driver.
+
+
+GPIO ranges definition
+----------------------
+
+The named pin groups of GPIO ports can be used to define GPIO ranges as
+explained in Documentation/devicetree/bindings/gpio/gpio.txt.
+
+
+Example
+-------
+
+iomux: iomux@FF10601c {
+ compatible = "abilis,tb10x-iomux";
+ reg = <0xFF10601c 0x4>;
+ pctl_gpio_a: pctl-gpio-a {
+ abilis,function = "gpioa";
+ };
+ pctl_uart0: pctl-uart0 {
+ abilis,function = "uart0";
+ };
+};
+uart@FF100000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xFF100000 0x100>;
+ clock-frequency = <166666666>;
+ interrupts = <25 1>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pctl_uart0>;
+};
+gpioa: gpio@FF140000 {
+ compatible = "abilis,tb10x-gpio";
+ reg = <0xFF140000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpio = <3>;
+ gpio-ranges = <&iomux 0 0>;
+ gpio-ranges-group-names = "gpioa";
+};
such as pull-up, multi drive, etc.
Required properties for iomux controller:
-- compatible: "atmel,at91rm9200-pinctrl"
+- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
configured in this periph mode. All the periph and bank need to be describe.
Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
Required properties for pin configuration node:
-- fsl,pins: two integers array, represents a group of pins mux and config
- setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
- pin working on a specific function, which consists of a tuple of
- <mux_reg conf_reg input_reg mux_val input_val>. CONFIG is the pad setting
- value like pull-up on this pin.
+- fsl,pins: each entry consists of 6 integers and represents the mux and config
+ setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
+ input_val> are specified using a PIN_FUNC_ID macro, which can be found in
+ imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
+ the pad setting value like pull-up on this pin. And that's why fsl,pins entry
+ looks like <PIN_FUNC_ID CONFIG> in the example below.
Bits used for CONFIG:
NO_PAD_CTL(1 << 31): indicate this pin does not need config.
/* shared pinctrl settings */
usdhc4 {
pinctrl_usdhc4_1: usdhc4grp-1 {
- fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
- 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
- 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
- 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
- 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
- 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
- 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
- 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
- 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
- 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
- };
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ >;
};
....
};
0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed,
80Ohm driver strength and Fast Slew Rate.
User should refer to each SoC spec to set the correct value.
-
-TODO: when dtc macro support is available, we can change above raw data
-to dt macro which can get better readability in dts file.
--- /dev/null
+* Freescale IMX27 IOMUX Controller
+
+Required properties:
+- compatible: "fsl,imx27-iomuxc"
+
+The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.
+
+Required properties for pin configuration node:
+- fsl,pins: three integers array, represents a group of pins mux and config
+ setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
+
+ PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
+ configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
+ number on the specific port (between 0 and 31).
+
+ MUX_ID is
+ function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
+
+ function value is used to select the pin function.
+ Possible values:
+ 0 - Primary function
+ 1 - Alternate function
+ 2 - GPIO
+ Registers: GIUS (GPIO In Use), GPR (General Purpose Register)
+
+ direction defines the data direction of the pin.
+ Possible values:
+ 0 - Input
+ 1 - Output
+ Register: DDIR
+
+ gpio_oconf configures the gpio submodule output signal. This does not
+ have any effect unless GPIO function is selected. A/B/C_IN are output
+ signals of function blocks A,B and C. Specific function blocks are
+ described in the reference manual.
+ Possible values:
+ 0 - A_IN
+ 1 - B_IN
+ 2 - C_IN
+ 3 - Data Register
+ Registers: OCR1, OCR2
+
+ gpio_iconfa/b configures the gpio submodule input to functionblocks A and
+ B. GPIO function should be selected if this is configured.
+ Possible values:
+ 0 - GPIO_IN
+ 1 - Interrupt Status Register
+ 2 - Pulldown
+ 3 - Pullup
+ Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
+
+ CONFIG can be 0 or 1, meaning Pullup disable/enable.
+
+
+
+Example:
+
+iomuxc: iomuxc@10015000 {
+ compatible = "fsl,imx27-iomuxc";
+ reg = <0x10015000 0x600>;
+
+ uart {
+ pinctrl_uart1: uart-1 {
+ fsl,pins = <
+ 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
+ 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
+ 0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
+ 0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
+ >;
+ };
+
+ ...
+ };
+};
+
+
+For convenience there are macros defined in imx27-pinfunc.h which provide PIN
+and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
+are defined in the i.MX27 reference manual.
+
+The above example using macros:
+
+iomuxc: iomuxc@10015000 {
+ compatible = "fsl,imx27-iomuxc";
+ reg = <0x10015000 0x600>;
+
+ uart {
+ pinctrl_uart1: uart-1 {
+ fsl,pins = <
+ MX27_PAD_UART1_TXD__UART1_TXD 0x0
+ MX27_PAD_UART1_RXD__UART1_RXD 0x0
+ MX27_PAD_UART1_CTS__UART1_CTS 0x0
+ MX27_PAD_UART1_RTS__UART1_RTS 0x0
+ >;
+ };
+
+ ...
+ };
+};
Required: pins
Options: function, bias-disable, bias-pull-up, bias-pull-down,
- bias-pin-default, drive-open-drain.
+ drive-open-drain.
Note that many of these properties are only valid for certain specific pins.
See the Palmas device datasheet for complete details regarding which pins
Required properties for iomux controller:
- compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
"rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
+ - reg: first element is the general register space of the iomux controller
+ second element is the separate pull register space of the rk3188
Required properties for gpio sub nodes:
- - compatible: "rockchip,gpio-bank"
+ - compatible: "rockchip,gpio-bank", "rockchip,rk3188-gpio-bank0"
- reg: register of the gpio bank (different than the iomux registerset)
+ second element: separate pull register for rk3188 bank0
- interrupts: base interrupt of the gpio bank in the interrupt controller
- clocks: clock that drives this bank
- gpio-controller: identifies the node as a gpio controller and pin bank.
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
};
+
+Example for rk3188:
+
+ pinctrl@20008000 {
+ compatible = "rockchip,rk3188-pinctrl";
+ reg = <0x20008000 0xa0>,
+ <0x20008164 0x1a0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio0@0x2000a000 {
+ compatible = "rockchip,rk3188-gpio-bank0";
+ reg = <0x2000a000 0x100>,
+ <0x20004064 0x8>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_gates8 9>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio1@0x2003c000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x2003c000 0x100>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_gates8 10>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ ...
+
+ };
.gc = &chip;
};
-In this case the pin_base property will be ignored.
+In this case the pin_base property will be ignored. If the name of a pin
+group is known, the pins and npins elements of the above structure can be
+initialised using the function pinctrl_get_group_pins(), e.g. for pin
+group "foo":
+
+pinctrl_get_group_pins(pctl, "foo", &gpio_range.pins, &gpio_range.npins);
When GPIO-specific functions in the pin control subsystem are called, these
ranges will be used to look up the appropriate pin controller by inspecting
sirf,function = "usb1_utmi_drvbus";
};
};
+ usb1_dp_dn_pins_a: usb1_dp_dn@0 {
+ usb1_dp_dn {
+ sirf,pins = "usb1_dp_dngrp";
+ sirf,function = "usb1_dp_dn";
+ };
+ };
+ uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
+ uart1_route_io_usb1 {
+ sirf,pins = "uart1_route_io_usb1grp";
+ sirf,function = "uart1_route_io_usb1";
+ };
+ };
warm_rst_pins_a: warm_rst@0 {
warm_rst {
sirf,pins = "warm_rstgrp";
sirf,function = "uart0";
};
};
+ uart0_noflow_pins_a: uart0@1 {
+ uart {
+ sirf,pins = "uart0_nostreamctrlgrp";
+ sirf,function = "uart0_nostreamctrl";
+ };
+ };
uart1_pins_a: uart1@0 {
uart {
sirf,pins = "uart1grp";
sirf,function = "usp0";
};
};
+ usp0_uart_nostreamctrl_pins_a: usp0@1 {
+ usp0 {
+ sirf,pins =
+ "usp0_uart_nostreamctrl_grp";
+ sirf,function =
+ "usp0_uart_nostreamctrl";
+ };
+ };
usp1_pins_a: usp1@0 {
usp1 {
sirf,pins = "usp1grp";
sirf,function = "usp1";
};
};
+ usp1_uart_nostreamctrl_pins_a: usp1@1 {
+ usp1 {
+ sirf,pins =
+ "usp1_uart_nostreamctrl_grp";
+ sirf,function =
+ "usp1_uart_nostreamctrl";
+ };
+ };
usp2_pins_a: usp2@0 {
usp2 {
sirf,pins = "usp2grp";
sirf,function = "usp2";
};
};
+ usp2_uart_nostreamctrl_pins_a: usp2@1 {
+ usp2 {
+ sirf,pins =
+ "usp2_uart_nostreamctrl_grp";
+ sirf,function =
+ "usp2_uart_nostreamctrl";
+ };
+ };
usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
usb0_utmi_drvbus {
sirf,pins = "usb0_utmi_drvbusgrp";
sirf,function = "usb1_utmi_drvbus";
};
};
+ usb1_dp_dn_pins_a: usb1_dp_dn@0 {
+ usb1_dp_dn {
+ sirf,pins = "usb1_dp_dngrp";
+ sirf,function = "usb1_dp_dn";
+ };
+ };
+ uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
+ uart1_route_io_usb1 {
+ sirf,pins = "uart1_route_io_usb1grp";
+ sirf,function = "uart1_route_io_usb1";
+ };
+ };
warm_rst_pins_a: warm_rst@0 {
warm_rst {
sirf,pins = "warm_rstgrp";
config ZONE_DMA
def_bool y
+config GENERIC_GPIO
+ def_bool y
+
config FORCE_MAX_ZONEORDER
int
default "14"
depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
default y
+config GPIO_ADI
+ def_bool y
+ depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561)
+
+config PINCTRL
+ def_bool y
+ depends on BF54x || BF60x
+
config MEM_MT48LC64M4A2FB_7E
bool
depends on (BFIN533_STAMP)
#ifndef __ASSEMBLY__
+#ifndef CONFIG_PINCTRL
+
#include <linux/compiler.h>
-#include <linux/gpio.h>
+#include <asm/blackfin.h>
+#include <asm/portmux.h>
+#include <asm/irq_handler.h>
/***********************************************************
*
* MODIFICATION HISTORY :
**************************************************************/
-#if !BFIN_GPIO_PINT
void set_gpio_dir(unsigned, unsigned short);
void set_gpio_inen(unsigned, unsigned short);
void set_gpio_polar(unsigned, unsigned short);
unsigned short dummy16;
unsigned short inen;
};
-#endif
#ifdef BFIN_SPECIAL_GPIO_BANKS
void bfin_special_gpio_free(unsigned gpio);
#endif
#ifdef CONFIG_PM
-int bfin_pm_standby_ctrl(unsigned ctrl);
+void bfin_gpio_pm_hibernate_restore(void);
+void bfin_gpio_pm_hibernate_suspend(void);
+int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
+int bfin_gpio_pm_standby_ctrl(unsigned ctrl);
static inline int bfin_pm_standby_setup(void)
{
- return bfin_pm_standby_ctrl(1);
+ return bfin_gpio_pm_standby_ctrl(1);
}
static inline void bfin_pm_standby_restore(void)
{
- bfin_pm_standby_ctrl(0);
+ bfin_gpio_pm_standby_ctrl(0);
}
-void bfin_gpio_pm_hibernate_restore(void);
-void bfin_gpio_pm_hibernate_suspend(void);
-void bfin_pint_suspend(void);
-void bfin_pint_resume(void);
-
-# if !BFIN_GPIO_PINT
-int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
struct gpio_port_s {
unsigned short data;
unsigned short reserved;
unsigned short mux;
};
-# endif
#endif /*CONFIG_PM*/
/***********************************************************
*************************************************************
* MODIFICATION HISTORY :
**************************************************************/
-
-int bfin_gpio_request(unsigned gpio, const char *label);
-void bfin_gpio_free(unsigned gpio);
int bfin_gpio_irq_request(unsigned gpio, const char *label);
void bfin_gpio_irq_free(unsigned gpio);
-int bfin_gpio_direction_input(unsigned gpio);
-int bfin_gpio_direction_output(unsigned gpio, int value);
-int bfin_gpio_get_value(unsigned gpio);
-void bfin_gpio_set_value(unsigned gpio, int value);
+void bfin_gpio_irq_prepare(unsigned gpio);
+
+static inline int irq_to_gpio(unsigned irq)
+{
+ return irq - GPIO_IRQ_BASE;
+}
+#endif /* CONFIG_PINCTRL */
#include <asm/irq.h>
#include <asm/errno.h>
-#ifdef CONFIG_GPIOLIB
#include <asm-generic/gpio.h> /* cansleep wrappers */
static inline int gpio_get_value(unsigned int gpio)
{
- if (gpio < MAX_BLACKFIN_GPIOS)
- return bfin_gpio_get_value(gpio);
- else
- return __gpio_get_value(gpio);
+ return __gpio_get_value(gpio);
}
static inline void gpio_set_value(unsigned int gpio, int value)
{
- if (gpio < MAX_BLACKFIN_GPIOS)
- bfin_gpio_set_value(gpio, value);
- else
- __gpio_set_value(gpio, value);
+ __gpio_set_value(gpio, value);
}
static inline int gpio_cansleep(unsigned int gpio)
{
return __gpio_to_irq(gpio);
}
-
-#else /* !CONFIG_GPIOLIB */
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
- return bfin_gpio_request(gpio, label);
-}
-
-static inline void gpio_free(unsigned gpio)
-{
- return bfin_gpio_free(gpio);
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
- return bfin_gpio_direction_input(gpio);
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
- return bfin_gpio_direction_output(gpio, value);
-}
-
-static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
-{
- return -EINVAL;
-}
-
-static inline int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
-{
- int err;
-
- err = bfin_gpio_request(gpio, label);
- if (err)
- return err;
-
- if (flags & GPIOF_DIR_IN)
- err = bfin_gpio_direction_input(gpio);
- else
- err = bfin_gpio_direction_output(gpio,
- (flags & GPIOF_INIT_HIGH) ? 1 : 0);
-
- if (err)
- bfin_gpio_free(gpio);
-
- return err;
-}
-
-static inline int gpio_request_array(const struct gpio *array, size_t num)
-{
- int i, err;
-
- for (i = 0; i < num; i++, array++) {
- err = gpio_request_one(array->gpio, array->flags, array->label);
- if (err)
- goto err_free;
- }
- return 0;
-
-err_free:
- while (i--)
- bfin_gpio_free((--array)->gpio);
- return err;
-}
-
-static inline void gpio_free_array(const struct gpio *array, size_t num)
-{
- while (num--)
- bfin_gpio_free((array++)->gpio);
-}
-
-static inline int __gpio_get_value(unsigned gpio)
-{
- return bfin_gpio_get_value(gpio);
-}
-
-static inline void __gpio_set_value(unsigned gpio, int value)
-{
- return bfin_gpio_set_value(gpio, value);
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
- return __gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
- return __gpio_set_value(gpio, value);
-}
-
-static inline int gpio_to_irq(unsigned gpio)
-{
- if (likely(gpio < MAX_BLACKFIN_GPIOS))
- return gpio + GPIO_IRQ_BASE;
-
- return -EINVAL;
-}
-
-#include <asm-generic/gpio.h> /* cansleep wrappers */
-#endif /* !CONFIG_GPIOLIB */
-
-static inline int irq_to_gpio(unsigned irq)
-{
- return (irq - GPIO_IRQ_BASE);
-}
-
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_BLACKFIN_GPIO_H__ */
#define P_MAYSHARE 0x2000
#define P_DONTCARE 0x1000
-
+#ifdef CONFIG_PINCTRL
+#include <asm/irq_handler.h>
+
+#define gpio_pint_regs bfin_pint_regs
+#define adi_internal_set_wake bfin_internal_set_wake
+
+#define peripheral_request(per, label) 0
+#define peripheral_free(per)
+#define peripheral_request_list(per, label) \
+ (pdev ? (IS_ERR(devm_pinctrl_get_select_default(&pdev->dev)) \
+ ? -EINVAL : 0) : 0)
+#define peripheral_free_list(per)
+#else
int peripheral_request(unsigned short per, const char *label);
void peripheral_free(unsigned short per);
int peripheral_request_list(const unsigned short per[], const char *label);
void peripheral_free_list(const unsigned short per[]);
+#endif
-#include <asm/gpio.h>
+#include <linux/err.h>
+#include <linux/pinctrl/pinctrl.h>
#include <mach/portmux.h>
+#include <linux/gpio.h>
#ifndef P_SPORT2_TFS
#define P_SPORT2_TFS P_UNDEF
obj-y := \
entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \
- fixed_code.o reboot.o bfin_gpio.o bfin_dma.o \
+ fixed_code.o reboot.o bfin_dma.o \
exception.o dumpstack.o
ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y)
obj-y += time.o
endif
+obj-$(CONFIG_GPIO_ADI) += bfin_gpio.o
obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
obj-$(CONFIG_FUNCTION_TRACER) += ftrace-entry.o
obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
/* EMAC RMII Port Mux */
#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
Select this to support Aeroflex Gaisler GRGPIO cores from the GRLIB
VHDL IP core library.
+config GPIO_TB10X
+ bool
+ select OF_GPIO
+
comment "I2C GPIO expanders:"
config GPIO_ARIZONA
obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o
obj-$(CONFIG_GPIO_STP_XWAY) += gpio-stp-xway.o
obj-$(CONFIG_GPIO_SX150X) += gpio-sx150x.o
+obj-$(CONFIG_GPIO_TB10X) += gpio-tb10x.o
obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o
obj-$(CONFIG_ARCH_TEGRA) += gpio-tegra.o
obj-$(CONFIG_GPIO_TIMBERDALE) += gpio-timberdale.o
--- /dev/null
+/* Abilis Systems MODULE DESCRIPTION
+ *
+ * Copyright (C) Abilis Systems 2013
+ *
+ * Authors: Sascha Leuenberger <sascha.leuenberger@abilis.com>
+ * Christian Ruppert <christian.ruppert@abilis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/slab.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_gpio.h>
+#include <linux/spinlock.h>
+#include <linux/bitops.h>
+#include <linux/pinctrl/consumer.h>
+
+#define TB10X_GPIO_DIR_IN (0x00000000)
+#define TB10X_GPIO_DIR_OUT (0x00000001)
+#define OFFSET_TO_REG_DDR (0x00)
+#define OFFSET_TO_REG_DATA (0x04)
+#define OFFSET_TO_REG_INT_EN (0x08)
+#define OFFSET_TO_REG_CHANGE (0x0C)
+#define OFFSET_TO_REG_WRMASK (0x10)
+#define OFFSET_TO_REG_INT_TYPE (0x14)
+
+
+/**
+ * @spinlock: used for atomic read/modify/write of registers
+ * @base: register base address
+ * @domain: IRQ domain of GPIO generated interrupts managed by this controller
+ * @irq: Interrupt line of parent interrupt controller
+ * @gc: gpio_chip structure associated to this GPIO controller
+ */
+struct tb10x_gpio {
+ spinlock_t spinlock;
+ void __iomem *base;
+ struct irq_domain *domain;
+ int irq;
+ struct gpio_chip gc;
+};
+
+static inline u32 tb10x_reg_read(struct tb10x_gpio *gpio, unsigned int offs)
+{
+ return ioread32(gpio->base + offs);
+}
+
+static inline void tb10x_reg_write(struct tb10x_gpio *gpio, unsigned int offs,
+ u32 val)
+{
+ iowrite32(val, gpio->base + offs);
+}
+
+static inline void tb10x_set_bits(struct tb10x_gpio *gpio, unsigned int offs,
+ u32 mask, u32 val)
+{
+ u32 r;
+ unsigned long flags;
+
+ spin_lock_irqsave(&gpio->spinlock, flags);
+
+ r = tb10x_reg_read(gpio, offs);
+ r = (r & ~mask) | (val & mask);
+
+ tb10x_reg_write(gpio, offs, r);
+
+ spin_unlock_irqrestore(&gpio->spinlock, flags);
+}
+
+static inline struct tb10x_gpio *to_tb10x_gpio(struct gpio_chip *chip)
+{
+ return container_of(chip, struct tb10x_gpio, gc);
+}
+
+static int tb10x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
+{
+ struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
+ int mask = BIT(offset);
+ int val = TB10X_GPIO_DIR_IN << offset;
+
+ tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val);
+
+ return 0;
+}
+
+static int tb10x_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
+ int val;
+
+ val = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_DATA);
+
+ if (val & BIT(offset))
+ return 1;
+ else
+ return 0;
+}
+
+static void tb10x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+ struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
+ int mask = BIT(offset);
+ int val = value << offset;
+
+ tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DATA, mask, val);
+}
+
+static int tb10x_gpio_direction_out(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
+ int mask = BIT(offset);
+ int val = TB10X_GPIO_DIR_OUT << offset;
+
+ tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val);
+
+ return 0;
+}
+
+static int tb10x_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+ return pinctrl_request_gpio(chip->base + offset);
+}
+
+static void tb10x_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+ pinctrl_free_gpio(chip->base + offset);
+}
+
+static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
+
+ return irq_create_mapping(tb10x_gpio->domain, offset);
+}
+
+static int tb10x_gpio_irq_set_type(struct irq_data *data, unsigned int type)
+{
+ if ((type & IRQF_TRIGGER_MASK) != IRQ_TYPE_EDGE_BOTH) {
+ pr_err("Only (both) edge triggered interrupts supported.\n");
+ return -EINVAL;
+ }
+
+ irqd_set_trigger_type(data, type);
+
+ return IRQ_SET_MASK_OK;
+}
+
+static irqreturn_t tb10x_gpio_irq_cascade(int irq, void *data)
+{
+ struct tb10x_gpio *tb10x_gpio = data;
+ u32 r = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_CHANGE);
+ u32 m = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_INT_EN);
+ const unsigned long bits = r & m;
+ int i;
+
+ for_each_set_bit(i, &bits, 32)
+ generic_handle_irq(irq_find_mapping(tb10x_gpio->domain, i));
+
+ return IRQ_HANDLED;
+}
+
+static int tb10x_gpio_probe(struct platform_device *pdev)
+{
+ struct tb10x_gpio *tb10x_gpio;
+ struct resource *mem;
+ struct device_node *dn = pdev->dev.of_node;
+ int ret = -EBUSY;
+ u32 ngpio;
+
+ if (!dn)
+ return -EINVAL;
+
+ if (of_property_read_u32(dn, "abilis,ngpio", &ngpio))
+ return -EINVAL;
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!mem) {
+ dev_err(&pdev->dev, "No memory resource defined.\n");
+ return -EINVAL;
+ }
+
+ tb10x_gpio = devm_kzalloc(&pdev->dev, sizeof(*tb10x_gpio), GFP_KERNEL);
+ if (tb10x_gpio == NULL)
+ return -ENOMEM;
+
+ spin_lock_init(&tb10x_gpio->spinlock);
+
+ tb10x_gpio->base = devm_ioremap_resource(&pdev->dev, mem);
+ if (IS_ERR(tb10x_gpio->base))
+ return PTR_ERR(tb10x_gpio->base);
+
+ tb10x_gpio->gc.label = of_node_full_name(dn);
+ tb10x_gpio->gc.dev = &pdev->dev;
+ tb10x_gpio->gc.owner = THIS_MODULE;
+ tb10x_gpio->gc.direction_input = tb10x_gpio_direction_in;
+ tb10x_gpio->gc.get = tb10x_gpio_get;
+ tb10x_gpio->gc.direction_output = tb10x_gpio_direction_out;
+ tb10x_gpio->gc.set = tb10x_gpio_set;
+ tb10x_gpio->gc.request = tb10x_gpio_request;
+ tb10x_gpio->gc.free = tb10x_gpio_free;
+ tb10x_gpio->gc.base = -1;
+ tb10x_gpio->gc.ngpio = ngpio;
+ tb10x_gpio->gc.can_sleep = 0;
+
+
+ ret = gpiochip_add(&tb10x_gpio->gc);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Could not add gpiochip.\n");
+ goto fail_gpiochip_registration;
+ }
+
+ platform_set_drvdata(pdev, tb10x_gpio);
+
+ if (of_find_property(dn, "interrupt-controller", NULL)) {
+ struct irq_chip_generic *gc;
+
+ ret = platform_get_irq(pdev, 0);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "No interrupt specified.\n");
+ goto fail_get_irq;
+ }
+
+ tb10x_gpio->gc.to_irq = tb10x_gpio_to_irq;
+ tb10x_gpio->irq = ret;
+
+ ret = devm_request_irq(&pdev->dev, ret, tb10x_gpio_irq_cascade,
+ IRQF_TRIGGER_NONE | IRQF_SHARED,
+ dev_name(&pdev->dev), tb10x_gpio);
+ if (ret != 0)
+ goto fail_request_irq;
+
+ tb10x_gpio->domain = irq_domain_add_linear(dn,
+ tb10x_gpio->gc.ngpio,
+ &irq_generic_chip_ops, NULL);
+ if (!tb10x_gpio->domain) {
+ ret = -ENOMEM;
+ goto fail_irq_domain;
+ }
+
+ ret = irq_alloc_domain_generic_chips(tb10x_gpio->domain,
+ tb10x_gpio->gc.ngpio, 1, tb10x_gpio->gc.label,
+ handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE,
+ IRQ_GC_INIT_MASK_CACHE);
+ if (ret)
+ goto fail_irq_domain;
+
+ gc = tb10x_gpio->domain->gc->gc[0];
+ gc->reg_base = tb10x_gpio->base;
+ gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH;
+ gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
+ gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
+ gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
+ gc->chip_types[0].chip.irq_set_type = tb10x_gpio_irq_set_type;
+ gc->chip_types[0].regs.ack = OFFSET_TO_REG_CHANGE;
+ gc->chip_types[0].regs.mask = OFFSET_TO_REG_INT_EN;
+ }
+
+ return 0;
+
+fail_irq_domain:
+fail_request_irq:
+fail_get_irq:
+ gpiochip_remove(&tb10x_gpio->gc);
+fail_gpiochip_registration:
+fail_ioremap:
+ return ret;
+}
+
+static int __exit tb10x_gpio_remove(struct platform_device *pdev)
+{
+ struct tb10x_gpio *tb10x_gpio = platform_get_drvdata(pdev);
+ int ret;
+
+ if (tb10x_gpio->gc.to_irq) {
+ irq_remove_generic_chip(tb10x_gpio->domain->gc->gc[0],
+ BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0);
+ kfree(tb10x_gpio->domain->gc);
+ irq_domain_remove(tb10x_gpio->domain);
+ free_irq(tb10x_gpio->irq, tb10x_gpio);
+ }
+ ret = gpiochip_remove(&tb10x_gpio->gc);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct of_device_id tb10x_gpio_dt_ids[] = {
+ { .compatible = "abilis,tb10x-gpio" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, tb10x_gpio_dt_ids);
+
+static struct platform_driver tb10x_gpio_driver = {
+ .probe = tb10x_gpio_probe,
+ .remove = tb10x_gpio_remove,
+ .driver = {
+ .name = "tb10x-gpio",
+ .of_match_table = of_match_ptr(tb10x_gpio_dt_ids),
+ .owner = THIS_MODULE,
+ }
+};
+
+module_platform_driver(tb10x_gpio_driver);
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("tb10x gpio.");
+MODULE_VERSION("0.0.1");
struct of_phandle_args pinspec;
struct pinctrl_dev *pctldev;
int index = 0, ret;
+ const char *name;
+ static const char group_names_propname[] = "gpio-ranges-group-names";
+ struct property *group_names;
if (!np)
return;
+ group_names = of_find_property(np, group_names_propname, NULL);
+
for (;; index++) {
ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3,
index, &pinspec);
if (!pctldev)
break;
- ret = gpiochip_add_pin_range(chip,
- pinctrl_dev_get_devname(pctldev),
- pinspec.args[0],
- pinspec.args[1],
- pinspec.args[2]);
-
- if (ret)
- break;
+ if (pinspec.args[2]) {
+ if (group_names) {
+ ret = of_property_read_string_index(np,
+ group_names_propname,
+ index, &name);
+ if (strlen(name)) {
+ pr_err("%s: Group name of numeric GPIO ranges must be the empty string.\n",
+ np->full_name);
+ break;
+ }
+ }
+ /* npins != 0: linear range */
+ ret = gpiochip_add_pin_range(chip,
+ pinctrl_dev_get_devname(pctldev),
+ pinspec.args[0],
+ pinspec.args[1],
+ pinspec.args[2]);
+ if (ret)
+ break;
+ } else {
+ /* npins == 0: special range */
+ if (pinspec.args[1]) {
+ pr_err("%s: Illegal gpio-range format.\n",
+ np->full_name);
+ break;
+ }
+
+ if (!group_names) {
+ pr_err("%s: GPIO group range requested but no %s property.\n",
+ np->full_name, group_names_propname);
+ break;
+ }
+
+ ret = of_property_read_string_index(np,
+ group_names_propname,
+ index, &name);
+ if (ret)
+ break;
+
+ if (!strlen(name)) {
+ pr_err("%s: Group name of GPIO group range cannot be the empty string.\n",
+ np->full_name);
+ break;
+ }
+
+ ret = gpiochip_add_pingroup_range(chip, pctldev,
+ pinspec.args[0], name);
+ if (ret)
+ break;
+ }
}
}
#ifdef CONFIG_PINCTRL
+/**
+ * gpiochip_add_pingroup_range() - add a range for GPIO <-> pin mapping
+ * @chip: the gpiochip to add the range for
+ * @pinctrl: the dev_name() of the pin controller to map to
+ * @gpio_offset: the start offset in the current gpio_chip number space
+ * @pin_group: name of the pin group inside the pin controller
+ */
+int gpiochip_add_pingroup_range(struct gpio_chip *chip,
+ struct pinctrl_dev *pctldev,
+ unsigned int gpio_offset, const char *pin_group)
+{
+ struct gpio_pin_range *pin_range;
+ int ret;
+
+ pin_range = kzalloc(sizeof(*pin_range), GFP_KERNEL);
+ if (!pin_range) {
+ pr_err("%s: GPIO chip: failed to allocate pin ranges\n",
+ chip->label);
+ return -ENOMEM;
+ }
+
+ /* Use local offset as range ID */
+ pin_range->range.id = gpio_offset;
+ pin_range->range.gc = chip;
+ pin_range->range.name = chip->label;
+ pin_range->range.base = chip->base + gpio_offset;
+ pin_range->pctldev = pctldev;
+
+ ret = pinctrl_get_group_pins(pctldev, pin_group,
+ &pin_range->range.pins,
+ &pin_range->range.npins);
+ if (ret < 0)
+ return ret;
+
+ pinctrl_add_gpio_range(pctldev, &pin_range->range);
+
+ pr_debug("GPIO chip %s: created GPIO range %d->%d ==> %s PINGRP %s\n",
+ chip->label, gpio_offset,
+ gpio_offset + pin_range->range.npins - 1,
+ pinctrl_dev_get_devname(pctldev), pin_group);
+
+ list_add_tail(&pin_range->node, &chip->pin_ranges);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(gpiochip_add_pingroup_range);
+
/**
* gpiochip_add_pin_range() - add a range for GPIO <-> pin mapping
* @chip: the gpiochip to add the range for
bool "AB8505 pin controller driver"
depends on PINCTRL_ABX500 && ARCH_U8500
+config PINCTRL_ADI2
+ bool "ADI pin controller driver"
+ depends on BLACKFIN
+ select PINMUX
+ select IRQ_DOMAIN
+ help
+ This is the pin controller and gpio driver for ADI BF54x, BF60x and
+ future processors. This option is selected automatically when specific
+ machine and arch are selected to build.
+
+config PINCTRL_AS3722
+ bool "Pinctrl and GPIO driver for ams AS3722 PMIC"
+ depends on MFD_AS3722 && GPIOLIB
+ select PINMUX
+ select GENERIC_PINCONF
+ help
+ AS3722 device supports the configuration of GPIO pins for different
+ functionality. This driver supports the pinmux, push-pull and
+ open drain configuration for the GPIO pins of AS3722 devices. It also
+ supports the GPIO functionality through gpiolib.
+
+config PINCTRL_BF54x
+ def_bool y if BF54x
+ select PINCTRL_ADI2
+
+config PINCTRL_BF60x
+ def_bool y if BF60x
+ select PINCTRL_ADI2
+
config PINCTRL_AT91
bool "AT91 pinctrl driver"
depends on OF
select PINMUX
select PINCONF
+config PINCTRL_IMX1_CORE
+ bool
+ select PINMUX
+ select PINCONF
+
+config PINCTRL_IMX27
+ bool "IMX27 pinctrl driver"
+ depends on OF
+ depends on SOC_IMX27
+ select PINCTRL_IMX1_CORE
+ help
+ Say Y here to enable the imx27 pinctrl driver
+
config PINCTRL_IMX35
bool "IMX35 pinctrl driver"
depends on OF
help
Say Y here to enable the imx35 pinctrl driver
+config PINCTRL_IMX50
+ bool "IMX50 pinctrl driver"
+ depends on OF
+ depends on SOC_IMX50
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx50 pinctrl driver
+
config PINCTRL_IMX51
bool "IMX51 pinctrl driver"
depends on OF
depends on SOC_TYPE_XWAY
depends on PINCTRL_LANTIQ
+config PINCTRL_TB10X
+ bool
+ depends on ARC_PLAT_TB10X
+
endmenu
endif
obj-$(CONFIG_PINCTRL_AB8540) += pinctrl-ab8540.o
obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o
obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o
+obj-$(CONFIG_PINCTRL_ADI2) += pinctrl-adi2.o
+obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o
+obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o
+obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o
obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
+obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
+obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
+obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o
obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
+obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
}
EXPORT_SYMBOL_GPL(pinctrl_find_and_add_gpio_range);
+int pinctrl_get_group_pins(struct pinctrl_dev *pctldev, const char *pin_group,
+ const unsigned **pins, unsigned *num_pins)
+{
+ const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
+ int gs;
+
+ gs = pinctrl_get_group_selector(pctldev, pin_group);
+ if (gs < 0)
+ return gs;
+
+ return pctlops->get_group_pins(pctldev, gs, pins, num_pins);
+}
+EXPORT_SYMBOL_GPL(pinctrl_get_group_pins);
+
/**
* pinctrl_find_gpio_range_from_pin() - locate the GPIO range for a pin
* @pctldev: the pin controller device to look in
.driver = {
.name = "armada-370-pinctrl",
.owner = THIS_MODULE,
- .of_match_table = of_match_ptr(armada_370_pinctrl_of_match),
+ .of_match_table = armada_370_pinctrl_of_match,
},
.probe = armada_370_pinctrl_probe,
.remove = armada_370_pinctrl_remove,
.driver = {
.name = "armada-xp-pinctrl",
.owner = THIS_MODULE,
- .of_match_table = of_match_ptr(armada_xp_pinctrl_of_match),
+ .of_match_table = armada_xp_pinctrl_of_match,
},
.probe = armada_xp_pinctrl_probe,
.remove = armada_xp_pinctrl_remove,
unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1;
- gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION2);
+ gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION3);
switch (config) {
case 1:
.driver = {
.name = "dove-pinctrl",
.owner = THIS_MODULE,
- .of_match_table = of_match_ptr(dove_pinctrl_of_match),
+ .of_match_table = dove_pinctrl_of_match,
},
.probe = dove_pinctrl_probe,
.remove = dove_pinctrl_remove,
.driver = {
.name = "kirkwood-pinctrl",
.owner = THIS_MODULE,
- .of_match_table = of_match_ptr(kirkwood_pinctrl_of_match),
+ .of_match_table = kirkwood_pinctrl_of_match,
},
.probe = kirkwood_pinctrl_probe,
.remove = kirkwood_pinctrl_remove,
--- /dev/null
+/*
+ * Pinctrl Driver for ADI GPIO2 controller
+ *
+ * Copyright 2007-2013 Analog Devices Inc.
+ *
+ * Licensed under the GPLv2 or later
+ */
+
+#include <asm/portmux.h>
+#include "pinctrl-adi2.h"
+
+static const struct pinctrl_pin_desc adi_pads[] = {
+ PINCTRL_PIN(0, "PA0"),
+ PINCTRL_PIN(1, "PA1"),
+ PINCTRL_PIN(2, "PA2"),
+ PINCTRL_PIN(3, "PG3"),
+ PINCTRL_PIN(4, "PA4"),
+ PINCTRL_PIN(5, "PA5"),
+ PINCTRL_PIN(6, "PA6"),
+ PINCTRL_PIN(7, "PA7"),
+ PINCTRL_PIN(8, "PA8"),
+ PINCTRL_PIN(9, "PA9"),
+ PINCTRL_PIN(10, "PA10"),
+ PINCTRL_PIN(11, "PA11"),
+ PINCTRL_PIN(12, "PA12"),
+ PINCTRL_PIN(13, "PA13"),
+ PINCTRL_PIN(14, "PA14"),
+ PINCTRL_PIN(15, "PA15"),
+ PINCTRL_PIN(16, "PB0"),
+ PINCTRL_PIN(17, "PB1"),
+ PINCTRL_PIN(18, "PB2"),
+ PINCTRL_PIN(19, "PB3"),
+ PINCTRL_PIN(20, "PB4"),
+ PINCTRL_PIN(21, "PB5"),
+ PINCTRL_PIN(22, "PB6"),
+ PINCTRL_PIN(23, "PB7"),
+ PINCTRL_PIN(24, "PB8"),
+ PINCTRL_PIN(25, "PB9"),
+ PINCTRL_PIN(26, "PB10"),
+ PINCTRL_PIN(27, "PB11"),
+ PINCTRL_PIN(28, "PB12"),
+ PINCTRL_PIN(29, "PB13"),
+ PINCTRL_PIN(30, "PB14"),
+ PINCTRL_PIN(32, "PC0"),
+ PINCTRL_PIN(33, "PC1"),
+ PINCTRL_PIN(34, "PC2"),
+ PINCTRL_PIN(35, "PC3"),
+ PINCTRL_PIN(36, "PC4"),
+ PINCTRL_PIN(37, "PC5"),
+ PINCTRL_PIN(38, "PC6"),
+ PINCTRL_PIN(39, "PC7"),
+ PINCTRL_PIN(40, "PC8"),
+ PINCTRL_PIN(41, "PC9"),
+ PINCTRL_PIN(42, "PC10"),
+ PINCTRL_PIN(43, "PC11"),
+ PINCTRL_PIN(44, "PC12"),
+ PINCTRL_PIN(45, "PC13"),
+ PINCTRL_PIN(48, "PD0"),
+ PINCTRL_PIN(49, "PD1"),
+ PINCTRL_PIN(50, "PD2"),
+ PINCTRL_PIN(51, "PD3"),
+ PINCTRL_PIN(52, "PD4"),
+ PINCTRL_PIN(53, "PD5"),
+ PINCTRL_PIN(54, "PD6"),
+ PINCTRL_PIN(55, "PD7"),
+ PINCTRL_PIN(56, "PD8"),
+ PINCTRL_PIN(57, "PD9"),
+ PINCTRL_PIN(58, "PD10"),
+ PINCTRL_PIN(59, "PD11"),
+ PINCTRL_PIN(60, "PD12"),
+ PINCTRL_PIN(61, "PD13"),
+ PINCTRL_PIN(62, "PD14"),
+ PINCTRL_PIN(63, "PD15"),
+ PINCTRL_PIN(64, "PE0"),
+ PINCTRL_PIN(65, "PE1"),
+ PINCTRL_PIN(66, "PE2"),
+ PINCTRL_PIN(67, "PE3"),
+ PINCTRL_PIN(68, "PE4"),
+ PINCTRL_PIN(69, "PE5"),
+ PINCTRL_PIN(70, "PE6"),
+ PINCTRL_PIN(71, "PE7"),
+ PINCTRL_PIN(72, "PE8"),
+ PINCTRL_PIN(73, "PE9"),
+ PINCTRL_PIN(74, "PE10"),
+ PINCTRL_PIN(75, "PE11"),
+ PINCTRL_PIN(76, "PE12"),
+ PINCTRL_PIN(77, "PE13"),
+ PINCTRL_PIN(78, "PE14"),
+ PINCTRL_PIN(79, "PE15"),
+ PINCTRL_PIN(80, "PF0"),
+ PINCTRL_PIN(81, "PF1"),
+ PINCTRL_PIN(82, "PF2"),
+ PINCTRL_PIN(83, "PF3"),
+ PINCTRL_PIN(84, "PF4"),
+ PINCTRL_PIN(85, "PF5"),
+ PINCTRL_PIN(86, "PF6"),
+ PINCTRL_PIN(87, "PF7"),
+ PINCTRL_PIN(88, "PF8"),
+ PINCTRL_PIN(89, "PF9"),
+ PINCTRL_PIN(90, "PF10"),
+ PINCTRL_PIN(91, "PF11"),
+ PINCTRL_PIN(92, "PF12"),
+ PINCTRL_PIN(93, "PF13"),
+ PINCTRL_PIN(94, "PF14"),
+ PINCTRL_PIN(95, "PF15"),
+ PINCTRL_PIN(96, "PG0"),
+ PINCTRL_PIN(97, "PG1"),
+ PINCTRL_PIN(98, "PG2"),
+ PINCTRL_PIN(99, "PG3"),
+ PINCTRL_PIN(100, "PG4"),
+ PINCTRL_PIN(101, "PG5"),
+ PINCTRL_PIN(102, "PG6"),
+ PINCTRL_PIN(103, "PG7"),
+ PINCTRL_PIN(104, "PG8"),
+ PINCTRL_PIN(105, "PG9"),
+ PINCTRL_PIN(106, "PG10"),
+ PINCTRL_PIN(107, "PG11"),
+ PINCTRL_PIN(108, "PG12"),
+ PINCTRL_PIN(109, "PG13"),
+ PINCTRL_PIN(110, "PG14"),
+ PINCTRL_PIN(111, "PG15"),
+ PINCTRL_PIN(112, "PH0"),
+ PINCTRL_PIN(113, "PH1"),
+ PINCTRL_PIN(114, "PH2"),
+ PINCTRL_PIN(115, "PH3"),
+ PINCTRL_PIN(116, "PH4"),
+ PINCTRL_PIN(117, "PH5"),
+ PINCTRL_PIN(118, "PH6"),
+ PINCTRL_PIN(119, "PH7"),
+ PINCTRL_PIN(120, "PH8"),
+ PINCTRL_PIN(121, "PH9"),
+ PINCTRL_PIN(122, "PH10"),
+ PINCTRL_PIN(123, "PH11"),
+ PINCTRL_PIN(124, "PH12"),
+ PINCTRL_PIN(125, "PH13"),
+ PINCTRL_PIN(128, "PI0"),
+ PINCTRL_PIN(129, "PI1"),
+ PINCTRL_PIN(130, "PI2"),
+ PINCTRL_PIN(131, "PI3"),
+ PINCTRL_PIN(132, "PI4"),
+ PINCTRL_PIN(133, "PI5"),
+ PINCTRL_PIN(134, "PI6"),
+ PINCTRL_PIN(135, "PI7"),
+ PINCTRL_PIN(136, "PI8"),
+ PINCTRL_PIN(137, "PI9"),
+ PINCTRL_PIN(138, "PI10"),
+ PINCTRL_PIN(139, "PI11"),
+ PINCTRL_PIN(140, "PI12"),
+ PINCTRL_PIN(141, "PI13"),
+ PINCTRL_PIN(142, "PI14"),
+ PINCTRL_PIN(143, "PI15"),
+ PINCTRL_PIN(144, "PJ0"),
+ PINCTRL_PIN(145, "PJ1"),
+ PINCTRL_PIN(146, "PJ2"),
+ PINCTRL_PIN(147, "PJ3"),
+ PINCTRL_PIN(148, "PJ4"),
+ PINCTRL_PIN(149, "PJ5"),
+ PINCTRL_PIN(150, "PJ6"),
+ PINCTRL_PIN(151, "PJ7"),
+ PINCTRL_PIN(152, "PJ8"),
+ PINCTRL_PIN(153, "PJ9"),
+ PINCTRL_PIN(154, "PJ10"),
+ PINCTRL_PIN(155, "PJ11"),
+ PINCTRL_PIN(156, "PJ12"),
+ PINCTRL_PIN(157, "PJ13"),
+};
+
+static const unsigned uart0_pins[] = {
+ GPIO_PE7, GPIO_PE8,
+};
+
+static const unsigned uart1_pins[] = {
+ GPIO_PH0, GPIO_PH1,
+};
+
+static const unsigned uart1_ctsrts_pins[] = {
+ GPIO_PE9, GPIO_PE10,
+};
+
+static const unsigned uart2_pins[] = {
+ GPIO_PB4, GPIO_PB5,
+};
+
+static const unsigned uart3_pins[] = {
+ GPIO_PB6, GPIO_PB7,
+};
+
+static const unsigned uart3_ctsrts_pins[] = {
+ GPIO_PB2, GPIO_PB3,
+};
+
+static const unsigned rsi0_pins[] = {
+ GPIO_PC8, GPIO_PC9, GPIO_PC10, GPIO_PC11, GPIO_PC12, GPIO_PC13,
+};
+
+static const unsigned spi0_pins[] = {
+ GPIO_PE0, GPIO_PE1, GPIO_PE2,
+};
+
+static const unsigned spi1_pins[] = {
+ GPIO_PG8, GPIO_PG9, GPIO_PG10,
+};
+
+static const unsigned twi0_pins[] = {
+ GPIO_PE14, GPIO_PE15,
+};
+
+static const unsigned twi1_pins[] = {
+ GPIO_PB0, GPIO_PB1,
+};
+
+static const unsigned rotary_pins[] = {
+ GPIO_PH4, GPIO_PH3, GPIO_PH5,
+};
+
+static const unsigned can0_pins[] = {
+ GPIO_PG13, GPIO_PG12,
+};
+
+static const unsigned can1_pins[] = {
+ GPIO_PG14, GPIO_PG15,
+};
+
+static const unsigned smc0_pins[] = {
+ GPIO_PH8, GPIO_PH9, GPIO_PH10, GPIO_PH11, GPIO_PH12, GPIO_PH13,
+ GPIO_PI0, GPIO_PI1, GPIO_PI2, GPIO_PI3, GPIO_PI4, GPIO_PI5, GPIO_PI6,
+ GPIO_PI7, GPIO_PI8, GPIO_PI9, GPIO_PI10, GPIO_PI11,
+ GPIO_PI12, GPIO_PI13, GPIO_PI14, GPIO_PI15,
+};
+
+static const unsigned sport0_pins[] = {
+ GPIO_PC0, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC6, GPIO_PC7,
+};
+
+static const unsigned sport1_pins[] = {
+ GPIO_PD0, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD6, GPIO_PD7,
+};
+
+static const unsigned sport2_pins[] = {
+ GPIO_PA0, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA6, GPIO_PA7,
+};
+
+static const unsigned sport3_pins[] = {
+ GPIO_PA8, GPIO_PA10, GPIO_PA11, GPIO_PA12, GPIO_PA14, GPIO_PA15,
+};
+
+static const unsigned ppi0_8b_pins[] = {
+ GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
+ GPIO_PF7, GPIO_PF13, GPIO_PG0, GPIO_PG1, GPIO_PG2,
+};
+
+static const unsigned ppi0_16b_pins[] = {
+ GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
+ GPIO_PF7, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
+ GPIO_PF13, GPIO_PF14, GPIO_PF15,
+ GPIO_PG0, GPIO_PG1, GPIO_PG2,
+};
+
+static const unsigned ppi0_24b_pins[] = {
+ GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
+ GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
+ GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PD0, GPIO_PD1, GPIO_PD2,
+ GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PG3, GPIO_PG4,
+ GPIO_PG0, GPIO_PG1, GPIO_PG2,
+};
+
+static const unsigned ppi1_8b_pins[] = {
+ GPIO_PD0, GPIO_PD1, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PD6,
+ GPIO_PD7, GPIO_PE11, GPIO_PE12, GPIO_PE13,
+};
+
+static const unsigned ppi1_16b_pins[] = {
+ GPIO_PD0, GPIO_PD1, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PD6,
+ GPIO_PD7, GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, GPIO_PD12,
+ GPIO_PD13, GPIO_PD14, GPIO_PD15,
+ GPIO_PE11, GPIO_PE12, GPIO_PE13,
+};
+
+static const unsigned ppi2_8b_pins[] = {
+ GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, GPIO_PD12,
+ GPIO_PD13, GPIO_PD14, GPIO_PD15,
+ GPIO_PA7, GPIO_PB0, GPIO_PB1, GPIO_PB2, GPIO_PB3,
+};
+
+static const unsigned atapi_pins[] = {
+ GPIO_PH2, GPIO_PJ3, GPIO_PJ4, GPIO_PJ5, GPIO_PJ6,
+ GPIO_PJ7, GPIO_PJ8, GPIO_PJ9, GPIO_PJ10,
+};
+
+static const unsigned atapi_alter_pins[] = {
+ GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
+ GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
+ GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PG2, GPIO_PG3, GPIO_PG4,
+};
+
+static const unsigned nfc0_pins[] = {
+ GPIO_PJ1, GPIO_PJ2,
+};
+
+static const unsigned keys_4x4_pins[] = {
+ GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11,
+ GPIO_PD12, GPIO_PD13, GPIO_PD14, GPIO_PD15,
+};
+
+static const unsigned keys_8x8_pins[] = {
+ GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11,
+ GPIO_PD12, GPIO_PD13, GPIO_PD14, GPIO_PD15,
+ GPIO_PE0, GPIO_PE1, GPIO_PE2, GPIO_PE3,
+ GPIO_PE4, GPIO_PE5, GPIO_PE6, GPIO_PE7,
+};
+
+static const struct adi_pin_group adi_pin_groups[] = {
+ ADI_PIN_GROUP("uart0grp", uart0_pins),
+ ADI_PIN_GROUP("uart1grp", uart1_pins),
+ ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins),
+ ADI_PIN_GROUP("uart2grp", uart2_pins),
+ ADI_PIN_GROUP("uart3grp", uart3_pins),
+ ADI_PIN_GROUP("uart3ctsrtsgrp", uart3_ctsrts_pins),
+ ADI_PIN_GROUP("rsi0grp", rsi0_pins),
+ ADI_PIN_GROUP("spi0grp", spi0_pins),
+ ADI_PIN_GROUP("spi1grp", spi1_pins),
+ ADI_PIN_GROUP("twi0grp", twi0_pins),
+ ADI_PIN_GROUP("twi1grp", twi1_pins),
+ ADI_PIN_GROUP("rotarygrp", rotary_pins),
+ ADI_PIN_GROUP("can0grp", can0_pins),
+ ADI_PIN_GROUP("can1grp", can1_pins),
+ ADI_PIN_GROUP("smc0grp", smc0_pins),
+ ADI_PIN_GROUP("sport0grp", sport0_pins),
+ ADI_PIN_GROUP("sport1grp", sport1_pins),
+ ADI_PIN_GROUP("sport2grp", sport2_pins),
+ ADI_PIN_GROUP("sport3grp", sport3_pins),
+ ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins),
+ ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins),
+ ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins),
+ ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins),
+ ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins),
+ ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins),
+ ADI_PIN_GROUP("atapigrp", atapi_pins),
+ ADI_PIN_GROUP("atapialtergrp", atapi_alter_pins),
+ ADI_PIN_GROUP("nfc0grp", nfc0_pins),
+ ADI_PIN_GROUP("keys_4x4grp", keys_4x4_pins),
+ ADI_PIN_GROUP("keys_8x8grp", keys_8x8_pins),
+};
+
+static const unsigned short uart0_mux[] = {
+ P_UART0_TX, P_UART0_RX,
+ 0
+};
+
+static const unsigned short uart1_mux[] = {
+ P_UART1_TX, P_UART1_RX,
+ 0
+};
+
+static const unsigned short uart1_ctsrts_mux[] = {
+ P_UART1_RTS, P_UART1_CTS,
+ 0
+};
+
+static const unsigned short uart2_mux[] = {
+ P_UART2_TX, P_UART2_RX,
+ 0
+};
+
+static const unsigned short uart3_mux[] = {
+ P_UART3_TX, P_UART3_RX,
+ 0
+};
+
+static const unsigned short uart3_ctsrts_mux[] = {
+ P_UART3_RTS, P_UART3_CTS,
+ 0
+};
+
+static const unsigned short rsi0_mux[] = {
+ P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD,
+ 0
+};
+
+static const unsigned short spi0_mux[] = {
+ P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0
+};
+
+static const unsigned short spi1_mux[] = {
+ P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0
+};
+
+static const unsigned short twi0_mux[] = {
+ P_TWI0_SCL, P_TWI0_SDA, 0
+};
+
+static const unsigned short twi1_mux[] = {
+ P_TWI1_SCL, P_TWI1_SDA, 0
+};
+
+static const unsigned short rotary_mux[] = {
+ P_CNT_CUD, P_CNT_CDG, P_CNT_CZM, 0
+};
+
+static const unsigned short sport0_mux[] = {
+ P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
+ P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
+};
+
+static const unsigned short sport1_mux[] = {
+ P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
+ P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
+};
+
+static const unsigned short sport2_mux[] = {
+ P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
+ P_SPORT2_DRPRI, P_SPORT2_RSCLK, 0
+};
+
+static const unsigned short sport3_mux[] = {
+ P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
+ P_SPORT3_DRPRI, P_SPORT3_RSCLK, 0
+};
+
+static const unsigned short can0_mux[] = {
+ P_CAN0_RX, P_CAN0_TX, 0
+};
+
+static const unsigned short can1_mux[] = {
+ P_CAN1_RX, P_CAN1_TX, 0
+};
+
+static const unsigned short smc0_mux[] = {
+ P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
+ P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
+ P_A22, P_A23, P_A24, P_A25, P_NOR_CLK, 0,
+};
+
+static const unsigned short ppi0_8b_mux[] = {
+ P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
+ P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
+ P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
+ 0,
+};
+
+static const unsigned short ppi0_16b_mux[] = {
+ P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
+ P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
+ P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
+ P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
+ P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
+ 0,
+};
+
+static const unsigned short ppi0_24b_mux[] = {
+ P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
+ P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
+ P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
+ P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
+ P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
+ P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
+ P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
+ 0,
+};
+
+static const unsigned short ppi1_8b_mux[] = {
+ P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
+ P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
+ P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
+ 0,
+};
+
+static const unsigned short ppi1_16b_mux[] = {
+ P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
+ P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
+ P_PPI1_D8, P_PPI1_D9, P_PPI1_D10, P_PPI1_D11,
+ P_PPI1_D12, P_PPI1_D13, P_PPI1_D14, P_PPI1_D15,
+ P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
+ 0,
+};
+
+static const unsigned short ppi2_8b_mux[] = {
+ P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3,
+ P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7,
+ P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2,
+ 0,
+};
+
+static const unsigned short atapi_mux[] = {
+ P_ATAPI_RESET, P_ATAPI_DIOR, P_ATAPI_DIOW, P_ATAPI_CS0, P_ATAPI_CS1,
+ P_ATAPI_DMACK, P_ATAPI_DMARQ, P_ATAPI_INTRQ, P_ATAPI_IORDY,
+};
+
+static const unsigned short atapi_alter_mux[] = {
+ P_ATAPI_D0A, P_ATAPI_D1A, P_ATAPI_D2A, P_ATAPI_D3A, P_ATAPI_D4A,
+ P_ATAPI_D5A, P_ATAPI_D6A, P_ATAPI_D7A, P_ATAPI_D8A, P_ATAPI_D9A,
+ P_ATAPI_D10A, P_ATAPI_D11A, P_ATAPI_D12A, P_ATAPI_D13A, P_ATAPI_D14A,
+ P_ATAPI_D15A, P_ATAPI_A0A, P_ATAPI_A1A, P_ATAPI_A2A,
+ 0
+};
+
+static const unsigned short nfc0_mux[] = {
+ P_NAND_CE, P_NAND_RB,
+ 0
+};
+
+static const unsigned short keys_4x4_mux[] = {
+ P_KEY_ROW3, P_KEY_ROW2, P_KEY_ROW1, P_KEY_ROW0,
+ P_KEY_COL3, P_KEY_COL2, P_KEY_COL1, P_KEY_COL0,
+ 0
+};
+
+static const unsigned short keys_8x8_mux[] = {
+ P_KEY_ROW7, P_KEY_ROW6, P_KEY_ROW5, P_KEY_ROW4,
+ P_KEY_ROW3, P_KEY_ROW2, P_KEY_ROW1, P_KEY_ROW0,
+ P_KEY_COL7, P_KEY_COL6, P_KEY_COL5, P_KEY_COL4,
+ P_KEY_COL3, P_KEY_COL2, P_KEY_COL1, P_KEY_COL0,
+ 0
+};
+
+static const char * const uart0grp[] = { "uart0grp" };
+static const char * const uart1grp[] = { "uart1grp" };
+static const char * const uart1ctsrtsgrp[] = { "uart1ctsrtsgrp" };
+static const char * const uart2grp[] = { "uart2grp" };
+static const char * const uart3grp[] = { "uart3grp" };
+static const char * const uart3ctsrtsgrp[] = { "uart3ctsrtsgrp" };
+static const char * const rsi0grp[] = { "rsi0grp" };
+static const char * const spi0grp[] = { "spi0grp" };
+static const char * const spi1grp[] = { "spi1grp" };
+static const char * const twi0grp[] = { "twi0grp" };
+static const char * const twi1grp[] = { "twi1grp" };
+static const char * const rotarygrp[] = { "rotarygrp" };
+static const char * const can0grp[] = { "can0grp" };
+static const char * const can1grp[] = { "can1grp" };
+static const char * const smc0grp[] = { "smc0grp" };
+static const char * const sport0grp[] = { "sport0grp" };
+static const char * const sport1grp[] = { "sport1grp" };
+static const char * const sport2grp[] = { "sport2grp" };
+static const char * const sport3grp[] = { "sport3grp" };
+static const char * const ppi0_8bgrp[] = { "ppi0_8bgrp" };
+static const char * const ppi0_16bgrp[] = { "ppi0_16bgrp" };
+static const char * const ppi0_24bgrp[] = { "ppi0_24bgrp" };
+static const char * const ppi1_8bgrp[] = { "ppi1_8bgrp" };
+static const char * const ppi1_16bgrp[] = { "ppi1_16bgrp" };
+static const char * const ppi2_8bgrp[] = { "ppi2_8bgrp" };
+static const char * const atapigrp[] = { "atapigrp" };
+static const char * const atapialtergrp[] = { "atapialtergrp" };
+static const char * const nfc0grp[] = { "nfc0grp" };
+static const char * const keys_4x4grp[] = { "keys_4x4grp" };
+static const char * const keys_8x8grp[] = { "keys_8x8grp" };
+
+static const struct adi_pmx_func adi_pmx_functions[] = {
+ ADI_PMX_FUNCTION("uart0", uart0grp, uart0_mux),
+ ADI_PMX_FUNCTION("uart1", uart1grp, uart1_mux),
+ ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp, uart1_ctsrts_mux),
+ ADI_PMX_FUNCTION("uart2", uart2grp, uart2_mux),
+ ADI_PMX_FUNCTION("uart3", uart3grp, uart3_mux),
+ ADI_PMX_FUNCTION("uart3_ctsrts", uart3ctsrtsgrp, uart3_ctsrts_mux),
+ ADI_PMX_FUNCTION("rsi0", rsi0grp, rsi0_mux),
+ ADI_PMX_FUNCTION("spi0", spi0grp, spi0_mux),
+ ADI_PMX_FUNCTION("spi1", spi1grp, spi1_mux),
+ ADI_PMX_FUNCTION("twi0", twi0grp, twi0_mux),
+ ADI_PMX_FUNCTION("twi1", twi1grp, twi1_mux),
+ ADI_PMX_FUNCTION("rotary", rotarygrp, rotary_mux),
+ ADI_PMX_FUNCTION("can0", can0grp, can0_mux),
+ ADI_PMX_FUNCTION("can1", can1grp, can1_mux),
+ ADI_PMX_FUNCTION("smc0", smc0grp, smc0_mux),
+ ADI_PMX_FUNCTION("sport0", sport0grp, sport0_mux),
+ ADI_PMX_FUNCTION("sport1", sport1grp, sport1_mux),
+ ADI_PMX_FUNCTION("sport2", sport2grp, sport2_mux),
+ ADI_PMX_FUNCTION("sport3", sport3grp, sport3_mux),
+ ADI_PMX_FUNCTION("ppi0_8b", ppi0_8bgrp, ppi0_8b_mux),
+ ADI_PMX_FUNCTION("ppi0_16b", ppi0_16bgrp, ppi0_16b_mux),
+ ADI_PMX_FUNCTION("ppi0_24b", ppi0_24bgrp, ppi0_24b_mux),
+ ADI_PMX_FUNCTION("ppi1_8b", ppi1_8bgrp, ppi1_8b_mux),
+ ADI_PMX_FUNCTION("ppi1_16b", ppi1_16bgrp, ppi1_16b_mux),
+ ADI_PMX_FUNCTION("ppi2_8b", ppi2_8bgrp, ppi2_8b_mux),
+ ADI_PMX_FUNCTION("atapi", atapigrp, atapi_mux),
+ ADI_PMX_FUNCTION("atapi_alter", atapialtergrp, atapi_alter_mux),
+ ADI_PMX_FUNCTION("nfc0", nfc0grp, nfc0_mux),
+ ADI_PMX_FUNCTION("keys_4x4", keys_4x4grp, keys_4x4_mux),
+ ADI_PMX_FUNCTION("keys_8x8", keys_8x8grp, keys_8x8_mux),
+};
+
+static const struct adi_pinctrl_soc_data adi_bf54x_soc = {
+ .functions = adi_pmx_functions,
+ .nfunctions = ARRAY_SIZE(adi_pmx_functions),
+ .groups = adi_pin_groups,
+ .ngroups = ARRAY_SIZE(adi_pin_groups),
+ .pins = adi_pads,
+ .npins = ARRAY_SIZE(adi_pads),
+};
+
+void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc)
+{
+ *soc = &adi_bf54x_soc;
+}
--- /dev/null
+/*
+ * Pinctrl Driver for ADI GPIO2 controller
+ *
+ * Copyright 2007-2013 Analog Devices Inc.
+ *
+ * Licensed under the GPLv2 or later
+ */
+
+#include <asm/portmux.h>
+#include "pinctrl-adi2.h"
+
+static const struct pinctrl_pin_desc adi_pads[] = {
+ PINCTRL_PIN(0, "PA0"),
+ PINCTRL_PIN(1, "PA1"),
+ PINCTRL_PIN(2, "PA2"),
+ PINCTRL_PIN(3, "PG3"),
+ PINCTRL_PIN(4, "PA4"),
+ PINCTRL_PIN(5, "PA5"),
+ PINCTRL_PIN(6, "PA6"),
+ PINCTRL_PIN(7, "PA7"),
+ PINCTRL_PIN(8, "PA8"),
+ PINCTRL_PIN(9, "PA9"),
+ PINCTRL_PIN(10, "PA10"),
+ PINCTRL_PIN(11, "PA11"),
+ PINCTRL_PIN(12, "PA12"),
+ PINCTRL_PIN(13, "PA13"),
+ PINCTRL_PIN(14, "PA14"),
+ PINCTRL_PIN(15, "PA15"),
+ PINCTRL_PIN(16, "PB0"),
+ PINCTRL_PIN(17, "PB1"),
+ PINCTRL_PIN(18, "PB2"),
+ PINCTRL_PIN(19, "PB3"),
+ PINCTRL_PIN(20, "PB4"),
+ PINCTRL_PIN(21, "PB5"),
+ PINCTRL_PIN(22, "PB6"),
+ PINCTRL_PIN(23, "PB7"),
+ PINCTRL_PIN(24, "PB8"),
+ PINCTRL_PIN(25, "PB9"),
+ PINCTRL_PIN(26, "PB10"),
+ PINCTRL_PIN(27, "PB11"),
+ PINCTRL_PIN(28, "PB12"),
+ PINCTRL_PIN(29, "PB13"),
+ PINCTRL_PIN(30, "PB14"),
+ PINCTRL_PIN(31, "PB15"),
+ PINCTRL_PIN(32, "PC0"),
+ PINCTRL_PIN(33, "PC1"),
+ PINCTRL_PIN(34, "PC2"),
+ PINCTRL_PIN(35, "PC3"),
+ PINCTRL_PIN(36, "PC4"),
+ PINCTRL_PIN(37, "PC5"),
+ PINCTRL_PIN(38, "PC6"),
+ PINCTRL_PIN(39, "PC7"),
+ PINCTRL_PIN(40, "PC8"),
+ PINCTRL_PIN(41, "PC9"),
+ PINCTRL_PIN(42, "PC10"),
+ PINCTRL_PIN(43, "PC11"),
+ PINCTRL_PIN(44, "PC12"),
+ PINCTRL_PIN(45, "PC13"),
+ PINCTRL_PIN(46, "PC14"),
+ PINCTRL_PIN(47, "PC15"),
+ PINCTRL_PIN(48, "PD0"),
+ PINCTRL_PIN(49, "PD1"),
+ PINCTRL_PIN(50, "PD2"),
+ PINCTRL_PIN(51, "PD3"),
+ PINCTRL_PIN(52, "PD4"),
+ PINCTRL_PIN(53, "PD5"),
+ PINCTRL_PIN(54, "PD6"),
+ PINCTRL_PIN(55, "PD7"),
+ PINCTRL_PIN(56, "PD8"),
+ PINCTRL_PIN(57, "PD9"),
+ PINCTRL_PIN(58, "PD10"),
+ PINCTRL_PIN(59, "PD11"),
+ PINCTRL_PIN(60, "PD12"),
+ PINCTRL_PIN(61, "PD13"),
+ PINCTRL_PIN(62, "PD14"),
+ PINCTRL_PIN(63, "PD15"),
+ PINCTRL_PIN(64, "PE0"),
+ PINCTRL_PIN(65, "PE1"),
+ PINCTRL_PIN(66, "PE2"),
+ PINCTRL_PIN(67, "PE3"),
+ PINCTRL_PIN(68, "PE4"),
+ PINCTRL_PIN(69, "PE5"),
+ PINCTRL_PIN(70, "PE6"),
+ PINCTRL_PIN(71, "PE7"),
+ PINCTRL_PIN(72, "PE8"),
+ PINCTRL_PIN(73, "PE9"),
+ PINCTRL_PIN(74, "PE10"),
+ PINCTRL_PIN(75, "PE11"),
+ PINCTRL_PIN(76, "PE12"),
+ PINCTRL_PIN(77, "PE13"),
+ PINCTRL_PIN(78, "PE14"),
+ PINCTRL_PIN(79, "PE15"),
+ PINCTRL_PIN(80, "PF0"),
+ PINCTRL_PIN(81, "PF1"),
+ PINCTRL_PIN(82, "PF2"),
+ PINCTRL_PIN(83, "PF3"),
+ PINCTRL_PIN(84, "PF4"),
+ PINCTRL_PIN(85, "PF5"),
+ PINCTRL_PIN(86, "PF6"),
+ PINCTRL_PIN(87, "PF7"),
+ PINCTRL_PIN(88, "PF8"),
+ PINCTRL_PIN(89, "PF9"),
+ PINCTRL_PIN(90, "PF10"),
+ PINCTRL_PIN(91, "PF11"),
+ PINCTRL_PIN(92, "PF12"),
+ PINCTRL_PIN(93, "PF13"),
+ PINCTRL_PIN(94, "PF14"),
+ PINCTRL_PIN(95, "PF15"),
+ PINCTRL_PIN(96, "PG0"),
+ PINCTRL_PIN(97, "PG1"),
+ PINCTRL_PIN(98, "PG2"),
+ PINCTRL_PIN(99, "PG3"),
+ PINCTRL_PIN(100, "PG4"),
+ PINCTRL_PIN(101, "PG5"),
+ PINCTRL_PIN(102, "PG6"),
+ PINCTRL_PIN(103, "PG7"),
+ PINCTRL_PIN(104, "PG8"),
+ PINCTRL_PIN(105, "PG9"),
+ PINCTRL_PIN(106, "PG10"),
+ PINCTRL_PIN(107, "PG11"),
+ PINCTRL_PIN(108, "PG12"),
+ PINCTRL_PIN(109, "PG13"),
+ PINCTRL_PIN(110, "PG14"),
+ PINCTRL_PIN(111, "PG15"),
+};
+
+static const unsigned uart0_pins[] = {
+ GPIO_PD7, GPIO_PD8,
+};
+
+static const unsigned uart0_ctsrts_pins[] = {
+ GPIO_PD9, GPIO_PD10,
+};
+
+static const unsigned uart1_pins[] = {
+ GPIO_PG15, GPIO_PG14,
+};
+
+static const unsigned uart1_ctsrts_pins[] = {
+ GPIO_PG10, GPIO_PG13,
+};
+
+static const unsigned rsi0_pins[] = {
+ GPIO_PG3, GPIO_PG2, GPIO_PG0, GPIO_PE15, GPIO_PG5, GPIO_PG6,
+};
+
+static const unsigned eth0_pins[] = {
+ GPIO_PC6, GPIO_PC7, GPIO_PC2, GPIO_PC0, GPIO_PC3, GPIO_PC1,
+ GPIO_PB13, GPIO_PD6, GPIO_PC5, GPIO_PC4, GPIO_PB14, GPIO_PB15,
+};
+
+static const unsigned eth1_pins[] = {
+ GPIO_PE10, GPIO_PE11, GPIO_PG3, GPIO_PG0, GPIO_PG2, GPIO_PE15,
+ GPIO_PG5, GPIO_PE12, GPIO_PE13, GPIO_PE14, GPIO_PG6, GPIO_PC9,
+};
+
+static const unsigned spi0_pins[] = {
+ GPIO_PD4, GPIO_PD2, GPIO_PD3,
+};
+
+static const unsigned spi1_pins[] = {
+ GPIO_PD5, GPIO_PD14, GPIO_PD13,
+};
+
+static const unsigned twi0_pins[] = {
+};
+
+static const unsigned twi1_pins[] = {
+};
+
+static const unsigned rotary_pins[] = {
+ GPIO_PG7, GPIO_PG11, GPIO_PG12,
+};
+
+static const unsigned can0_pins[] = {
+ GPIO_PG1, GPIO_PG4,
+};
+
+static const unsigned smc0_pins[] = {
+ GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6,
+ GPIO_PA7, GPIO_PA8, GPIO_PA9, GPIO_PB2, GPIO_PA10, GPIO_PA11,
+ GPIO_PB3, GPIO_PA12, GPIO_PA13, GPIO_PA14, GPIO_PA15, GPIO_PB6,
+ GPIO_PB7, GPIO_PB8, GPIO_PB10, GPIO_PB11, GPIO_PB0,
+};
+
+static const unsigned sport0_pins[] = {
+ GPIO_PB5, GPIO_PB4, GPIO_PB9, GPIO_PB8, GPIO_PB7, GPIO_PB11,
+};
+
+static const unsigned sport1_pins[] = {
+ GPIO_PE2, GPIO_PE5, GPIO_PD15, GPIO_PE4, GPIO_PE3, GPIO_PE1,
+};
+
+static const unsigned sport2_pins[] = {
+ GPIO_PG4, GPIO_PG1, GPIO_PG9, GPIO_PG10, GPIO_PG7, GPIO_PB12,
+};
+
+static const unsigned ppi0_8b_pins[] = {
+ GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
+ GPIO_PF7, GPIO_PF13, GPIO_PF14, GPIO_PF15,
+ GPIO_PE6, GPIO_PE7, GPIO_PE8, GPIO_PE9,
+};
+
+static const unsigned ppi0_16b_pins[] = {
+ GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
+ GPIO_PF7, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
+ GPIO_PF13, GPIO_PF14, GPIO_PF15,
+ GPIO_PE6, GPIO_PE7, GPIO_PE8, GPIO_PE9,
+};
+
+static const unsigned ppi0_24b_pins[] = {
+ GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
+ GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
+ GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PE0, GPIO_PE1, GPIO_PE2,
+ GPIO_PE3, GPIO_PE4, GPIO_PE5, GPIO_PE6, GPIO_PE7, GPIO_PE8,
+ GPIO_PE9, GPIO_PD12, GPIO_PD15,
+};
+
+static const unsigned ppi1_8b_pins[] = {
+ GPIO_PC0, GPIO_PC1, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC5, GPIO_PC6,
+ GPIO_PC7, GPIO_PC8, GPIO_PB13, GPIO_PB14, GPIO_PB15, GPIO_PD6,
+};
+
+static const unsigned ppi1_16b_pins[] = {
+ GPIO_PC0, GPIO_PC1, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC5, GPIO_PC6,
+ GPIO_PC7, GPIO_PC9, GPIO_PC10, GPIO_PC11, GPIO_PC12,
+ GPIO_PC13, GPIO_PC14, GPIO_PC15,
+ GPIO_PB13, GPIO_PB14, GPIO_PB15, GPIO_PD6,
+};
+
+static const unsigned ppi2_8b_pins[] = {
+ GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6,
+ GPIO_PA7, GPIO_PB0, GPIO_PB1, GPIO_PB2, GPIO_PB3,
+};
+
+static const unsigned ppi2_16b_pins[] = {
+ GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6,
+ GPIO_PA7, GPIO_PA8, GPIO_PA9, GPIO_PA10, GPIO_PA11, GPIO_PA12,
+ GPIO_PA13, GPIO_PA14, GPIO_PA15, GPIO_PB0, GPIO_PB1, GPIO_PB2,
+};
+
+static const unsigned lp0_pins[] = {
+ GPIO_PB0, GPIO_PB1, GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3,
+ GPIO_PA4, GPIO_PA5, GPIO_PA6, GPIO_PA7,
+};
+
+static const unsigned lp1_pins[] = {
+ GPIO_PB3, GPIO_PB2, GPIO_PA8, GPIO_PA9, GPIO_PA10, GPIO_PA11,
+ GPIO_PA12, GPIO_PA13, GPIO_PA14, GPIO_PA15,
+};
+
+static const unsigned lp2_pins[] = {
+ GPIO_PE6, GPIO_PE7, GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3,
+ GPIO_PF4, GPIO_PF5, GPIO_PF6, GPIO_PF7,
+};
+
+static const unsigned lp3_pins[] = {
+ GPIO_PE9, GPIO_PE8, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11,
+ GPIO_PF12, GPIO_PF13, GPIO_PF14, GPIO_PF15,
+};
+
+static const struct adi_pin_group adi_pin_groups[] = {
+ ADI_PIN_GROUP("uart0grp", uart0_pins),
+ ADI_PIN_GROUP("uart0ctsrtsgrp", uart0_ctsrts_pins),
+ ADI_PIN_GROUP("uart1grp", uart1_pins),
+ ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins),
+ ADI_PIN_GROUP("rsi0grp", rsi0_pins),
+ ADI_PIN_GROUP("eth0grp", eth0_pins),
+ ADI_PIN_GROUP("eth1grp", eth1_pins),
+ ADI_PIN_GROUP("spi0grp", spi0_pins),
+ ADI_PIN_GROUP("spi1grp", spi1_pins),
+ ADI_PIN_GROUP("twi0grp", twi0_pins),
+ ADI_PIN_GROUP("twi1grp", twi1_pins),
+ ADI_PIN_GROUP("rotarygrp", rotary_pins),
+ ADI_PIN_GROUP("can0grp", can0_pins),
+ ADI_PIN_GROUP("smc0grp", smc0_pins),
+ ADI_PIN_GROUP("sport0grp", sport0_pins),
+ ADI_PIN_GROUP("sport1grp", sport1_pins),
+ ADI_PIN_GROUP("sport2grp", sport2_pins),
+ ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins),
+ ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins),
+ ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins),
+ ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins),
+ ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins),
+ ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins),
+ ADI_PIN_GROUP("ppi2_16bgrp", ppi2_16b_pins),
+ ADI_PIN_GROUP("lp0grp", lp0_pins),
+ ADI_PIN_GROUP("lp1grp", lp1_pins),
+ ADI_PIN_GROUP("lp2grp", lp2_pins),
+ ADI_PIN_GROUP("lp3grp", lp3_pins),
+};
+
+static const unsigned short uart0_mux[] = {
+ P_UART0_TX, P_UART0_RX,
+ 0
+};
+
+static const unsigned short uart0_ctsrts_mux[] = {
+ P_UART0_RTS, P_UART0_CTS,
+ 0
+};
+
+static const unsigned short uart1_mux[] = {
+ P_UART1_TX, P_UART1_RX,
+ 0
+};
+
+static const unsigned short uart1_ctsrts_mux[] = {
+ P_UART1_RTS, P_UART1_CTS,
+ 0
+};
+
+static const unsigned short rsi0_mux[] = {
+ P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3,
+ P_RSI_CMD, P_RSI_CLK, 0
+};
+
+static const unsigned short eth0_mux[] = P_RMII0;
+static const unsigned short eth1_mux[] = P_RMII1;
+
+static const unsigned short spi0_mux[] = {
+ P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0
+};
+
+static const unsigned short spi1_mux[] = {
+ P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0
+};
+
+static const unsigned short twi0_mux[] = {
+ P_TWI0_SCL, P_TWI0_SDA, 0
+};
+
+static const unsigned short twi1_mux[] = {
+ P_TWI1_SCL, P_TWI1_SDA, 0
+};
+
+static const unsigned short rotary_mux[] = {
+ P_CNT_CUD, P_CNT_CDG, P_CNT_CZM, 0
+};
+
+static const unsigned short sport0_mux[] = {
+ P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
+ P_SPORT0_BFS, P_SPORT0_BD0, 0,
+};
+
+static const unsigned short sport1_mux[] = {
+ P_SPORT1_ACLK, P_SPORT1_AFS, P_SPORT1_AD0, P_SPORT1_BCLK,
+ P_SPORT1_BFS, P_SPORT1_BD0, 0,
+};
+
+static const unsigned short sport2_mux[] = {
+ P_SPORT2_ACLK, P_SPORT2_AFS, P_SPORT2_AD0, P_SPORT2_BCLK,
+ P_SPORT2_BFS, P_SPORT2_BD0, 0,
+};
+
+static const unsigned short can0_mux[] = {
+ P_CAN0_RX, P_CAN0_TX, 0
+};
+
+static const unsigned short smc0_mux[] = {
+ P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
+ P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
+ P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
+};
+
+static const unsigned short ppi0_8b_mux[] = {
+ P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
+ P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
+ P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
+ 0,
+};
+
+static const unsigned short ppi0_16b_mux[] = {
+ P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
+ P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
+ P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
+ P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
+ P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
+ 0,
+};
+
+static const unsigned short ppi0_24b_mux[] = {
+ P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
+ P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
+ P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
+ P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
+ P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
+ P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
+ P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
+ 0,
+};
+
+static const unsigned short ppi1_8b_mux[] = {
+ P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
+ P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
+ P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
+ 0,
+};
+
+static const unsigned short ppi1_16b_mux[] = {
+ P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
+ P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
+ P_PPI1_D8, P_PPI1_D9, P_PPI1_D10, P_PPI1_D11,
+ P_PPI1_D12, P_PPI1_D13, P_PPI1_D14, P_PPI1_D15,
+ P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
+ 0,
+};
+
+static const unsigned short ppi2_8b_mux[] = {
+ P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3,
+ P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7,
+ P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2,
+ 0,
+};
+
+static const unsigned short ppi2_16b_mux[] = {
+ P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3,
+ P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7,
+ P_PPI2_D8, P_PPI2_D9, P_PPI2_D10, P_PPI2_D11,
+ P_PPI2_D12, P_PPI2_D13, P_PPI2_D14, P_PPI2_D15,
+ P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2,
+ 0,
+};
+
+static const unsigned short lp0_mux[] = {
+ P_LP0_CLK, P_LP0_ACK, P_LP0_D0, P_LP0_D1, P_LP0_D2,
+ P_LP0_D3, P_LP0_D4, P_LP0_D5, P_LP0_D6, P_LP0_D7,
+ 0
+};
+
+static const unsigned short lp1_mux[] = {
+ P_LP1_CLK, P_LP1_ACK, P_LP1_D0, P_LP1_D1, P_LP1_D2,
+ P_LP1_D3, P_LP1_D4, P_LP1_D5, P_LP1_D6, P_LP1_D7,
+ 0
+};
+
+static const unsigned short lp2_mux[] = {
+ P_LP2_CLK, P_LP2_ACK, P_LP2_D0, P_LP2_D1, P_LP2_D2,
+ P_LP2_D3, P_LP2_D4, P_LP2_D5, P_LP2_D6, P_LP2_D7,
+ 0
+};
+
+static const unsigned short lp3_mux[] = {
+ P_LP3_CLK, P_LP3_ACK, P_LP3_D0, P_LP3_D1, P_LP3_D2,
+ P_LP3_D3, P_LP3_D4, P_LP3_D5, P_LP3_D6, P_LP3_D7,
+ 0
+};
+
+static const char * const uart0grp[] = { "uart0grp" };
+static const char * const uart0ctsrtsgrp[] = { "uart0ctsrtsgrp" };
+static const char * const uart1grp[] = { "uart1grp" };
+static const char * const uart1ctsrtsgrp[] = { "uart1ctsrtsgrp" };
+static const char * const rsi0grp[] = { "rsi0grp" };
+static const char * const eth0grp[] = { "eth0grp" };
+static const char * const eth1grp[] = { "eth1grp" };
+static const char * const spi0grp[] = { "spi0grp" };
+static const char * const spi1grp[] = { "spi1grp" };
+static const char * const twi0grp[] = { "twi0grp" };
+static const char * const twi1grp[] = { "twi1grp" };
+static const char * const rotarygrp[] = { "rotarygrp" };
+static const char * const can0grp[] = { "can0grp" };
+static const char * const smc0grp[] = { "smc0grp" };
+static const char * const sport0grp[] = { "sport0grp" };
+static const char * const sport1grp[] = { "sport1grp" };
+static const char * const sport2grp[] = { "sport2grp" };
+static const char * const ppi0_8bgrp[] = { "ppi0_8bgrp" };
+static const char * const ppi0_16bgrp[] = { "ppi0_16bgrp" };
+static const char * const ppi0_24bgrp[] = { "ppi0_24bgrp" };
+static const char * const ppi1_8bgrp[] = { "ppi1_8bgrp" };
+static const char * const ppi1_16bgrp[] = { "ppi1_16bgrp" };
+static const char * const ppi2_8bgrp[] = { "ppi2_8bgrp" };
+static const char * const ppi2_16bgrp[] = { "ppi2_16bgrp" };
+static const char * const lp0grp[] = { "lp0grp" };
+static const char * const lp1grp[] = { "lp1grp" };
+static const char * const lp2grp[] = { "lp2grp" };
+static const char * const lp3grp[] = { "lp3grp" };
+
+static const struct adi_pmx_func adi_pmx_functions[] = {
+ ADI_PMX_FUNCTION("uart0", uart0grp, uart0_mux),
+ ADI_PMX_FUNCTION("uart0_ctsrts", uart0ctsrtsgrp, uart0_ctsrts_mux),
+ ADI_PMX_FUNCTION("uart1", uart1grp, uart1_mux),
+ ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp, uart1_ctsrts_mux),
+ ADI_PMX_FUNCTION("rsi0", rsi0grp, rsi0_mux),
+ ADI_PMX_FUNCTION("eth0", eth0grp, eth0_mux),
+ ADI_PMX_FUNCTION("eth1", eth1grp, eth1_mux),
+ ADI_PMX_FUNCTION("spi0", spi0grp, spi0_mux),
+ ADI_PMX_FUNCTION("spi1", spi1grp, spi1_mux),
+ ADI_PMX_FUNCTION("twi0", twi0grp, twi0_mux),
+ ADI_PMX_FUNCTION("twi1", twi1grp, twi1_mux),
+ ADI_PMX_FUNCTION("rotary", rotarygrp, rotary_mux),
+ ADI_PMX_FUNCTION("can0", can0grp, can0_mux),
+ ADI_PMX_FUNCTION("smc0", smc0grp, smc0_mux),
+ ADI_PMX_FUNCTION("sport0", sport0grp, sport0_mux),
+ ADI_PMX_FUNCTION("sport1", sport1grp, sport1_mux),
+ ADI_PMX_FUNCTION("sport2", sport2grp, sport2_mux),
+ ADI_PMX_FUNCTION("ppi0_8b", ppi0_8bgrp, ppi0_8b_mux),
+ ADI_PMX_FUNCTION("ppi0_16b", ppi0_16bgrp, ppi0_16b_mux),
+ ADI_PMX_FUNCTION("ppi0_24b", ppi0_24bgrp, ppi0_24b_mux),
+ ADI_PMX_FUNCTION("ppi1_8b", ppi1_8bgrp, ppi1_8b_mux),
+ ADI_PMX_FUNCTION("ppi1_16b", ppi1_16bgrp, ppi1_16b_mux),
+ ADI_PMX_FUNCTION("ppi2_8b", ppi2_8bgrp, ppi2_8b_mux),
+ ADI_PMX_FUNCTION("ppi2_16b", ppi2_16bgrp, ppi2_16b_mux),
+ ADI_PMX_FUNCTION("lp0", lp0grp, lp0_mux),
+ ADI_PMX_FUNCTION("lp1", lp1grp, lp1_mux),
+ ADI_PMX_FUNCTION("lp2", lp2grp, lp2_mux),
+ ADI_PMX_FUNCTION("lp3", lp3grp, lp3_mux),
+};
+
+static const struct adi_pinctrl_soc_data adi_bf60x_soc = {
+ .functions = adi_pmx_functions,
+ .nfunctions = ARRAY_SIZE(adi_pmx_functions),
+ .groups = adi_pin_groups,
+ .ngroups = ARRAY_SIZE(adi_pin_groups),
+ .pins = adi_pads,
+ .npins = ARRAY_SIZE(adi_pads),
+};
+
+void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc)
+{
+ *soc = &adi_bf60x_soc;
+}
--- /dev/null
+/*
+ * Pinctrl Driver for ADI GPIO2 controller
+ *
+ * Copyright 2007-2013 Analog Devices Inc.
+ *
+ * Licensed under the GPLv2 or later
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/irq.h>
+#include <linux/platform_data/pinctrl-adi2.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/syscore_ops.h>
+#include <linux/gpio.h>
+#include <asm/portmux.h>
+#include "pinctrl-adi2.h"
+#include "core.h"
+
+/*
+According to the BF54x HRM, pint means "pin interrupt".
+http://www.analog.com/static/imported-files/processor_manuals/ADSP-BF54x_hwr_rev1.2.pdf
+
+ADSP-BF54x processor Blackfin processors have four SIC interrupt chan-
+nels dedicated to pin interrupt purposes. These channels are managed by
+four hardware blocks, called PINT0, PINT1, PINT2, and PINT3. Every PINTx
+block can sense to up to 32 pins. While PINT0 and PINT1 can sense the
+pins of port A and port B, PINT2 and PINT3 manage all the pins from port
+C to port J as shown in Figure 9-2.
+
+n BF54x HRM:
+The ten GPIO ports are subdivided into 8-bit half ports, resulting in lower and
+upper half 8-bit units. The PINTx_ASSIGN registers control the 8-bit multi-
+plexers shown in Figure 9-3. Lower half units of eight pins can be
+forwarded to either byte 0 or byte 2 of either associated PINTx block.
+Upper half units can be forwarded to either byte 1 or byte 3 of the pin
+interrupt blocks, without further restrictions.
+
+All MMR registers in the pin interrupt module are 32 bits wide. To simply the
+mapping logic, this driver only maps a 16-bit gpio port to the upper or lower
+16 bits of a PINTx block. You can find the Figure 9-3 on page 583.
+
+Each IRQ domain is binding to a GPIO bank device. 2 GPIO bank devices can map
+to one PINT device. Two in "struct gpio_pint" are used to ease the PINT
+interrupt handler.
+
+The GPIO bank mapping to the lower 16 bits of the PINT device set its IRQ
+domain pointer in domain[0]. The IRQ domain pointer of the other bank is set
+to domain[1]. PINT interrupt handler adi_gpio_handle_pint_irq() finds out
+the current domain pointer according to whether the interrupt request mask
+is in lower 16 bits (domain[0]) or upper 16bits (domain[1]).
+
+A PINT device is not part of a GPIO port device in Blackfin. Multiple GPIO
+port devices can be mapped to the same PINT device.
+
+*/
+
+static LIST_HEAD(adi_pint_list);
+static LIST_HEAD(adi_gpio_port_list);
+
+#define DRIVER_NAME "pinctrl-adi2"
+
+#define PINT_HI_OFFSET 16
+
+/**
+ * struct gpio_port_saved - GPIO port registers that should be saved between
+ * power suspend and resume operations.
+ *
+ * @fer: PORTx_FER register
+ * @data: PORTx_DATA register
+ * @dir: PORTx_DIR register
+ * @inen: PORTx_INEN register
+ * @mux: PORTx_MUX register
+ */
+struct gpio_port_saved {
+ u16 fer;
+ u16 data;
+ u16 dir;
+ u16 inen;
+ u32 mux;
+};
+
+/**
+ * struct gpio_pint - Pin interrupt controller device. Multiple ADI GPIO
+ * banks can be mapped into one Pin interrupt controller.
+ *
+ * @node: All gpio_pint instances are added to a global list.
+ * @base: PINT device register base address
+ * @irq: IRQ of the PINT device, it is the parent IRQ of all
+ * GPIO IRQs mapping to this device.
+ * @domain: [0] irq domain of the gpio port, whose hardware interrupts are
+ * mapping to the low 16-bit of the pint registers.
+ * [1] irq domain of the gpio port, whose hardware interrupts are
+ * mapping to the high 16-bit of the pint registers.
+ * @regs: address pointer to the PINT device
+ * @map_count: No more than 2 GPIO banks can be mapped to this PINT device.
+ * @lock: This lock make sure the irq_chip operations to one PINT device
+ * for different GPIO interrrupts are atomic.
+ * @pint_map_port: Set up the mapping between one PINT device and
+ * multiple GPIO banks.
+ */
+struct gpio_pint {
+ struct list_head node;
+ void __iomem *base;
+ int irq;
+ struct irq_domain *domain[2];
+ struct gpio_pint_regs *regs;
+ struct adi_pm_pint_save saved_data;
+ int map_count;
+ spinlock_t lock;
+
+ int (*pint_map_port)(struct gpio_pint *pint, bool assign,
+ u8 map, struct irq_domain *domain);
+};
+
+/**
+ * ADI pin controller
+ *
+ * @dev: a pointer back to containing device
+ * @pctl: the pinctrl device
+ * @soc: SoC data for this specific chip
+ */
+struct adi_pinctrl {
+ struct device *dev;
+ struct pinctrl_dev *pctl;
+ const struct adi_pinctrl_soc_data *soc;
+};
+
+/**
+ * struct gpio_port - GPIO bank device. Multiple ADI GPIO banks can be mapped
+ * into one pin interrupt controller.
+ *
+ * @node: All gpio_port instances are added to a list.
+ * @base: GPIO bank device register base address
+ * @irq_base: base IRQ of the GPIO bank device
+ * @width: PIN number of the GPIO bank device
+ * @regs: address pointer to the GPIO bank device
+ * @saved_data: registers that should be saved between PM operations.
+ * @dev: device structure of this GPIO bank
+ * @pint: GPIO PINT device that this GPIO bank mapped to
+ * @pint_map: GIOP bank mapping code in PINT device
+ * @pint_assign: The 32-bit PINT registers can be divided into 2 parts. A
+ * GPIO bank can be mapped into either low 16 bits[0] or high 16
+ * bits[1] of each PINT register.
+ * @lock: This lock make sure the irq_chip operations to one PINT device
+ * for different GPIO interrrupts are atomic.
+ * @chip: abstract a GPIO controller
+ * @domain: The irq domain owned by the GPIO port.
+ * @rsvmap: Reservation map array for each pin in the GPIO bank
+ */
+struct gpio_port {
+ struct list_head node;
+ void __iomem *base;
+ unsigned int irq_base;
+ unsigned int width;
+ struct gpio_port_t *regs;
+ struct gpio_port_saved saved_data;
+ struct device *dev;
+
+ struct gpio_pint *pint;
+ u8 pint_map;
+ bool pint_assign;
+
+ spinlock_t lock;
+ struct gpio_chip chip;
+ struct irq_domain *domain;
+};
+
+static inline u8 pin_to_offset(struct pinctrl_gpio_range *range, unsigned pin)
+{
+ return pin - range->pin_base;
+}
+
+static inline u32 hwirq_to_pintbit(struct gpio_port *port, int hwirq)
+{
+ return port->pint_assign ? BIT(hwirq) << PINT_HI_OFFSET : BIT(hwirq);
+}
+
+static struct gpio_pint *find_gpio_pint(unsigned id)
+{
+ struct gpio_pint *pint;
+ int i = 0;
+
+ list_for_each_entry(pint, &adi_pint_list, node) {
+ if (id == i)
+ return pint;
+ i++;
+ }
+
+ return NULL;
+}
+
+static inline void port_setup(struct gpio_port *port, unsigned offset,
+ bool use_for_gpio)
+{
+ struct gpio_port_t *regs = port->regs;
+
+ if (use_for_gpio)
+ writew(readw(®s->port_fer) & ~BIT(offset),
+ ®s->port_fer);
+ else
+ writew(readw(®s->port_fer) | BIT(offset), ®s->port_fer);
+}
+
+static inline void portmux_setup(struct gpio_port *port, unsigned offset,
+ unsigned short function)
+{
+ struct gpio_port_t *regs = port->regs;
+ u32 pmux;
+
+ pmux = readl(®s->port_mux);
+
+ /* The function field of each pin has 2 consecutive bits in
+ * the mux register.
+ */
+ pmux &= ~(0x3 << (2 * offset));
+ pmux |= (function & 0x3) << (2 * offset);
+
+ writel(pmux, ®s->port_mux);
+}
+
+static inline u16 get_portmux(struct gpio_port *port, unsigned offset)
+{
+ struct gpio_port_t *regs = port->regs;
+ u32 pmux = readl(®s->port_mux);
+
+ /* The function field of each pin has 2 consecutive bits in
+ * the mux register.
+ */
+ return pmux >> (2 * offset) & 0x3;
+}
+
+static void adi_gpio_ack_irq(struct irq_data *d)
+{
+ unsigned long flags;
+ struct gpio_port *port = irq_data_get_irq_chip_data(d);
+ struct gpio_pint_regs *regs = port->pint->regs;
+ unsigned pintbit = hwirq_to_pintbit(port, d->hwirq);
+
+ spin_lock_irqsave(&port->lock, flags);
+ spin_lock(&port->pint->lock);
+
+ if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
+ if (readl(®s->invert_set) & pintbit)
+ writel(pintbit, ®s->invert_clear);
+ else
+ writel(pintbit, ®s->invert_set);
+ }
+
+ writel(pintbit, ®s->request);
+
+ spin_unlock(&port->pint->lock);
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static void adi_gpio_mask_ack_irq(struct irq_data *d)
+{
+ unsigned long flags;
+ struct gpio_port *port = irq_data_get_irq_chip_data(d);
+ struct gpio_pint_regs *regs = port->pint->regs;
+ unsigned pintbit = hwirq_to_pintbit(port, d->hwirq);
+
+ spin_lock_irqsave(&port->lock, flags);
+ spin_lock(&port->pint->lock);
+
+ if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
+ if (readl(®s->invert_set) & pintbit)
+ writel(pintbit, ®s->invert_clear);
+ else
+ writel(pintbit, ®s->invert_set);
+ }
+
+ writel(pintbit, ®s->request);
+ writel(pintbit, ®s->mask_clear);
+
+ spin_unlock(&port->pint->lock);
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static void adi_gpio_mask_irq(struct irq_data *d)
+{
+ unsigned long flags;
+ struct gpio_port *port = irq_data_get_irq_chip_data(d);
+ struct gpio_pint_regs *regs = port->pint->regs;
+
+ spin_lock_irqsave(&port->lock, flags);
+ spin_lock(&port->pint->lock);
+
+ writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_clear);
+
+ spin_unlock(&port->pint->lock);
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static void adi_gpio_unmask_irq(struct irq_data *d)
+{
+ unsigned long flags;
+ struct gpio_port *port = irq_data_get_irq_chip_data(d);
+ struct gpio_pint_regs *regs = port->pint->regs;
+
+ spin_lock_irqsave(&port->lock, flags);
+ spin_lock(&port->pint->lock);
+
+ writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_set);
+
+ spin_unlock(&port->pint->lock);
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static unsigned int adi_gpio_irq_startup(struct irq_data *d)
+{
+ unsigned long flags;
+ struct gpio_port *port = irq_data_get_irq_chip_data(d);
+ struct gpio_pint_regs *regs;
+
+ if (!port) {
+ pr_err("GPIO IRQ %d :Not exist\n", d->irq);
+ return -ENODEV;
+ }
+
+ regs = port->pint->regs;
+
+ spin_lock_irqsave(&port->lock, flags);
+ spin_lock(&port->pint->lock);
+
+ port_setup(port, d->hwirq, true);
+ writew(BIT(d->hwirq), &port->regs->dir_clear);
+ writew(readw(&port->regs->inen) | BIT(d->hwirq), &port->regs->inen);
+
+ writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_set);
+
+ spin_unlock(&port->pint->lock);
+ spin_unlock_irqrestore(&port->lock, flags);
+
+ return 0;
+}
+
+static void adi_gpio_irq_shutdown(struct irq_data *d)
+{
+ unsigned long flags;
+ struct gpio_port *port = irq_data_get_irq_chip_data(d);
+ struct gpio_pint_regs *regs = port->pint->regs;
+
+ spin_lock_irqsave(&port->lock, flags);
+ spin_lock(&port->pint->lock);
+
+ writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_clear);
+
+ spin_unlock(&port->pint->lock);
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static int adi_gpio_irq_type(struct irq_data *d, unsigned int type)
+{
+ unsigned long flags;
+ struct gpio_port *port = irq_data_get_irq_chip_data(d);
+ struct gpio_pint_regs *pint_regs;
+ unsigned pintmask;
+ unsigned int irq = d->irq;
+ int ret = 0;
+ char buf[16];
+
+ if (!port) {
+ pr_err("GPIO IRQ %d :Not exist\n", d->irq);
+ return -ENODEV;
+ }
+
+ pint_regs = port->pint->regs;
+
+ pintmask = hwirq_to_pintbit(port, d->hwirq);
+
+ spin_lock_irqsave(&port->lock, flags);
+ spin_lock(&port->pint->lock);
+
+ /* In case of interrupt autodetect, set irq type to edge sensitive. */
+ if (type == IRQ_TYPE_PROBE)
+ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
+
+ if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
+ IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
+ snprintf(buf, 16, "gpio-irq%d", irq);
+ port_setup(port, d->hwirq, true);
+ } else
+ goto out;
+
+ /* The GPIO interrupt is triggered only when its input value
+ * transfer from 0 to 1. So, invert the input value if the
+ * irq type is low or falling
+ */
+ if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
+ writel(pintmask, &pint_regs->invert_set);
+ else
+ writel(pintmask, &pint_regs->invert_clear);
+
+ /* In edge sensitive case, if the input value of the requested irq
+ * is already 1, invert it.
+ */
+ if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
+ if (gpio_get_value(port->chip.base + d->hwirq))
+ writel(pintmask, &pint_regs->invert_set);
+ else
+ writel(pintmask, &pint_regs->invert_clear);
+ }
+
+ if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
+ writel(pintmask, &pint_regs->edge_set);
+ __irq_set_handler_locked(irq, handle_edge_irq);
+ } else {
+ writel(pintmask, &pint_regs->edge_clear);
+ __irq_set_handler_locked(irq, handle_level_irq);
+ }
+
+out:
+ spin_unlock(&port->pint->lock);
+ spin_unlock_irqrestore(&port->lock, flags);
+
+ return ret;
+}
+
+#ifdef CONFIG_PM
+static int adi_gpio_set_wake(struct irq_data *d, unsigned int state)
+{
+ struct gpio_port *port = irq_data_get_irq_chip_data(d);
+
+ if (!port || !port->pint || port->pint->irq != d->irq)
+ return -EINVAL;
+
+#ifndef SEC_GCTL
+ adi_internal_set_wake(port->pint->irq, state);
+#endif
+
+ return 0;
+}
+
+static int adi_pint_suspend(void)
+{
+ struct gpio_pint *pint;
+
+ list_for_each_entry(pint, &adi_pint_list, node) {
+ writel(0xffffffff, &pint->regs->mask_clear);
+ pint->saved_data.assign = readl(&pint->regs->assign);
+ pint->saved_data.edge_set = readl(&pint->regs->edge_set);
+ pint->saved_data.invert_set = readl(&pint->regs->invert_set);
+ }
+
+ return 0;
+}
+
+static void adi_pint_resume(void)
+{
+ struct gpio_pint *pint;
+
+ list_for_each_entry(pint, &adi_pint_list, node) {
+ writel(pint->saved_data.assign, &pint->regs->assign);
+ writel(pint->saved_data.edge_set, &pint->regs->edge_set);
+ writel(pint->saved_data.invert_set, &pint->regs->invert_set);
+ }
+}
+
+static int adi_gpio_suspend(void)
+{
+ struct gpio_port *port;
+
+ list_for_each_entry(port, &adi_gpio_port_list, node) {
+ port->saved_data.fer = readw(&port->regs->port_fer);
+ port->saved_data.mux = readl(&port->regs->port_mux);
+ port->saved_data.data = readw(&port->regs->data);
+ port->saved_data.inen = readw(&port->regs->inen);
+ port->saved_data.dir = readw(&port->regs->dir_set);
+ }
+
+ return adi_pint_suspend();
+}
+
+static void adi_gpio_resume(void)
+{
+ struct gpio_port *port;
+
+ adi_pint_resume();
+
+ list_for_each_entry(port, &adi_gpio_port_list, node) {
+ writel(port->saved_data.mux, &port->regs->port_mux);
+ writew(port->saved_data.fer, &port->regs->port_fer);
+ writew(port->saved_data.inen, &port->regs->inen);
+ writew(port->saved_data.data & port->saved_data.dir,
+ &port->regs->data_set);
+ writew(port->saved_data.dir, &port->regs->dir_set);
+ }
+
+}
+
+static struct syscore_ops gpio_pm_syscore_ops = {
+ .suspend = adi_gpio_suspend,
+ .resume = adi_gpio_resume,
+};
+#else /* CONFIG_PM */
+#define adi_gpio_set_wake NULL
+#endif /* CONFIG_PM */
+
+#ifdef CONFIG_IRQ_PREFLOW_FASTEOI
+static inline void preflow_handler(struct irq_desc *desc)
+{
+ if (desc->preflow_handler)
+ desc->preflow_handler(&desc->irq_data);
+}
+#else
+static inline void preflow_handler(struct irq_desc *desc) { }
+#endif
+
+static void adi_gpio_handle_pint_irq(unsigned int inta_irq,
+ struct irq_desc *desc)
+{
+ u32 request;
+ u32 level_mask, hwirq;
+ bool umask = false;
+ struct gpio_pint *pint = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct gpio_pint_regs *regs = pint->regs;
+ struct irq_domain *domain;
+
+ preflow_handler(desc);
+ chained_irq_enter(chip, desc);
+
+ request = readl(®s->request);
+ level_mask = readl(®s->edge_set) & request;
+
+ hwirq = 0;
+ domain = pint->domain[0];
+ while (request) {
+ /* domain pointer need to be changed only once at IRQ 16 when
+ * we go through IRQ requests from bit 0 to bit 31.
+ */
+ if (hwirq == PINT_HI_OFFSET)
+ domain = pint->domain[1];
+
+ if (request & 1) {
+ if (level_mask & BIT(hwirq)) {
+ umask = true;
+ chained_irq_exit(chip, desc);
+ }
+ generic_handle_irq(irq_find_mapping(domain,
+ hwirq % PINT_HI_OFFSET));
+ }
+
+ hwirq++;
+ request >>= 1;
+ }
+
+ if (!umask)
+ chained_irq_exit(chip, desc);
+}
+
+static struct irq_chip adi_gpio_irqchip = {
+ .name = "GPIO",
+ .irq_ack = adi_gpio_ack_irq,
+ .irq_mask = adi_gpio_mask_irq,
+ .irq_mask_ack = adi_gpio_mask_ack_irq,
+ .irq_unmask = adi_gpio_unmask_irq,
+ .irq_disable = adi_gpio_mask_irq,
+ .irq_enable = adi_gpio_unmask_irq,
+ .irq_set_type = adi_gpio_irq_type,
+ .irq_startup = adi_gpio_irq_startup,
+ .irq_shutdown = adi_gpio_irq_shutdown,
+ .irq_set_wake = adi_gpio_set_wake,
+};
+
+static int adi_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pinctrl->soc->ngroups;
+}
+
+static const char *adi_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned selector)
+{
+ struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pinctrl->soc->groups[selector].name;
+}
+
+static int adi_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
+ const unsigned **pins,
+ unsigned *num_pins)
+{
+ struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = pinctrl->soc->groups[selector].pins;
+ *num_pins = pinctrl->soc->groups[selector].num;
+ return 0;
+}
+
+static struct pinctrl_ops adi_pctrl_ops = {
+ .get_groups_count = adi_get_groups_count,
+ .get_group_name = adi_get_group_name,
+ .get_group_pins = adi_get_group_pins,
+};
+
+static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
+ unsigned group)
+{
+ struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
+ struct gpio_port *port;
+ struct pinctrl_gpio_range *range;
+ unsigned long flags;
+ unsigned short *mux, pin;
+
+ mux = (unsigned short *)pinctrl->soc->functions[selector].mux;
+
+ while (*mux) {
+ pin = P_IDENT(*mux);
+
+ range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
+ if (range == NULL) /* should not happen */
+ return -ENODEV;
+
+ port = container_of(range->gc, struct gpio_port, chip);
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ portmux_setup(port, pin_to_offset(range, pin),
+ P_FUNCT2MUX(*mux));
+ port_setup(port, pin_to_offset(range, pin), false);
+ mux++;
+
+ spin_unlock_irqrestore(&port->lock, flags);
+ }
+
+ return 0;
+}
+
+static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned selector,
+ unsigned group)
+{
+ struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
+ struct gpio_port *port;
+ struct pinctrl_gpio_range *range;
+ unsigned long flags;
+ unsigned short *mux, pin;
+
+ mux = (unsigned short *)pinctrl->soc->functions[selector].mux;
+
+ while (*mux) {
+ pin = P_IDENT(*mux);
+
+ range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
+ if (range == NULL) /* should not happen */
+ return;
+
+ port = container_of(range->gc, struct gpio_port, chip);
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ port_setup(port, pin_to_offset(range, pin), true);
+ mux++;
+
+ spin_unlock_irqrestore(&port->lock, flags);
+ }
+}
+
+static int adi_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+ struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pinctrl->soc->nfunctions;
+}
+
+static const char *adi_pinmux_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned selector)
+{
+ struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pinctrl->soc->functions[selector].name;
+}
+
+static int adi_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
+ const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = pinctrl->soc->functions[selector].groups;
+ *num_groups = pinctrl->soc->functions[selector].num_groups;
+ return 0;
+}
+
+static int adi_pinmux_request_gpio(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range, unsigned pin)
+{
+ struct gpio_port *port;
+ unsigned long flags;
+ u8 offset;
+
+ port = container_of(range->gc, struct gpio_port, chip);
+ offset = pin_to_offset(range, pin);
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ port_setup(port, offset, true);
+
+ spin_unlock_irqrestore(&port->lock, flags);
+
+ return 0;
+}
+
+static struct pinmux_ops adi_pinmux_ops = {
+ .enable = adi_pinmux_enable,
+ .disable = adi_pinmux_disable,
+ .get_functions_count = adi_pinmux_get_funcs_count,
+ .get_function_name = adi_pinmux_get_func_name,
+ .get_function_groups = adi_pinmux_get_groups,
+ .gpio_request_enable = adi_pinmux_request_gpio,
+};
+
+
+static struct pinctrl_desc adi_pinmux_desc = {
+ .name = DRIVER_NAME,
+ .pctlops = &adi_pctrl_ops,
+ .pmxops = &adi_pinmux_ops,
+ .owner = THIS_MODULE,
+};
+
+static int adi_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+ return pinctrl_request_gpio(chip->base + offset);
+}
+
+static void adi_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+ pinctrl_free_gpio(chip->base + offset);
+}
+
+static int adi_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+ struct gpio_port *port;
+ unsigned long flags;
+
+ port = container_of(chip, struct gpio_port, chip);
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ writew(BIT(offset), &port->regs->dir_clear);
+ writew(readw(&port->regs->inen) | BIT(offset), &port->regs->inen);
+
+ spin_unlock_irqrestore(&port->lock, flags);
+
+ return 0;
+}
+
+static void adi_gpio_set_value(struct gpio_chip *chip, unsigned offset,
+ int value)
+{
+ struct gpio_port *port = container_of(chip, struct gpio_port, chip);
+ struct gpio_port_t *regs = port->regs;
+ unsigned long flags;
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ if (value)
+ writew(BIT(offset), ®s->data_set);
+ else
+ writew(BIT(offset), ®s->data_clear);
+
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static int adi_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+ int value)
+{
+ struct gpio_port *port = container_of(chip, struct gpio_port, chip);
+ struct gpio_port_t *regs = port->regs;
+ unsigned long flags;
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ writew(readw(®s->inen) & ~BIT(offset), ®s->inen);
+ if (value)
+ writew(BIT(offset), ®s->data_set);
+ else
+ writew(BIT(offset), ®s->data_clear);
+ writew(BIT(offset), ®s->dir_set);
+
+ spin_unlock_irqrestore(&port->lock, flags);
+
+ return 0;
+}
+
+static int adi_gpio_get_value(struct gpio_chip *chip, unsigned offset)
+{
+ struct gpio_port *port = container_of(chip, struct gpio_port, chip);
+ struct gpio_port_t *regs = port->regs;
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ ret = !!(readw(®s->data) & BIT(offset));
+
+ spin_unlock_irqrestore(&port->lock, flags);
+
+ return ret;
+}
+
+static int adi_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ struct gpio_port *port = container_of(chip, struct gpio_port, chip);
+
+ if (port->irq_base >= 0)
+ return irq_find_mapping(port->domain, offset);
+ else
+ return irq_create_mapping(port->domain, offset);
+}
+
+static int adi_pint_map_port(struct gpio_pint *pint, bool assign, u8 map,
+ struct irq_domain *domain)
+{
+ struct gpio_pint_regs *regs = pint->regs;
+ u32 map_mask;
+
+ if (pint->map_count > 1)
+ return -EINVAL;
+
+ pint->map_count++;
+
+ /* The map_mask of each gpio port is a 16-bit duplicate
+ * of the 8-bit map. It can be set to either high 16 bits or low
+ * 16 bits of the pint assignment register.
+ */
+ map_mask = (map << 8) | map;
+ if (assign) {
+ map_mask <<= PINT_HI_OFFSET;
+ writel((readl(®s->assign) & 0xFFFF) | map_mask,
+ ®s->assign);
+ } else
+ writel((readl(®s->assign) & 0xFFFF0000) | map_mask,
+ ®s->assign);
+
+ pint->domain[assign] = domain;
+
+ return 0;
+}
+
+static int adi_gpio_pint_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct gpio_pint *pint;
+
+ pint = devm_kzalloc(dev, sizeof(struct gpio_pint), GFP_KERNEL);
+ if (!pint) {
+ dev_err(dev, "Memory alloc failed\n");
+ return -ENOMEM;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ pint->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(pint->base))
+ return PTR_ERR(pint->base);
+
+ pint->regs = (struct gpio_pint_regs *)pint->base;
+
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (!res) {
+ dev_err(dev, "Invalid IRQ resource\n");
+ return -ENODEV;
+ }
+
+ spin_lock_init(&pint->lock);
+
+ pint->irq = res->start;
+ pint->pint_map_port = adi_pint_map_port;
+ platform_set_drvdata(pdev, pint);
+
+ irq_set_chained_handler(pint->irq, adi_gpio_handle_pint_irq);
+ irq_set_handler_data(pint->irq, pint);
+
+ list_add_tail(&pint->node, &adi_pint_list);
+
+ return 0;
+}
+
+static int adi_gpio_pint_remove(struct platform_device *pdev)
+{
+ struct gpio_pint *pint = platform_get_drvdata(pdev);
+
+ list_del(&pint->node);
+ irq_set_handler(pint->irq, handle_simple_irq);
+
+ return 0;
+}
+
+static int adi_gpio_irq_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hwirq)
+{
+ struct gpio_port *port = d->host_data;
+
+ if (!port)
+ return -EINVAL;
+
+ irq_set_chip_data(irq, port);
+ irq_set_chip_and_handler(irq, &adi_gpio_irqchip,
+ handle_level_irq);
+
+ return 0;
+}
+
+const struct irq_domain_ops adi_gpio_irq_domain_ops = {
+ .map = adi_gpio_irq_map,
+ .xlate = irq_domain_xlate_onecell,
+};
+
+static int adi_gpio_init_int(struct gpio_port *port)
+{
+ struct device_node *node = port->dev->of_node;
+ struct gpio_pint *pint = port->pint;
+ int ret;
+
+ port->domain = irq_domain_add_linear(node, port->width,
+ &adi_gpio_irq_domain_ops, port);
+ if (!port->domain) {
+ dev_err(port->dev, "Failed to create irqdomain\n");
+ return -ENOSYS;
+ }
+
+ /* According to BF54x and BF60x HRM, pin interrupt devices are not
+ * part of the GPIO port device. in GPIO interrupt mode, the GPIO
+ * pins of multiple port devices can be routed into one pin interrupt
+ * device. The mapping can be configured by setting pint assignment
+ * register with the mapping value of different GPIO port. This is
+ * done via function pint_map_port().
+ */
+ ret = pint->pint_map_port(port->pint, port->pint_assign,
+ port->pint_map, port->domain);
+ if (ret)
+ return ret;
+
+ if (port->irq_base >= 0) {
+ ret = irq_create_strict_mappings(port->domain, port->irq_base,
+ 0, port->width);
+ if (ret) {
+ dev_err(port->dev, "Couldn't associate to domain\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+#define DEVNAME_SIZE 16
+
+static int adi_gpio_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct adi_pinctrl_gpio_platform_data *pdata;
+ struct resource *res;
+ struct gpio_port *port;
+ char pinctrl_devname[DEVNAME_SIZE];
+ static int gpio;
+ int ret = 0, ret1;
+
+ pdata = dev->platform_data;
+ if (!pdata)
+ return -EINVAL;
+
+ port = devm_kzalloc(dev, sizeof(struct gpio_port), GFP_KERNEL);
+ if (!port) {
+ dev_err(dev, "Memory alloc failed\n");
+ return -ENOMEM;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ port->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(port->base))
+ return PTR_ERR(port->base);
+
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (!res)
+ port->irq_base = -1;
+ else
+ port->irq_base = res->start;
+
+ port->width = pdata->port_width;
+ port->dev = dev;
+ port->regs = (struct gpio_port_t *)port->base;
+ port->pint_assign = pdata->pint_assign;
+ port->pint_map = pdata->pint_map;
+
+ port->pint = find_gpio_pint(pdata->pint_id);
+ if (port->pint) {
+ ret = adi_gpio_init_int(port);
+ if (ret)
+ return ret;
+ }
+
+ spin_lock_init(&port->lock);
+
+ platform_set_drvdata(pdev, port);
+
+ port->chip.label = "adi-gpio";
+ port->chip.direction_input = adi_gpio_direction_input;
+ port->chip.get = adi_gpio_get_value;
+ port->chip.direction_output = adi_gpio_direction_output;
+ port->chip.set = adi_gpio_set_value;
+ port->chip.request = adi_gpio_request;
+ port->chip.free = adi_gpio_free;
+ port->chip.to_irq = adi_gpio_to_irq;
+ if (pdata->port_gpio_base > 0)
+ port->chip.base = pdata->port_gpio_base;
+ else
+ port->chip.base = gpio;
+ port->chip.ngpio = port->width;
+ gpio = port->chip.base + port->width;
+
+ ret = gpiochip_add(&port->chip);
+ if (ret) {
+ dev_err(&pdev->dev, "Fail to add GPIO chip.\n");
+ goto out_remove_domain;
+ }
+
+ /* Add gpio pin range */
+ snprintf(pinctrl_devname, DEVNAME_SIZE, "pinctrl-adi2.%d",
+ pdata->pinctrl_id);
+ pinctrl_devname[DEVNAME_SIZE - 1] = 0;
+ ret = gpiochip_add_pin_range(&port->chip, pinctrl_devname,
+ 0, pdata->port_pin_base, port->width);
+ if (ret) {
+ dev_err(&pdev->dev, "Fail to add pin range to %s.\n",
+ pinctrl_devname);
+ goto out_remove_gpiochip;
+ }
+
+ list_add_tail(&port->node, &adi_gpio_port_list);
+
+ return 0;
+
+out_remove_gpiochip:
+ ret1 = gpiochip_remove(&port->chip);
+out_remove_domain:
+ if (port->pint)
+ irq_domain_remove(port->domain);
+
+ return ret;
+}
+
+static int adi_gpio_remove(struct platform_device *pdev)
+{
+ struct gpio_port *port = platform_get_drvdata(pdev);
+ int ret;
+ u8 offset;
+
+ list_del(&port->node);
+ gpiochip_remove_pin_ranges(&port->chip);
+ ret = gpiochip_remove(&port->chip);
+ if (port->pint) {
+ for (offset = 0; offset < port->width; offset++)
+ irq_dispose_mapping(irq_find_mapping(port->domain,
+ offset));
+ irq_domain_remove(port->domain);
+ }
+
+ return ret;
+}
+
+static int adi_pinctrl_probe(struct platform_device *pdev)
+{
+ struct adi_pinctrl *pinctrl;
+
+ pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
+ if (!pinctrl)
+ return -ENOMEM;
+
+ pinctrl->dev = &pdev->dev;
+
+ adi_pinctrl_soc_init(&pinctrl->soc);
+
+ adi_pinmux_desc.pins = pinctrl->soc->pins;
+ adi_pinmux_desc.npins = pinctrl->soc->npins;
+
+ /* Now register the pin controller and all pins it handles */
+ pinctrl->pctl = pinctrl_register(&adi_pinmux_desc, &pdev->dev, pinctrl);
+ if (!pinctrl->pctl) {
+ dev_err(&pdev->dev, "could not register pinctrl ADI2 driver\n");
+ return -EINVAL;
+ }
+
+ platform_set_drvdata(pdev, pinctrl);
+
+ return 0;
+}
+
+static int adi_pinctrl_remove(struct platform_device *pdev)
+{
+ struct adi_pinctrl *pinctrl = platform_get_drvdata(pdev);
+
+ pinctrl_unregister(pinctrl->pctl);
+
+ return 0;
+}
+
+static struct platform_driver adi_pinctrl_driver = {
+ .probe = adi_pinctrl_probe,
+ .remove = adi_pinctrl_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ },
+};
+
+static struct platform_driver adi_gpio_pint_driver = {
+ .probe = adi_gpio_pint_probe,
+ .remove = adi_gpio_pint_remove,
+ .driver = {
+ .name = "adi-gpio-pint",
+ },
+};
+
+static struct platform_driver adi_gpio_driver = {
+ .probe = adi_gpio_probe,
+ .remove = adi_gpio_remove,
+ .driver = {
+ .name = "adi-gpio",
+ },
+};
+
+static int __init adi_pinctrl_setup(void)
+{
+ int ret;
+
+ ret = platform_driver_register(&adi_pinctrl_driver);
+ if (ret)
+ return ret;
+
+ ret = platform_driver_register(&adi_gpio_pint_driver);
+ if (ret)
+ goto pint_error;
+
+ ret = platform_driver_register(&adi_gpio_driver);
+ if (ret)
+ goto gpio_error;
+
+#ifdef CONFIG_PM
+ register_syscore_ops(&gpio_pm_syscore_ops);
+#endif
+ return ret;
+gpio_error:
+ platform_driver_unregister(&adi_gpio_pint_driver);
+pint_error:
+ platform_driver_unregister(&adi_pinctrl_driver);
+
+ return ret;
+}
+arch_initcall(adi_pinctrl_setup);
+
+MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
+MODULE_DESCRIPTION("ADI gpio2 pin control driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * Pinctrl Driver for ADI GPIO2 controller
+ *
+ * Copyright 2007-2013 Analog Devices Inc.
+ *
+ * Licensed under the GPLv2 or later
+ */
+
+#ifndef PINCTRL_PINCTRL_ADI2_H
+#define PINCTRL_PINCTRL_ADI2_H
+
+#include <linux/pinctrl/pinctrl.h>
+
+ /**
+ * struct adi_pin_group - describes a pin group
+ * @name: the name of this pin group
+ * @pins: an array of pins
+ * @num: the number of pins in this array
+ */
+struct adi_pin_group {
+ const char *name;
+ const unsigned *pins;
+ const unsigned num;
+};
+
+#define ADI_PIN_GROUP(n, p) \
+ { \
+ .name = n, \
+ .pins = p, \
+ .num = ARRAY_SIZE(p), \
+ }
+
+ /**
+ * struct adi_pmx_func - describes function mux setting of pin groups
+ * @name: the name of this function mux setting
+ * @groups: an array of pin groups
+ * @num_groups: the number of pin groups in this array
+ * @mux: the function mux setting array, end by zero
+ */
+struct adi_pmx_func {
+ const char *name;
+ const char * const *groups;
+ const unsigned num_groups;
+ const unsigned short *mux;
+};
+
+#define ADI_PMX_FUNCTION(n, g, m) \
+ { \
+ .name = n, \
+ .groups = g, \
+ .num_groups = ARRAY_SIZE(g), \
+ .mux = m, \
+ }
+
+/**
+ * struct adi_pinctrl_soc_data - ADI pin controller per-SoC configuration
+ * @functions: The functions supported on this SoC.
+ * @nfunction: The number of entries in @functions.
+ * @groups: An array describing all pin groups the pin SoC supports.
+ * @ngroups: The number of entries in @groups.
+ * @pins: An array describing all pins the pin controller affects.
+ * @npins: The number of entries in @pins.
+ */
+struct adi_pinctrl_soc_data {
+ const struct adi_pmx_func *functions;
+ int nfunctions;
+ const struct adi_pin_group *groups;
+ int ngroups;
+ const struct pinctrl_pin_desc *pins;
+ int npins;
+};
+
+void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc);
+
+#endif /* PINCTRL_PINCTRL_ADI2_H */
--- /dev/null
+/*
+ * ams AS3722 pin control and GPIO driver.
+ *
+ * Copyright (c) 2013, NVIDIA Corporation.
+ *
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mfd/as3722.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pm.h>
+#include <linux/slab.h>
+
+#include "core.h"
+#include "pinconf.h"
+#include "pinctrl-utils.h"
+
+#define AS3722_PIN_GPIO0 0
+#define AS3722_PIN_GPIO1 1
+#define AS3722_PIN_GPIO2 2
+#define AS3722_PIN_GPIO3 3
+#define AS3722_PIN_GPIO4 4
+#define AS3722_PIN_GPIO5 5
+#define AS3722_PIN_GPIO6 6
+#define AS3722_PIN_GPIO7 7
+#define AS3722_PIN_NUM (AS3722_PIN_GPIO7 + 1)
+
+#define AS3722_GPIO_MODE_PULL_UP BIT(PIN_CONFIG_BIAS_PULL_UP)
+#define AS3722_GPIO_MODE_PULL_DOWN BIT(PIN_CONFIG_BIAS_PULL_DOWN)
+#define AS3722_GPIO_MODE_HIGH_IMPED BIT(PIN_CONFIG_BIAS_HIGH_IMPEDANCE)
+#define AS3722_GPIO_MODE_OPEN_DRAIN BIT(PIN_CONFIG_DRIVE_OPEN_DRAIN)
+
+struct as3722_pin_function {
+ const char *name;
+ const char * const *groups;
+ unsigned ngroups;
+ int mux_option;
+};
+
+struct as3722_gpio_pin_control {
+ bool enable_gpio_invert;
+ unsigned mode_prop;
+ int io_function;
+};
+
+struct as3722_pingroup {
+ const char *name;
+ const unsigned pins[1];
+ unsigned npins;
+};
+
+struct as3722_pctrl_info {
+ struct device *dev;
+ struct pinctrl_dev *pctl;
+ struct as3722 *as3722;
+ struct gpio_chip gpio_chip;
+ int pins_current_opt[AS3722_PIN_NUM];
+ const struct as3722_pin_function *functions;
+ unsigned num_functions;
+ const struct as3722_pingroup *pin_groups;
+ int num_pin_groups;
+ const struct pinctrl_pin_desc *pins;
+ unsigned num_pins;
+ struct as3722_gpio_pin_control gpio_control[AS3722_PIN_NUM];
+};
+
+static const struct pinctrl_pin_desc as3722_pins_desc[] = {
+ PINCTRL_PIN(AS3722_PIN_GPIO0, "gpio0"),
+ PINCTRL_PIN(AS3722_PIN_GPIO1, "gpio1"),
+ PINCTRL_PIN(AS3722_PIN_GPIO2, "gpio2"),
+ PINCTRL_PIN(AS3722_PIN_GPIO3, "gpio3"),
+ PINCTRL_PIN(AS3722_PIN_GPIO4, "gpio4"),
+ PINCTRL_PIN(AS3722_PIN_GPIO5, "gpio5"),
+ PINCTRL_PIN(AS3722_PIN_GPIO6, "gpio6"),
+ PINCTRL_PIN(AS3722_PIN_GPIO7, "gpio7"),
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0",
+ "gpio1",
+ "gpio2",
+ "gpio3",
+ "gpio4",
+ "gpio5",
+ "gpio6",
+ "gpio7",
+};
+
+enum as3722_pinmux_option {
+ AS3722_PINMUX_GPIO = 0,
+ AS3722_PINMUX_INTERRUPT_OUT = 1,
+ AS3722_PINMUX_VSUB_VBAT_UNDEB_LOW_OUT = 2,
+ AS3722_PINMUX_GPIO_INTERRUPT = 3,
+ AS3722_PINMUX_PWM_INPUT = 4,
+ AS3722_PINMUX_VOLTAGE_IN_STBY = 5,
+ AS3722_PINMUX_OC_PG_SD0 = 6,
+ AS3722_PINMUX_PG_OUT = 7,
+ AS3722_PINMUX_CLK32K_OUT = 8,
+ AS3722_PINMUX_WATCHDOG_INPUT = 9,
+ AS3722_PINMUX_SOFT_RESET_IN = 11,
+ AS3722_PINMUX_PWM_OUTPUT = 12,
+ AS3722_PINMUX_VSUB_VBAT_LOW_DEB_OUT = 13,
+ AS3722_PINMUX_OC_PG_SD6 = 14,
+};
+
+#define FUNCTION_GROUP(fname, mux) \
+ { \
+ .name = #fname, \
+ .groups = gpio_groups, \
+ .ngroups = ARRAY_SIZE(gpio_groups), \
+ .mux_option = AS3722_PINMUX_##mux, \
+ }
+
+static const struct as3722_pin_function as3722_pin_function[] = {
+ FUNCTION_GROUP(gpio, GPIO),
+ FUNCTION_GROUP(interrupt-out, INTERRUPT_OUT),
+ FUNCTION_GROUP(gpio-in-interrupt, GPIO_INTERRUPT),
+ FUNCTION_GROUP(vsup-vbat-low-undebounce-out, VSUB_VBAT_UNDEB_LOW_OUT),
+ FUNCTION_GROUP(vsup-vbat-low-debounce-out, VSUB_VBAT_LOW_DEB_OUT),
+ FUNCTION_GROUP(voltage-in-standby, VOLTAGE_IN_STBY),
+ FUNCTION_GROUP(oc-pg-sd0, OC_PG_SD0),
+ FUNCTION_GROUP(oc-pg-sd6, OC_PG_SD6),
+ FUNCTION_GROUP(powergood-out, PG_OUT),
+ FUNCTION_GROUP(pwm-in, PWM_INPUT),
+ FUNCTION_GROUP(pwm-out, PWM_OUTPUT),
+ FUNCTION_GROUP(clk32k-out, CLK32K_OUT),
+ FUNCTION_GROUP(watchdog-in, WATCHDOG_INPUT),
+ FUNCTION_GROUP(soft-reset-in, SOFT_RESET_IN),
+};
+
+#define AS3722_PINGROUP(pg_name, pin_id) \
+ { \
+ .name = #pg_name, \
+ .pins = {AS3722_PIN_##pin_id}, \
+ .npins = 1, \
+ }
+
+static const struct as3722_pingroup as3722_pingroups[] = {
+ AS3722_PINGROUP(gpio0, GPIO0),
+ AS3722_PINGROUP(gpio1, GPIO1),
+ AS3722_PINGROUP(gpio2, GPIO2),
+ AS3722_PINGROUP(gpio3, GPIO3),
+ AS3722_PINGROUP(gpio4, GPIO4),
+ AS3722_PINGROUP(gpio5, GPIO5),
+ AS3722_PINGROUP(gpio6, GPIO6),
+ AS3722_PINGROUP(gpio7, GPIO7),
+};
+
+static int as3722_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
+
+ return as_pci->num_pin_groups;
+}
+
+static const char *as3722_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned group)
+{
+ struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
+
+ return as_pci->pin_groups[group].name;
+}
+
+static int as3722_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned group, const unsigned **pins, unsigned *num_pins)
+{
+ struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = as_pci->pin_groups[group].pins;
+ *num_pins = as_pci->pin_groups[group].npins;
+ return 0;
+}
+
+static const struct pinctrl_ops as3722_pinctrl_ops = {
+ .get_groups_count = as3722_pinctrl_get_groups_count,
+ .get_group_name = as3722_pinctrl_get_group_name,
+ .get_group_pins = as3722_pinctrl_get_group_pins,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
+ .dt_free_map = pinctrl_utils_dt_free_map,
+};
+
+static int as3722_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+ struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
+
+ return as_pci->num_functions;
+}
+
+static const char *as3722_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned function)
+{
+ struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
+
+ return as_pci->functions[function].name;
+}
+
+static int as3722_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
+ unsigned function, const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = as_pci->functions[function].groups;
+ *num_groups = as_pci->functions[function].ngroups;
+ return 0;
+}
+
+static int as3722_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
+ unsigned group)
+{
+ struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
+ int gpio_cntr_reg = AS3722_GPIOn_CONTROL_REG(group);
+ u8 val = AS3722_GPIO_IOSF_VAL(as_pci->functions[function].mux_option);
+ int ret;
+
+ dev_dbg(as_pci->dev, "%s(): GPIO %u pin to function %u and val %u\n",
+ __func__, group, function, val);
+
+ ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg,
+ AS3722_GPIO_IOSF_MASK, val);
+ if (ret < 0) {
+ dev_err(as_pci->dev, "GPIO%d_CTRL_REG update failed %d\n",
+ group, ret);
+ return ret;
+ }
+ as_pci->gpio_control[group].io_function = function;
+ return ret;
+}
+
+static int as3722_pinctrl_gpio_get_mode(unsigned gpio_mode_prop, bool input)
+{
+ if (gpio_mode_prop & AS3722_GPIO_MODE_HIGH_IMPED)
+ return -EINVAL;
+
+ if (gpio_mode_prop & AS3722_GPIO_MODE_OPEN_DRAIN) {
+ if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP)
+ return AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP;
+ return AS3722_GPIO_MODE_IO_OPEN_DRAIN;
+ }
+ if (input) {
+ if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP)
+ return AS3722_GPIO_MODE_INPUT_PULL_UP;
+ else if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN)
+ return AS3722_GPIO_MODE_INPUT_PULL_DOWN;
+ return AS3722_GPIO_MODE_INPUT;
+ }
+ if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN)
+ return AS3722_GPIO_MODE_OUTPUT_VDDL;
+ return AS3722_GPIO_MODE_OUTPUT_VDDH;
+}
+
+static int as3722_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range, unsigned offset)
+{
+ struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
+
+ if (as_pci->gpio_control[offset].io_function)
+ return -EBUSY;
+ return 0;
+}
+
+static int as3722_pinctrl_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range, unsigned offset, bool input)
+{
+ struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
+ struct as3722 *as3722 = as_pci->as3722;
+ int mode;
+
+ mode = as3722_pinctrl_gpio_get_mode(
+ as_pci->gpio_control[offset].mode_prop, input);
+ if (mode < 0) {
+ dev_err(as_pci->dev, "%s direction for GPIO %d not supported\n",
+ (input) ? "Input" : "Output", offset);
+ return mode;
+ }
+
+ if (as_pci->gpio_control[offset].enable_gpio_invert)
+ mode |= AS3722_GPIO_INV;
+
+ return as3722_write(as3722, AS3722_GPIOn_CONTROL_REG(offset), mode);
+}
+
+static const struct pinmux_ops as3722_pinmux_ops = {
+ .get_functions_count = as3722_pinctrl_get_funcs_count,
+ .get_function_name = as3722_pinctrl_get_func_name,
+ .get_function_groups = as3722_pinctrl_get_func_groups,
+ .enable = as3722_pinctrl_enable,
+ .gpio_request_enable = as3722_pinctrl_gpio_request_enable,
+ .gpio_set_direction = as3722_pinctrl_gpio_set_direction,
+};
+
+static int as3722_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned pin, unsigned long *config)
+{
+ struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param param = pinconf_to_config_param(*config);
+ int arg = 0;
+ u16 prop;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ prop = AS3722_GPIO_MODE_PULL_UP |
+ AS3722_GPIO_MODE_PULL_DOWN;
+ if (!(as_pci->gpio_control[pin].mode_prop & prop))
+ arg = 1;
+ prop = 0;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ prop = AS3722_GPIO_MODE_PULL_UP;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ prop = AS3722_GPIO_MODE_PULL_DOWN;
+ break;
+
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ prop = AS3722_GPIO_MODE_OPEN_DRAIN;
+ break;
+
+ case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
+ prop = AS3722_GPIO_MODE_HIGH_IMPED;
+ break;
+
+ default:
+ dev_err(as_pci->dev, "Properties not supported\n");
+ return -ENOTSUPP;
+ }
+
+ if (as_pci->gpio_control[pin].mode_prop & prop)
+ arg = 1;
+
+ *config = pinconf_to_config_packed(param, (u16)arg);
+ return 0;
+}
+
+static int as3722_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned pin, unsigned long *configs,
+ unsigned num_configs)
+{
+ struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param param;
+ int mode_prop;
+ int i;
+
+ for (i = 0; i < num_configs; i++) {
+ param = pinconf_to_config_param(configs[i]);
+ mode_prop = as_pci->gpio_control[pin].mode_prop;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
+ break;
+
+ case PIN_CONFIG_BIAS_DISABLE:
+ mode_prop &= ~(AS3722_GPIO_MODE_PULL_UP |
+ AS3722_GPIO_MODE_PULL_DOWN);
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ mode_prop |= AS3722_GPIO_MODE_PULL_UP;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ mode_prop |= AS3722_GPIO_MODE_PULL_DOWN;
+ break;
+
+ case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
+ mode_prop |= AS3722_GPIO_MODE_HIGH_IMPED;
+ break;
+
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ mode_prop |= AS3722_GPIO_MODE_OPEN_DRAIN;
+ break;
+
+ default:
+ dev_err(as_pci->dev, "Properties not supported\n");
+ return -ENOTSUPP;
+ }
+
+ as_pci->gpio_control[pin].mode_prop = mode_prop;
+ }
+ return 0;
+}
+
+static const struct pinconf_ops as3722_pinconf_ops = {
+ .pin_config_get = as3722_pinconf_get,
+ .pin_config_set = as3722_pinconf_set,
+};
+
+static struct pinctrl_desc as3722_pinctrl_desc = {
+ .pctlops = &as3722_pinctrl_ops,
+ .pmxops = &as3722_pinmux_ops,
+ .confops = &as3722_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+static inline struct as3722_pctrl_info *to_as_pci(struct gpio_chip *chip)
+{
+ return container_of(chip, struct as3722_pctrl_info, gpio_chip);
+}
+
+static int as3722_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct as3722_pctrl_info *as_pci = to_as_pci(chip);
+ struct as3722 *as3722 = as_pci->as3722;
+ int ret;
+ u32 reg;
+ u32 control;
+ u32 val;
+ int mode;
+ int invert_enable;
+
+ ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &control);
+ if (ret < 0) {
+ dev_err(as_pci->dev,
+ "GPIO_CONTROL%d_REG read failed: %d\n", offset, ret);
+ return ret;
+ }
+
+ invert_enable = !!(control & AS3722_GPIO_INV);
+ mode = control & AS3722_GPIO_MODE_MASK;
+ switch (mode) {
+ case AS3722_GPIO_MODE_INPUT:
+ case AS3722_GPIO_MODE_INPUT_PULL_UP:
+ case AS3722_GPIO_MODE_INPUT_PULL_DOWN:
+ case AS3722_GPIO_MODE_IO_OPEN_DRAIN:
+ case AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP:
+ reg = AS3722_GPIO_SIGNAL_IN_REG;
+ break;
+ case AS3722_GPIO_MODE_OUTPUT_VDDH:
+ case AS3722_GPIO_MODE_OUTPUT_VDDL:
+ reg = AS3722_GPIO_SIGNAL_OUT_REG;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ ret = as3722_read(as3722, reg, &val);
+ if (ret < 0) {
+ dev_err(as_pci->dev,
+ "GPIO_SIGNAL_IN_REG read failed: %d\n", ret);
+ return ret;
+ }
+
+ val = !!(val & AS3722_GPIOn_SIGNAL(offset));
+ return (invert_enable) ? !val : val;
+}
+
+static void as3722_gpio_set(struct gpio_chip *chip, unsigned offset,
+ int value)
+{
+ struct as3722_pctrl_info *as_pci = to_as_pci(chip);
+ struct as3722 *as3722 = as_pci->as3722;
+ int en_invert = as_pci->gpio_control[offset].enable_gpio_invert;
+ u32 val;
+ int ret;
+
+ if (value)
+ val = (en_invert) ? 0 : AS3722_GPIOn_SIGNAL(offset);
+ else
+ val = (en_invert) ? AS3722_GPIOn_SIGNAL(offset) : 0;
+
+ ret = as3722_update_bits(as3722, AS3722_GPIO_SIGNAL_OUT_REG,
+ AS3722_GPIOn_SIGNAL(offset), val);
+ if (ret < 0)
+ dev_err(as_pci->dev,
+ "GPIO_SIGNAL_OUT_REG update failed: %d\n", ret);
+}
+
+static int as3722_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+ return pinctrl_gpio_direction_input(chip->base + offset);
+}
+
+static int as3722_gpio_direction_output(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ as3722_gpio_set(chip, offset, value);
+ return pinctrl_gpio_direction_output(chip->base + offset);
+}
+
+static int as3722_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ struct as3722_pctrl_info *as_pci = to_as_pci(chip);
+
+ return as3722_irq_get_virq(as_pci->as3722, offset);
+}
+
+static int as3722_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+ return pinctrl_request_gpio(chip->base + offset);
+}
+
+static void as3722_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+ pinctrl_free_gpio(chip->base + offset);
+}
+
+static const struct gpio_chip as3722_gpio_chip = {
+ .label = "as3722-gpio",
+ .owner = THIS_MODULE,
+ .request = as3722_gpio_request,
+ .free = as3722_gpio_free,
+ .get = as3722_gpio_get,
+ .set = as3722_gpio_set,
+ .direction_input = as3722_gpio_direction_input,
+ .direction_output = as3722_gpio_direction_output,
+ .to_irq = as3722_gpio_to_irq,
+ .can_sleep = 1,
+ .ngpio = AS3722_PIN_NUM,
+ .base = -1,
+};
+
+static int as3722_pinctrl_probe(struct platform_device *pdev)
+{
+ struct as3722_pctrl_info *as_pci;
+ int ret;
+ int tret;
+
+ as_pci = devm_kzalloc(&pdev->dev, sizeof(*as_pci), GFP_KERNEL);
+ if (!as_pci)
+ return -ENOMEM;
+
+ as_pci->dev = &pdev->dev;
+ as_pci->dev->of_node = pdev->dev.parent->of_node;
+ as_pci->as3722 = dev_get_drvdata(pdev->dev.parent);
+ platform_set_drvdata(pdev, as_pci);
+
+ as_pci->pins = as3722_pins_desc;
+ as_pci->num_pins = ARRAY_SIZE(as3722_pins_desc);
+ as_pci->functions = as3722_pin_function;
+ as_pci->num_functions = ARRAY_SIZE(as3722_pin_function);
+ as_pci->pin_groups = as3722_pingroups;
+ as_pci->num_pin_groups = ARRAY_SIZE(as3722_pingroups);
+ as3722_pinctrl_desc.name = dev_name(&pdev->dev);
+ as3722_pinctrl_desc.pins = as3722_pins_desc;
+ as3722_pinctrl_desc.npins = ARRAY_SIZE(as3722_pins_desc);
+ as_pci->pctl = pinctrl_register(&as3722_pinctrl_desc,
+ &pdev->dev, as_pci);
+ if (!as_pci->pctl) {
+ dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
+ return -EINVAL;
+ }
+
+ as_pci->gpio_chip = as3722_gpio_chip;
+ as_pci->gpio_chip.dev = &pdev->dev;
+ as_pci->gpio_chip.of_node = pdev->dev.parent->of_node;
+ ret = gpiochip_add(&as_pci->gpio_chip);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Couldn't register gpiochip, %d\n", ret);
+ goto fail_chip_add;
+ }
+
+ ret = gpiochip_add_pin_range(&as_pci->gpio_chip, dev_name(&pdev->dev),
+ 0, 0, AS3722_PIN_NUM);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Couldn't add pin range, %d\n", ret);
+ goto fail_range_add;
+ }
+
+ return 0;
+
+fail_range_add:
+ tret = gpiochip_remove(&as_pci->gpio_chip);
+ if (tret < 0)
+ dev_warn(&pdev->dev, "Couldn't remove gpio chip, %d\n", tret);
+
+fail_chip_add:
+ pinctrl_unregister(as_pci->pctl);
+ return ret;
+}
+
+static int as3722_pinctrl_remove(struct platform_device *pdev)
+{
+ struct as3722_pctrl_info *as_pci = platform_get_drvdata(pdev);
+ int ret;
+
+ ret = gpiochip_remove(&as_pci->gpio_chip);
+ if (ret < 0)
+ return ret;
+ pinctrl_unregister(as_pci->pctl);
+ return 0;
+}
+
+static struct of_device_id as3722_pinctrl_of_match[] = {
+ { .compatible = "ams,as3722-pinctrl", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, as3722_pinctrl_of_match);
+
+static struct platform_driver as3722_pinctrl_driver = {
+ .driver = {
+ .name = "as3722-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = as3722_pinctrl_of_match,
+ },
+ .probe = as3722_pinctrl_probe,
+ .remove = as3722_pinctrl_remove,
+};
+module_platform_driver(as3722_pinctrl_driver);
+
+MODULE_ALIAS("platform:as3722-pinctrl");
+MODULE_DESCRIPTION("AS3722 pin control and GPIO driver");
+MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
+MODULE_LICENSE("GPL v2");
#include "core.h"
+#define MAX_GPIO_BANKS 5
#define MAX_NB_GPIO_PER_BANK 32
struct at91_pinctrl_mux_ops;
void (*mux_C_periph)(void __iomem *pio, unsigned mask);
void (*mux_D_periph)(void __iomem *pio, unsigned mask);
bool (*get_deglitch)(void __iomem *pio, unsigned pin);
- void (*set_deglitch)(void __iomem *pio, unsigned mask, bool in_on);
+ void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
- void (*set_debounce)(void __iomem *pio, unsigned mask, bool in_on, u32 div);
+ void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
bool (*get_pulldown)(void __iomem *pio, unsigned pin);
- void (*set_pulldown)(void __iomem *pio, unsigned mask, bool in_on);
+ void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
/* irq */
int i;
/*
- * first find the group of this node and check if we need create
+ * first find the group of this node and check if we need to create
* config maps for pins
*/
grp = at91_pinctrl_find_group_by_name(info, np->name);
__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
}
+static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
+{
+ if ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1)
+ return !((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
+
+ return false;
+}
+
static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
{
if (is_on)
{
*div = __raw_readl(pio + PIO_SCDR);
- return (__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1;
+ return ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) &&
+ ((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
}
static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
__raw_writel(mask, pio + PIO_IFSCER);
__raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
__raw_writel(mask, pio + PIO_IFER);
- } else {
- __raw_writel(mask, pio + PIO_IFDR);
- }
+ } else
+ __raw_writel(mask, pio + PIO_IFSCDR);
}
static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
.mux_B_periph = at91_mux_pio3_set_B_periph,
.mux_C_periph = at91_mux_pio3_set_C_periph,
.mux_D_periph = at91_mux_pio3_set_D_periph,
- .get_deglitch = at91_mux_get_deglitch,
+ .get_deglitch = at91_mux_pio3_get_deglitch,
.set_deglitch = at91_mux_pio3_set_deglitch,
.get_debounce = at91_mux_pio3_get_debounce,
.set_debounce = at91_mux_pio3_set_debounce,
info->functions[selector].name, info->groups[group].name);
/* first check that all the pins of the group are valid with a valid
- * paramter */
+ * parameter */
for (i = 0; i < npins; i++) {
pin = &pins_conf[i];
ret = pin_check_config(info, info->groups[group].name, i, pin);
at91_pinctrl_child_count(info, np);
if (info->nbanks < 1) {
- dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n");
+ dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
return -EINVAL;
}
if (at91_gpio->pioc_idx)
prev = gpio_chips[at91_gpio->pioc_idx - 1];
- /* The toplevel handler handles one bank of GPIOs, except
+ /* The top level handler handles one bank of GPIOs, except
* on some SoC it can handles up to three...
* We only set up the handler for the first of the list.
*/
.driver = {
.name = "gpio-at91",
.owner = THIS_MODULE,
- .of_match_table = of_match_ptr(at91_gpio_of_match),
+ .of_match_table = at91_gpio_of_match,
},
.probe = at91_gpio_probe,
};
.driver = {
.name = "pinctrl-at91",
.owner = THIS_MODULE,
- .of_match_table = of_match_ptr(at91_pinctrl_of_match),
+ .of_match_table = at91_pinctrl_of_match,
},
.probe = at91_pinctrl_probe,
.remove = at91_pinctrl_remove,
.driver = {
.name = "exynos5440-pinctrl",
.owner = THIS_MODULE,
- .of_match_table = of_match_ptr(exynos5440_pinctrl_dt_match),
+ .of_match_table = exynos5440_pinctrl_dt_match,
},
};
* The input_reg[i] here is actually some IOMUXC general
* purpose register, not regular select input register.
*/
- val = readl(ipctl->base + pin->input_val);
+ val = readl(ipctl->base + pin->input_reg);
val &= ~mask;
val |= select << shift;
- writel(val, ipctl->base + pin->input_val);
- } else if (pin->input_val) {
+ writel(val, ipctl->base + pin->input_reg);
+ } else if (pin->input_reg) {
/*
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
--- /dev/null
+/*
+ * Core driver for the imx pin controller in imx1/21/27
+ *
+ * Copyright (C) 2013 Pengutronix
+ * Author: Markus Pargmann <mpa@pengutronix.de>
+ *
+ * Based on pinctrl-imx.c:
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/slab.h>
+
+#include "core.h"
+#include "pinctrl-imx1.h"
+
+struct imx1_pinctrl {
+ struct device *dev;
+ struct pinctrl_dev *pctl;
+ void __iomem *base;
+ const struct imx1_pinctrl_soc_info *info;
+};
+
+/*
+ * MX1 register offsets
+ */
+
+#define MX1_DDIR 0x00
+#define MX1_OCR 0x04
+#define MX1_ICONFA 0x0c
+#define MX1_ICONFB 0x10
+#define MX1_GIUS 0x20
+#define MX1_GPR 0x38
+#define MX1_PUEN 0x40
+
+#define MX1_PORT_STRIDE 0x100
+
+
+/*
+ * MUX_ID format defines
+ */
+#define MX1_MUX_FUNCTION(val) (BIT(0) & val)
+#define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1)
+#define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2)
+#define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4)
+#define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8)
+#define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10)
+
+
+/*
+ * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX
+ * control register are seperated into function, output configuration, input
+ * configuration A, input configuration B, GPIO in use and data direction.
+ *
+ * Those controls that are represented by 1 bit have a direct mapping between
+ * bit position and pin id. If they are represented by 2 bit, the lower 16 pins
+ * are in the first register and the upper 16 pins in the second (next)
+ * register. pin_id is stored in bit (pin_id%16)*2 and the bit above.
+ */
+
+/*
+ * Calculates the register offset from a pin_id
+ */
+static void __iomem *imx1_mem(struct imx1_pinctrl *ipctl, unsigned int pin_id)
+{
+ unsigned int port = pin_id / 32;
+ return ipctl->base + port * MX1_PORT_STRIDE;
+}
+
+/*
+ * Write to a register with 2 bits per pin. The function will automatically
+ * use the next register if the pin is managed in the second register.
+ */
+static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
+ u32 value, u32 reg_offset)
+{
+ void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
+ int offset = (pin_id % 16) * 2; /* offset, regardless of register used */
+ int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */
+ u32 old_val;
+ u32 new_val;
+
+ dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
+ reg, offset, value);
+
+ /* Use the next register if the pin's port pin number is >=16 */
+ if (pin_id % 32 >= 16)
+ reg += 0x04;
+
+ /* Get current state of pins */
+ old_val = readl(reg);
+ old_val &= mask;
+
+ new_val = value & 0x3; /* Make sure value is really 2 bit */
+ new_val <<= offset;
+ new_val |= old_val;/* Set new state for pin_id */
+
+ writel(new_val, reg);
+}
+
+static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
+ u32 value, u32 reg_offset)
+{
+ void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
+ int offset = pin_id % 32;
+ int mask = ~BIT_MASK(offset);
+ u32 old_val;
+ u32 new_val;
+
+ /* Get current state of pins */
+ old_val = readl(reg);
+ old_val &= mask;
+
+ new_val = value & 0x1; /* Make sure value is really 1 bit */
+ new_val <<= offset;
+ new_val |= old_val;/* Set new state for pin_id */
+
+ writel(new_val, reg);
+}
+
+static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
+ u32 reg_offset)
+{
+ void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
+ int offset = pin_id % 16;
+
+ /* Use the next register if the pin's port pin number is >=16 */
+ if (pin_id % 32 >= 16)
+ reg += 0x04;
+
+ return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset;
+}
+
+static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
+ u32 reg_offset)
+{
+ void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
+ int offset = pin_id % 32;
+
+ return !!(readl(reg) & BIT(offset));
+}
+
+static const inline struct imx1_pin_group *imx1_pinctrl_find_group_by_name(
+ const struct imx1_pinctrl_soc_info *info,
+ const char *name)
+{
+ const struct imx1_pin_group *grp = NULL;
+ int i;
+
+ for (i = 0; i < info->ngroups; i++) {
+ if (!strcmp(info->groups[i].name, name)) {
+ grp = &info->groups[i];
+ break;
+ }
+ }
+
+ return grp;
+}
+
+static int imx1_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ return info->ngroups;
+}
+
+static const char *imx1_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned selector)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ return info->groups[selector].name;
+}
+
+static int imx1_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
+ const unsigned int **pins,
+ unsigned *npins)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ if (selector >= info->ngroups)
+ return -EINVAL;
+
+ *pins = info->groups[selector].pin_ids;
+ *npins = info->groups[selector].npins;
+
+ return 0;
+}
+
+static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+ unsigned offset)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+
+ seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d",
+ imx1_read_bit(ipctl, offset, MX1_GIUS),
+ imx1_read_bit(ipctl, offset, MX1_GPR),
+ imx1_read_bit(ipctl, offset, MX1_DDIR),
+ imx1_read_2bit(ipctl, offset, MX1_OCR),
+ imx1_read_2bit(ipctl, offset, MX1_ICONFA),
+ imx1_read_2bit(ipctl, offset, MX1_ICONFB));
+}
+
+static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **map, unsigned *num_maps)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+ const struct imx1_pin_group *grp;
+ struct pinctrl_map *new_map;
+ struct device_node *parent;
+ int map_num = 1;
+ int i, j;
+
+ /*
+ * first find the group of this node and check if we need create
+ * config maps for pins
+ */
+ grp = imx1_pinctrl_find_group_by_name(info, np->name);
+ if (!grp) {
+ dev_err(info->dev, "unable to find group for node %s\n",
+ np->name);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < grp->npins; i++)
+ map_num++;
+
+ new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
+ if (!new_map)
+ return -ENOMEM;
+
+ *map = new_map;
+ *num_maps = map_num;
+
+ /* create mux map */
+ parent = of_get_parent(np);
+ if (!parent) {
+ kfree(new_map);
+ return -EINVAL;
+ }
+ new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
+ new_map[0].data.mux.function = parent->name;
+ new_map[0].data.mux.group = np->name;
+ of_node_put(parent);
+
+ /* create config map */
+ new_map++;
+ for (i = j = 0; i < grp->npins; i++) {
+ new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
+ new_map[j].data.configs.group_or_pin =
+ pin_get_name(pctldev, grp->pins[i].pin_id);
+ new_map[j].data.configs.configs = &grp->pins[i].config;
+ new_map[j].data.configs.num_configs = 1;
+ j++;
+ }
+
+ dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
+ (*map)->data.mux.function, (*map)->data.mux.group, map_num);
+
+ return 0;
+}
+
+static void imx1_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map, unsigned num_maps)
+{
+ kfree(map);
+}
+
+static const struct pinctrl_ops imx1_pctrl_ops = {
+ .get_groups_count = imx1_get_groups_count,
+ .get_group_name = imx1_get_group_name,
+ .get_group_pins = imx1_get_group_pins,
+ .pin_dbg_show = imx1_pin_dbg_show,
+ .dt_node_to_map = imx1_dt_node_to_map,
+ .dt_free_map = imx1_dt_free_map,
+
+};
+
+static int imx1_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
+ unsigned group)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+ const struct imx1_pin *pins;
+ unsigned int npins;
+ int i;
+
+ /*
+ * Configure the mux mode for each pin in the group for a specific
+ * function.
+ */
+ pins = info->groups[group].pins;
+ npins = info->groups[group].npins;
+
+ WARN_ON(!pins || !npins);
+
+ dev_dbg(ipctl->dev, "enable function %s group %s\n",
+ info->functions[selector].name, info->groups[group].name);
+
+ for (i = 0; i < npins; i++) {
+ unsigned int mux = pins[i].mux_id;
+ unsigned int pin_id = pins[i].pin_id;
+ unsigned int afunction = MX1_MUX_FUNCTION(mux);
+ unsigned int gpio_in_use = MX1_MUX_GPIO(mux);
+ unsigned int direction = MX1_MUX_DIR(mux);
+ unsigned int gpio_oconf = MX1_MUX_OCONF(mux);
+ unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux);
+ unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux);
+
+ dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n",
+ __func__, pin_id, afunction, gpio_in_use,
+ direction, gpio_oconf, gpio_iconfa,
+ gpio_iconfb);
+
+ imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS);
+ imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR);
+
+ if (gpio_in_use) {
+ imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR);
+ imx1_write_2bit(ipctl, pin_id, gpio_iconfa,
+ MX1_ICONFA);
+ imx1_write_2bit(ipctl, pin_id, gpio_iconfb,
+ MX1_ICONFB);
+ } else {
+ imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR);
+ }
+ }
+
+ return 0;
+}
+
+static int imx1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ return info->nfunctions;
+}
+
+static const char *imx1_pmx_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned selector)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ return info->functions[selector].name;
+}
+
+static int imx1_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
+ const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+
+ *groups = info->functions[selector].groups;
+ *num_groups = info->functions[selector].num_groups;
+
+ return 0;
+}
+
+static const struct pinmux_ops imx1_pmx_ops = {
+ .get_functions_count = imx1_pmx_get_funcs_count,
+ .get_function_name = imx1_pmx_get_func_name,
+ .get_function_groups = imx1_pmx_get_groups,
+ .enable = imx1_pmx_enable,
+};
+
+static int imx1_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *config)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *config = imx1_read_bit(ipctl, pin_id, MX1_PUEN);
+
+ return 0;
+}
+
+static int imx1_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+ int i;
+
+ for (i = 0; i != num_configs; ++i) {
+ imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN);
+
+ dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n",
+ info->pins[pin_id].name);
+ }
+
+ return 0;
+}
+
+static void imx1_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned pin_id)
+{
+ unsigned long config;
+
+ imx1_pinconf_get(pctldev, pin_id, &config);
+ seq_printf(s, "0x%lx", config);
+}
+
+static void imx1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned group)
+{
+ struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx1_pinctrl_soc_info *info = ipctl->info;
+ struct imx1_pin_group *grp;
+ unsigned long config;
+ const char *name;
+ int i, ret;
+
+ if (group > info->ngroups)
+ return;
+
+ seq_puts(s, "\n");
+ grp = &info->groups[group];
+ for (i = 0; i < grp->npins; i++) {
+ name = pin_get_name(pctldev, grp->pins[i].pin_id);
+ ret = imx1_pinconf_get(pctldev, grp->pins[i].pin_id, &config);
+ if (ret)
+ return;
+ seq_printf(s, "%s: 0x%lx", name, config);
+ }
+}
+
+static const struct pinconf_ops imx1_pinconf_ops = {
+ .pin_config_get = imx1_pinconf_get,
+ .pin_config_set = imx1_pinconf_set,
+ .pin_config_dbg_show = imx1_pinconf_dbg_show,
+ .pin_config_group_dbg_show = imx1_pinconf_group_dbg_show,
+};
+
+static struct pinctrl_desc imx1_pinctrl_desc = {
+ .pctlops = &imx1_pctrl_ops,
+ .pmxops = &imx1_pmx_ops,
+ .confops = &imx1_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+static int imx1_pinctrl_parse_groups(struct device_node *np,
+ struct imx1_pin_group *grp,
+ struct imx1_pinctrl_soc_info *info,
+ u32 index)
+{
+ int size;
+ const __be32 *list;
+ int i;
+
+ dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
+
+ /* Initialise group */
+ grp->name = np->name;
+
+ /*
+ * the binding format is fsl,pins = <PIN MUX_ID CONFIG>
+ */
+ list = of_get_property(np, "fsl,pins", &size);
+ /* we do not check return since it's safe node passed down */
+ if (!size || size % 12) {
+ dev_notice(info->dev, "Not a valid fsl,pins property (%s)\n",
+ np->name);
+ return -EINVAL;
+ }
+
+ grp->npins = size / 12;
+ grp->pins = devm_kzalloc(info->dev,
+ grp->npins * sizeof(struct imx1_pin), GFP_KERNEL);
+ grp->pin_ids = devm_kzalloc(info->dev,
+ grp->npins * sizeof(unsigned int), GFP_KERNEL);
+
+ if (!grp->pins || !grp->pin_ids)
+ return -ENOMEM;
+
+ for (i = 0; i < grp->npins; i++) {
+ grp->pins[i].pin_id = be32_to_cpu(*list++);
+ grp->pins[i].mux_id = be32_to_cpu(*list++);
+ grp->pins[i].config = be32_to_cpu(*list++);
+
+ grp->pin_ids[i] = grp->pins[i].pin_id;
+ }
+
+ return 0;
+}
+
+static int imx1_pinctrl_parse_functions(struct device_node *np,
+ struct imx1_pinctrl_soc_info *info,
+ u32 index)
+{
+ struct device_node *child;
+ struct imx1_pmx_func *func;
+ struct imx1_pin_group *grp;
+ int ret;
+ static u32 grp_index;
+ u32 i = 0;
+
+ dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
+
+ func = &info->functions[index];
+
+ /* Initialise function */
+ func->name = np->name;
+ func->num_groups = of_get_child_count(np);
+ if (func->num_groups <= 0)
+ return -EINVAL;
+
+ func->groups = devm_kzalloc(info->dev,
+ func->num_groups * sizeof(char *), GFP_KERNEL);
+
+ if (!func->groups)
+ return -ENOMEM;
+
+ for_each_child_of_node(np, child) {
+ func->groups[i] = child->name;
+ grp = &info->groups[grp_index++];
+ ret = imx1_pinctrl_parse_groups(child, grp, info, i++);
+ if (ret == -ENOMEM)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
+ struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *child;
+ int ret;
+ u32 nfuncs = 0;
+ u32 ngroups = 0;
+ u32 ifunc = 0;
+
+ if (!np)
+ return -ENODEV;
+
+ for_each_child_of_node(np, child) {
+ ++nfuncs;
+ ngroups += of_get_child_count(child);
+ }
+
+ if (!nfuncs) {
+ dev_err(&pdev->dev, "No pin functions defined\n");
+ return -EINVAL;
+ }
+
+ info->nfunctions = nfuncs;
+ info->functions = devm_kzalloc(&pdev->dev,
+ nfuncs * sizeof(struct imx1_pmx_func), GFP_KERNEL);
+
+ info->ngroups = ngroups;
+ info->groups = devm_kzalloc(&pdev->dev,
+ ngroups * sizeof(struct imx1_pin_group), GFP_KERNEL);
+
+
+ if (!info->functions || !info->groups)
+ return -ENOMEM;
+
+ for_each_child_of_node(np, child) {
+ ret = imx1_pinctrl_parse_functions(child, info, ifunc++);
+ if (ret == -ENOMEM)
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+int imx1_pinctrl_core_probe(struct platform_device *pdev,
+ struct imx1_pinctrl_soc_info *info)
+{
+ struct imx1_pinctrl *ipctl;
+ struct resource *res;
+ struct pinctrl_desc *pctl_desc;
+ int ret;
+
+ if (!info || !info->pins || !info->npins) {
+ dev_err(&pdev->dev, "wrong pinctrl info\n");
+ return -EINVAL;
+ }
+ info->dev = &pdev->dev;
+
+ /* Create state holders etc for this driver */
+ ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
+ if (!ipctl)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENOENT;
+
+ ipctl->base = devm_ioremap_nocache(&pdev->dev, res->start,
+ resource_size(res));
+ if (!ipctl->base)
+ return -ENOMEM;
+
+ pctl_desc = &imx1_pinctrl_desc;
+ pctl_desc->name = dev_name(&pdev->dev);
+ pctl_desc->pins = info->pins;
+ pctl_desc->npins = info->npins;
+
+ ret = imx1_pinctrl_parse_dt(pdev, ipctl, info);
+ if (ret) {
+ dev_err(&pdev->dev, "fail to probe dt properties\n");
+ return ret;
+ }
+
+ ipctl->info = info;
+ ipctl->dev = info->dev;
+ platform_set_drvdata(pdev, ipctl);
+ ipctl->pctl = pinctrl_register(pctl_desc, &pdev->dev, ipctl);
+ if (!ipctl->pctl) {
+ dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
+ return -EINVAL;
+ }
+
+ dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
+
+ return 0;
+}
+
+int imx1_pinctrl_core_remove(struct platform_device *pdev)
+{
+ struct imx1_pinctrl *ipctl = platform_get_drvdata(pdev);
+
+ pinctrl_unregister(ipctl->pctl);
+
+ return 0;
+}
--- /dev/null
+/*
+ * IMX pinmux core definitions
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DRIVERS_PINCTRL_IMX1_H
+#define __DRIVERS_PINCTRL_IMX1_H
+
+struct platform_device;
+
+/**
+ * struct imx1_pin - describes an IMX1/21/27 pin.
+ * @pin_id: ID of the described pin.
+ * @mux_id: ID of the mux setup.
+ * @config: Configuration of the pin (currently only pullup-enable).
+ */
+struct imx1_pin {
+ unsigned int pin_id;
+ unsigned int mux_id;
+ unsigned long config;
+};
+
+/**
+ * struct imx1_pin_group - describes an IMX pin group
+ * @name: the name of this specific pin group
+ * @pins: an array of imx1_pin structs used in this group
+ * @npins: the number of pins in this group array, i.e. the number of
+ * elements in .pins so we can iterate over that array
+ */
+struct imx1_pin_group {
+ const char *name;
+ unsigned int *pin_ids;
+ struct imx1_pin *pins;
+ unsigned npins;
+};
+
+/**
+ * struct imx1_pmx_func - describes IMX pinmux functions
+ * @name: the name of this specific function
+ * @groups: corresponding pin groups
+ * @num_groups: the number of groups
+ */
+struct imx1_pmx_func {
+ const char *name;
+ const char **groups;
+ unsigned num_groups;
+};
+
+struct imx1_pinctrl_soc_info {
+ struct device *dev;
+ const struct pinctrl_pin_desc *pins;
+ unsigned int npins;
+ struct imx1_pin_group *groups;
+ unsigned int ngroups;
+ struct imx1_pmx_func *functions;
+ unsigned int nfunctions;
+};
+
+#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
+
+int imx1_pinctrl_core_probe(struct platform_device *pdev,
+ struct imx1_pinctrl_soc_info *info);
+int imx1_pinctrl_core_remove(struct platform_device *pdev);
+#endif /* __DRIVERS_PINCTRL_IMX1_H */
--- /dev/null
+/*
+ * imx27 pinctrl driver based on imx pinmux core
+ *
+ * Copyright (C) 2013 Pengutronix
+ *
+ * Author: Markus Pargmann <mpa@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx1.h"
+
+#define PAD_ID(port, pin) (port*32 + pin)
+#define PA 0
+#define PB 1
+#define PC 2
+#define PD 3
+#define PE 4
+#define PF 5
+
+enum imx27_pads {
+ MX27_PAD_USBH2_CLK = PAD_ID(PA, 0),
+ MX27_PAD_USBH2_DIR = PAD_ID(PA, 1),
+ MX27_PAD_USBH2_DATA7 = PAD_ID(PA, 2),
+ MX27_PAD_USBH2_NXT = PAD_ID(PA, 3),
+ MX27_PAD_USBH2_STP = PAD_ID(PA, 4),
+ MX27_PAD_LSCLK = PAD_ID(PA, 5),
+ MX27_PAD_LD0 = PAD_ID(PA, 6),
+ MX27_PAD_LD1 = PAD_ID(PA, 7),
+ MX27_PAD_LD2 = PAD_ID(PA, 8),
+ MX27_PAD_LD3 = PAD_ID(PA, 9),
+ MX27_PAD_LD4 = PAD_ID(PA, 10),
+ MX27_PAD_LD5 = PAD_ID(PA, 11),
+ MX27_PAD_LD6 = PAD_ID(PA, 12),
+ MX27_PAD_LD7 = PAD_ID(PA, 13),
+ MX27_PAD_LD8 = PAD_ID(PA, 14),
+ MX27_PAD_LD9 = PAD_ID(PA, 15),
+ MX27_PAD_LD10 = PAD_ID(PA, 16),
+ MX27_PAD_LD11 = PAD_ID(PA, 17),
+ MX27_PAD_LD12 = PAD_ID(PA, 18),
+ MX27_PAD_LD13 = PAD_ID(PA, 19),
+ MX27_PAD_LD14 = PAD_ID(PA, 20),
+ MX27_PAD_LD15 = PAD_ID(PA, 21),
+ MX27_PAD_LD16 = PAD_ID(PA, 22),
+ MX27_PAD_LD17 = PAD_ID(PA, 23),
+ MX27_PAD_REV = PAD_ID(PA, 24),
+ MX27_PAD_CLS = PAD_ID(PA, 25),
+ MX27_PAD_PS = PAD_ID(PA, 26),
+ MX27_PAD_SPL_SPR = PAD_ID(PA, 27),
+ MX27_PAD_HSYNC = PAD_ID(PA, 28),
+ MX27_PAD_VSYNC = PAD_ID(PA, 29),
+ MX27_PAD_CONTRAST = PAD_ID(PA, 30),
+ MX27_PAD_OE_ACD = PAD_ID(PA, 31),
+
+ MX27_PAD_UNUSED0 = PAD_ID(PB, 0),
+ MX27_PAD_UNUSED1 = PAD_ID(PB, 1),
+ MX27_PAD_UNUSED2 = PAD_ID(PB, 2),
+ MX27_PAD_UNUSED3 = PAD_ID(PB, 3),
+ MX27_PAD_SD2_D0 = PAD_ID(PB, 4),
+ MX27_PAD_SD2_D1 = PAD_ID(PB, 5),
+ MX27_PAD_SD2_D2 = PAD_ID(PB, 6),
+ MX27_PAD_SD2_D3 = PAD_ID(PB, 7),
+ MX27_PAD_SD2_CMD = PAD_ID(PB, 8),
+ MX27_PAD_SD2_CLK = PAD_ID(PB, 9),
+ MX27_PAD_CSI_D0 = PAD_ID(PB, 10),
+ MX27_PAD_CSI_D1 = PAD_ID(PB, 11),
+ MX27_PAD_CSI_D2 = PAD_ID(PB, 12),
+ MX27_PAD_CSI_D3 = PAD_ID(PB, 13),
+ MX27_PAD_CSI_D4 = PAD_ID(PB, 14),
+ MX27_PAD_CSI_MCLK = PAD_ID(PB, 15),
+ MX27_PAD_CSI_PIXCLK = PAD_ID(PB, 16),
+ MX27_PAD_CSI_D5 = PAD_ID(PB, 17),
+ MX27_PAD_CSI_D6 = PAD_ID(PB, 18),
+ MX27_PAD_CSI_D7 = PAD_ID(PB, 19),
+ MX27_PAD_CSI_VSYNC = PAD_ID(PB, 20),
+ MX27_PAD_CSI_HSYNC = PAD_ID(PB, 21),
+ MX27_PAD_USBH1_SUSP = PAD_ID(PB, 22),
+ MX27_PAD_USB_PWR = PAD_ID(PB, 23),
+ MX27_PAD_USB_OC_B = PAD_ID(PB, 24),
+ MX27_PAD_USBH1_RCV = PAD_ID(PB, 25),
+ MX27_PAD_USBH1_FS = PAD_ID(PB, 26),
+ MX27_PAD_USBH1_OE_B = PAD_ID(PB, 27),
+ MX27_PAD_USBH1_TXDM = PAD_ID(PB, 28),
+ MX27_PAD_USBH1_TXDP = PAD_ID(PB, 29),
+ MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30),
+ MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31),
+
+ MX27_PAD_UNUSED4 = PAD_ID(PC, 0),
+ MX27_PAD_UNUSED5 = PAD_ID(PC, 1),
+ MX27_PAD_UNUSED6 = PAD_ID(PC, 2),
+ MX27_PAD_UNUSED7 = PAD_ID(PC, 3),
+ MX27_PAD_UNUSED8 = PAD_ID(PC, 4),
+ MX27_PAD_I2C2_SDA = PAD_ID(PC, 5),
+ MX27_PAD_I2C2_SCL = PAD_ID(PC, 6),
+ MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7),
+ MX27_PAD_USBOTG_DATA6 = PAD_ID(PC, 8),
+ MX27_PAD_USBOTG_DATA0 = PAD_ID(PC, 9),
+ MX27_PAD_USBOTG_DATA2 = PAD_ID(PC, 10),
+ MX27_PAD_USBOTG_DATA1 = PAD_ID(PC, 11),
+ MX27_PAD_USBOTG_DATA4 = PAD_ID(PC, 12),
+ MX27_PAD_USBOTG_DATA3 = PAD_ID(PC, 13),
+ MX27_PAD_TOUT = PAD_ID(PC, 14),
+ MX27_PAD_TIN = PAD_ID(PC, 15),
+ MX27_PAD_SSI4_FS = PAD_ID(PC, 16),
+ MX27_PAD_SSI4_RXDAT = PAD_ID(PC, 17),
+ MX27_PAD_SSI4_TXDAT = PAD_ID(PC, 18),
+ MX27_PAD_SSI4_CLK = PAD_ID(PC, 19),
+ MX27_PAD_SSI1_FS = PAD_ID(PC, 20),
+ MX27_PAD_SSI1_RXDAT = PAD_ID(PC, 21),
+ MX27_PAD_SSI1_TXDAT = PAD_ID(PC, 22),
+ MX27_PAD_SSI1_CLK = PAD_ID(PC, 23),
+ MX27_PAD_SSI2_FS = PAD_ID(PC, 24),
+ MX27_PAD_SSI2_RXDAT = PAD_ID(PC, 25),
+ MX27_PAD_SSI2_TXDAT = PAD_ID(PC, 26),
+ MX27_PAD_SSI2_CLK = PAD_ID(PC, 27),
+ MX27_PAD_SSI3_FS = PAD_ID(PC, 28),
+ MX27_PAD_SSI3_RXDAT = PAD_ID(PC, 29),
+ MX27_PAD_SSI3_TXDAT = PAD_ID(PC, 30),
+ MX27_PAD_SSI3_CLK = PAD_ID(PC, 31),
+
+ MX27_PAD_SD3_CMD = PAD_ID(PD, 0),
+ MX27_PAD_SD3_CLK = PAD_ID(PD, 1),
+ MX27_PAD_ATA_DATA0 = PAD_ID(PD, 2),
+ MX27_PAD_ATA_DATA1 = PAD_ID(PD, 3),
+ MX27_PAD_ATA_DATA2 = PAD_ID(PD, 4),
+ MX27_PAD_ATA_DATA3 = PAD_ID(PD, 5),
+ MX27_PAD_ATA_DATA4 = PAD_ID(PD, 6),
+ MX27_PAD_ATA_DATA5 = PAD_ID(PD, 7),
+ MX27_PAD_ATA_DATA6 = PAD_ID(PD, 8),
+ MX27_PAD_ATA_DATA7 = PAD_ID(PD, 9),
+ MX27_PAD_ATA_DATA8 = PAD_ID(PD, 10),
+ MX27_PAD_ATA_DATA9 = PAD_ID(PD, 11),
+ MX27_PAD_ATA_DATA10 = PAD_ID(PD, 12),
+ MX27_PAD_ATA_DATA11 = PAD_ID(PD, 13),
+ MX27_PAD_ATA_DATA12 = PAD_ID(PD, 14),
+ MX27_PAD_ATA_DATA13 = PAD_ID(PD, 15),
+ MX27_PAD_ATA_DATA14 = PAD_ID(PD, 16),
+ MX27_PAD_I2C_DATA = PAD_ID(PD, 17),
+ MX27_PAD_I2C_CLK = PAD_ID(PD, 18),
+ MX27_PAD_CSPI2_SS2 = PAD_ID(PD, 19),
+ MX27_PAD_CSPI2_SS1 = PAD_ID(PD, 20),
+ MX27_PAD_CSPI2_SS0 = PAD_ID(PD, 21),
+ MX27_PAD_CSPI2_SCLK = PAD_ID(PD, 22),
+ MX27_PAD_CSPI2_MISO = PAD_ID(PD, 23),
+ MX27_PAD_CSPI2_MOSI = PAD_ID(PD, 24),
+ MX27_PAD_CSPI1_RDY = PAD_ID(PD, 25),
+ MX27_PAD_CSPI1_SS2 = PAD_ID(PD, 26),
+ MX27_PAD_CSPI1_SS1 = PAD_ID(PD, 27),
+ MX27_PAD_CSPI1_SS0 = PAD_ID(PD, 28),
+ MX27_PAD_CSPI1_SCLK = PAD_ID(PD, 29),
+ MX27_PAD_CSPI1_MISO = PAD_ID(PD, 30),
+ MX27_PAD_CSPI1_MOSI = PAD_ID(PD, 31),
+
+ MX27_PAD_USBOTG_NXT = PAD_ID(PE, 0),
+ MX27_PAD_USBOTG_STP = PAD_ID(PE, 1),
+ MX27_PAD_USBOTG_DIR = PAD_ID(PE, 2),
+ MX27_PAD_UART2_CTS = PAD_ID(PE, 3),
+ MX27_PAD_UART2_RTS = PAD_ID(PE, 4),
+ MX27_PAD_PWMO = PAD_ID(PE, 5),
+ MX27_PAD_UART2_TXD = PAD_ID(PE, 6),
+ MX27_PAD_UART2_RXD = PAD_ID(PE, 7),
+ MX27_PAD_UART3_TXD = PAD_ID(PE, 8),
+ MX27_PAD_UART3_RXD = PAD_ID(PE, 9),
+ MX27_PAD_UART3_CTS = PAD_ID(PE, 10),
+ MX27_PAD_UART3_RTS = PAD_ID(PE, 11),
+ MX27_PAD_UART1_TXD = PAD_ID(PE, 12),
+ MX27_PAD_UART1_RXD = PAD_ID(PE, 13),
+ MX27_PAD_UART1_CTS = PAD_ID(PE, 14),
+ MX27_PAD_UART1_RTS = PAD_ID(PE, 15),
+ MX27_PAD_RTCK = PAD_ID(PE, 16),
+ MX27_PAD_RESET_OUT_B = PAD_ID(PE, 17),
+ MX27_PAD_SD1_D0 = PAD_ID(PE, 18),
+ MX27_PAD_SD1_D1 = PAD_ID(PE, 19),
+ MX27_PAD_SD1_D2 = PAD_ID(PE, 20),
+ MX27_PAD_SD1_D3 = PAD_ID(PE, 21),
+ MX27_PAD_SD1_CMD = PAD_ID(PE, 22),
+ MX27_PAD_SD1_CLK = PAD_ID(PE, 23),
+ MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24),
+ MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25),
+ MX27_PAD_UNUSED9 = PAD_ID(PE, 26),
+ MX27_PAD_UNUSED10 = PAD_ID(PE, 27),
+ MX27_PAD_UNUSED11 = PAD_ID(PE, 28),
+ MX27_PAD_UNUSED12 = PAD_ID(PE, 29),
+ MX27_PAD_UNUSED13 = PAD_ID(PE, 30),
+ MX27_PAD_UNUSED14 = PAD_ID(PE, 31),
+
+ MX27_PAD_NFRB = PAD_ID(PF, 0),
+ MX27_PAD_NFCLE = PAD_ID(PF, 1),
+ MX27_PAD_NFWP_B = PAD_ID(PF, 2),
+ MX27_PAD_NFCE_B = PAD_ID(PF, 3),
+ MX27_PAD_NFALE = PAD_ID(PF, 4),
+ MX27_PAD_NFRE_B = PAD_ID(PF, 5),
+ MX27_PAD_NFWE_B = PAD_ID(PF, 6),
+ MX27_PAD_PC_POE = PAD_ID(PF, 7),
+ MX27_PAD_PC_RW_B = PAD_ID(PF, 8),
+ MX27_PAD_IOIS16 = PAD_ID(PF, 9),
+ MX27_PAD_PC_RST = PAD_ID(PF, 10),
+ MX27_PAD_PC_BVD2 = PAD_ID(PF, 11),
+ MX27_PAD_PC_BVD1 = PAD_ID(PF, 12),
+ MX27_PAD_PC_VS2 = PAD_ID(PF, 13),
+ MX27_PAD_PC_VS1 = PAD_ID(PF, 14),
+ MX27_PAD_CLKO = PAD_ID(PF, 15),
+ MX27_PAD_PC_PWRON = PAD_ID(PF, 16),
+ MX27_PAD_PC_READY = PAD_ID(PF, 17),
+ MX27_PAD_PC_WAIT_B = PAD_ID(PF, 18),
+ MX27_PAD_PC_CD2_B = PAD_ID(PF, 19),
+ MX27_PAD_PC_CD1_B = PAD_ID(PF, 20),
+ MX27_PAD_CS4_B = PAD_ID(PF, 21),
+ MX27_PAD_CS5_B = PAD_ID(PF, 22),
+ MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23),
+ MX27_PAD_UNUSED15 = PAD_ID(PF, 24),
+ MX27_PAD_UNUSED16 = PAD_ID(PF, 25),
+ MX27_PAD_UNUSED17 = PAD_ID(PF, 26),
+ MX27_PAD_UNUSED18 = PAD_ID(PF, 27),
+ MX27_PAD_UNUSED19 = PAD_ID(PF, 28),
+ MX27_PAD_UNUSED20 = PAD_ID(PF, 29),
+ MX27_PAD_UNUSED21 = PAD_ID(PF, 30),
+ MX27_PAD_UNUSED22 = PAD_ID(PF, 31),
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_DIR),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_DATA7),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_NXT),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH2_STP),
+ IMX_PINCTRL_PIN(MX27_PAD_LSCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_LD0),
+ IMX_PINCTRL_PIN(MX27_PAD_LD1),
+ IMX_PINCTRL_PIN(MX27_PAD_LD2),
+ IMX_PINCTRL_PIN(MX27_PAD_LD3),
+ IMX_PINCTRL_PIN(MX27_PAD_LD4),
+ IMX_PINCTRL_PIN(MX27_PAD_LD5),
+ IMX_PINCTRL_PIN(MX27_PAD_LD6),
+ IMX_PINCTRL_PIN(MX27_PAD_LD7),
+ IMX_PINCTRL_PIN(MX27_PAD_LD8),
+ IMX_PINCTRL_PIN(MX27_PAD_LD9),
+ IMX_PINCTRL_PIN(MX27_PAD_LD10),
+ IMX_PINCTRL_PIN(MX27_PAD_LD11),
+ IMX_PINCTRL_PIN(MX27_PAD_LD12),
+ IMX_PINCTRL_PIN(MX27_PAD_LD13),
+ IMX_PINCTRL_PIN(MX27_PAD_LD14),
+ IMX_PINCTRL_PIN(MX27_PAD_LD15),
+ IMX_PINCTRL_PIN(MX27_PAD_LD16),
+ IMX_PINCTRL_PIN(MX27_PAD_LD17),
+ IMX_PINCTRL_PIN(MX27_PAD_REV),
+ IMX_PINCTRL_PIN(MX27_PAD_CLS),
+ IMX_PINCTRL_PIN(MX27_PAD_PS),
+ IMX_PINCTRL_PIN(MX27_PAD_SPL_SPR),
+ IMX_PINCTRL_PIN(MX27_PAD_HSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_VSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_CONTRAST),
+ IMX_PINCTRL_PIN(MX27_PAD_OE_ACD),
+
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED0),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED1),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED2),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED3),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D0),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D1),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D2),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_D3),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_CMD),
+ IMX_PINCTRL_PIN(MX27_PAD_SD2_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D0),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D1),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D2),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D3),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D4),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_MCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_PIXCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D5),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D6),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_D7),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_VSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_CSI_HSYNC),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_SUSP),
+ IMX_PINCTRL_PIN(MX27_PAD_USB_PWR),
+ IMX_PINCTRL_PIN(MX27_PAD_USB_OC_B),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_RCV),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_OE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDM),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDP),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM),
+ IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP),
+
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED4),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED5),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED6),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED7),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED8),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA6),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA0),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA2),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA1),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA4),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA3),
+ IMX_PINCTRL_PIN(MX27_PAD_TOUT),
+ IMX_PINCTRL_PIN(MX27_PAD_TIN),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI4_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI1_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI2_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_FS),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_RXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_TXDAT),
+ IMX_PINCTRL_PIN(MX27_PAD_SSI3_CLK),
+
+ IMX_PINCTRL_PIN(MX27_PAD_SD3_CMD),
+ IMX_PINCTRL_PIN(MX27_PAD_SD3_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA0),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA1),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA2),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA3),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA4),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA5),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA6),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA7),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA8),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA9),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA10),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA11),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA12),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA13),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA14),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C_DATA),
+ IMX_PINCTRL_PIN(MX27_PAD_I2C_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS2),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS1),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS0),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MISO),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MOSI),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_RDY),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS2),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS1),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS0),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SCLK),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MISO),
+ IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MOSI),
+
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_NXT),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_STP),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DIR),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_CTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_RTS),
+ IMX_PINCTRL_PIN(MX27_PAD_PWMO),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_TXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART2_RXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_TXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_RXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_CTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART3_RTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_TXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_RXD),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_CTS),
+ IMX_PINCTRL_PIN(MX27_PAD_UART1_RTS),
+ IMX_PINCTRL_PIN(MX27_PAD_RTCK),
+ IMX_PINCTRL_PIN(MX27_PAD_RESET_OUT_B),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D0),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D1),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D2),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_D3),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK),
+ IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED9),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED10),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED11),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED12),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED13),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED14),
+
+ IMX_PINCTRL_PIN(MX27_PAD_NFRB),
+ IMX_PINCTRL_PIN(MX27_PAD_NFCLE),
+ IMX_PINCTRL_PIN(MX27_PAD_NFWP_B),
+ IMX_PINCTRL_PIN(MX27_PAD_NFCE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_NFALE),
+ IMX_PINCTRL_PIN(MX27_PAD_NFRE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_NFWE_B),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_POE),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_RW_B),
+ IMX_PINCTRL_PIN(MX27_PAD_IOIS16),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_RST),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_BVD2),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_BVD1),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_VS2),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_VS1),
+ IMX_PINCTRL_PIN(MX27_PAD_CLKO),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_PWRON),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_READY),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_WAIT_B),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_CD2_B),
+ IMX_PINCTRL_PIN(MX27_PAD_PC_CD1_B),
+ IMX_PINCTRL_PIN(MX27_PAD_CS4_B),
+ IMX_PINCTRL_PIN(MX27_PAD_CS5_B),
+ IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED15),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED16),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED17),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED18),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED19),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED20),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED21),
+ IMX_PINCTRL_PIN(MX27_PAD_UNUSED22),
+};
+
+static struct imx1_pinctrl_soc_info imx27_pinctrl_info = {
+ .pins = imx27_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx27_pinctrl_pads),
+};
+
+static struct of_device_id imx27_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx27-iomuxc", },
+ { /* sentinel */ }
+};
+
+struct imx27_pinctrl_private {
+ int num_gpio_childs;
+ struct platform_device **gpio_dev;
+ struct mxc_gpio_platform_data *gpio_pdata;
+};
+
+static int imx27_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info);
+}
+
+static struct platform_driver imx27_pinctrl_driver = {
+ .driver = {
+ .name = "imx27-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(imx27_pinctrl_of_match),
+ },
+ .probe = imx27_pinctrl_probe,
+ .remove = imx1_pinctrl_core_remove,
+};
+
+static int __init imx27_pinctrl_init(void)
+{
+ return platform_driver_register(&imx27_pinctrl_driver);
+}
+arch_initcall(imx27_pinctrl_init);
+
+static void __exit imx27_pinctrl_exit(void)
+{
+ platform_driver_unregister(&imx27_pinctrl_driver);
+}
+module_exit(imx27_pinctrl_exit);
+MODULE_AUTHOR("Markus Pargmann <mpa@pengutronix.de>");
+MODULE_DESCRIPTION("Freescale IMX27 pinctrl driver");
+MODULE_LICENSE("GPL v2");
.driver = {
.name = "imx35-pinctrl",
.owner = THIS_MODULE,
- .of_match_table = of_match_ptr(imx35_pinctrl_of_match),
+ .of_match_table = imx35_pinctrl_of_match,
},
.probe = imx35_pinctrl_probe,
.remove = imx_pinctrl_remove,
--- /dev/null
+/*
+ * imx50 pinctrl driver based on imx pinmux core
+ *
+ * Copyright (C) 2013 Greg Ungerer <gerg@uclinux.org>
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx50_pads {
+ MX50_PAD_RESERVE0 = 0,
+ MX50_PAD_RESERVE1 = 1,
+ MX50_PAD_RESERVE2 = 2,
+ MX50_PAD_RESERVE3 = 3,
+ MX50_PAD_RESERVE4 = 4,
+ MX50_PAD_RESERVE5 = 5,
+ MX50_PAD_RESERVE6 = 6,
+ MX50_PAD_RESERVE7 = 7,
+ MX50_PAD_KEY_COL0 = 8,
+ MX50_PAD_KEY_ROW0 = 9,
+ MX50_PAD_KEY_COL1 = 10,
+ MX50_PAD_KEY_ROW1 = 11,
+ MX50_PAD_KEY_COL2 = 12,
+ MX50_PAD_KEY_ROW2 = 13,
+ MX50_PAD_KEY_COL3 = 14,
+ MX50_PAD_KEY_ROW3 = 15,
+ MX50_PAD_I2C1_SCL = 16,
+ MX50_PAD_I2C1_SDA = 17,
+ MX50_PAD_I2C2_SCL = 18,
+ MX50_PAD_I2C2_SDA = 19,
+ MX50_PAD_I2C3_SCL = 20,
+ MX50_PAD_I2C3_SDA = 21,
+ MX50_PAD_PWM1 = 22,
+ MX50_PAD_PWM2 = 23,
+ MX50_PAD_0WIRE = 24,
+ MX50_PAD_EPITO = 25,
+ MX50_PAD_WDOG = 26,
+ MX50_PAD_SSI_TXFS = 27,
+ MX50_PAD_SSI_TXC = 28,
+ MX50_PAD_SSI_TXD = 29,
+ MX50_PAD_SSI_RXD = 30,
+ MX50_PAD_SSI_RXF = 31,
+ MX50_PAD_SSI_RXC = 32,
+ MX50_PAD_UART1_TXD = 33,
+ MX50_PAD_UART1_RXD = 34,
+ MX50_PAD_UART1_CTS = 35,
+ MX50_PAD_UART1_RTS = 36,
+ MX50_PAD_UART2_TXD = 37,
+ MX50_PAD_UART2_RXD = 38,
+ MX50_PAD_UART2_CTS = 39,
+ MX50_PAD_UART2_RTS = 40,
+ MX50_PAD_UART3_TXD = 41,
+ MX50_PAD_UART3_RXD = 42,
+ MX50_PAD_UART4_TXD = 43,
+ MX50_PAD_UART4_RXD = 44,
+ MX50_PAD_CSPI_CLK = 45,
+ MX50_PAD_CSPI_MOSI = 46,
+ MX50_PAD_CSPI_MISO = 47,
+ MX50_PAD_CSPI_SS0 = 48,
+ MX50_PAD_ECSPI1_CLK = 49,
+ MX50_PAD_ECSPI1_MOSI = 50,
+ MX50_PAD_ECSPI1_MISO = 51,
+ MX50_PAD_ECSPI1_SS0 = 52,
+ MX50_PAD_ECSPI2_CLK = 53,
+ MX50_PAD_ECSPI2_MOSI = 54,
+ MX50_PAD_ECSPI2_MISO = 55,
+ MX50_PAD_ECSPI2_SS0 = 56,
+ MX50_PAD_SD1_CLK = 57,
+ MX50_PAD_SD1_CMD = 58,
+ MX50_PAD_SD1_D0 = 59,
+ MX50_PAD_SD1_D1 = 60,
+ MX50_PAD_SD1_D2 = 61,
+ MX50_PAD_SD1_D3 = 62,
+ MX50_PAD_SD2_CLK = 63,
+ MX50_PAD_SD2_CMD = 64,
+ MX50_PAD_SD2_D0 = 65,
+ MX50_PAD_SD2_D1 = 66,
+ MX50_PAD_SD2_D2 = 67,
+ MX50_PAD_SD2_D3 = 68,
+ MX50_PAD_SD2_D4 = 69,
+ MX50_PAD_SD2_D5 = 70,
+ MX50_PAD_SD2_D6 = 71,
+ MX50_PAD_SD2_D7 = 72,
+ MX50_PAD_SD2_WP = 73,
+ MX50_PAD_SD2_CD = 74,
+ MX50_PAD_DISP_D0 = 75,
+ MX50_PAD_DISP_D1 = 76,
+ MX50_PAD_DISP_D2 = 77,
+ MX50_PAD_DISP_D3 = 78,
+ MX50_PAD_DISP_D4 = 79,
+ MX50_PAD_DISP_D5 = 80,
+ MX50_PAD_DISP_D6 = 81,
+ MX50_PAD_DISP_D7 = 82,
+ MX50_PAD_DISP_WR = 83,
+ MX50_PAD_DISP_RD = 84,
+ MX50_PAD_DISP_RS = 85,
+ MX50_PAD_DISP_CS = 86,
+ MX50_PAD_DISP_BUSY = 87,
+ MX50_PAD_DISP_RESET = 88,
+ MX50_PAD_SD3_CLK = 89,
+ MX50_PAD_SD3_CMD = 90,
+ MX50_PAD_SD3_D0 = 91,
+ MX50_PAD_SD3_D1 = 92,
+ MX50_PAD_SD3_D2 = 93,
+ MX50_PAD_SD3_D3 = 94,
+ MX50_PAD_SD3_D4 = 95,
+ MX50_PAD_SD3_D5 = 96,
+ MX50_PAD_SD3_D6 = 97,
+ MX50_PAD_SD3_D7 = 98,
+ MX50_PAD_SD3_WP = 99,
+ MX50_PAD_DISP_D8 = 100,
+ MX50_PAD_DISP_D9 = 101,
+ MX50_PAD_DISP_D10 = 102,
+ MX50_PAD_DISP_D11 = 103,
+ MX50_PAD_DISP_D12 = 104,
+ MX50_PAD_DISP_D13 = 105,
+ MX50_PAD_DISP_D14 = 106,
+ MX50_PAD_DISP_D15 = 107,
+ MX50_PAD_EPDC_D0 = 108,
+ MX50_PAD_EPDC_D1 = 109,
+ MX50_PAD_EPDC_D2 = 110,
+ MX50_PAD_EPDC_D3 = 111,
+ MX50_PAD_EPDC_D4 = 112,
+ MX50_PAD_EPDC_D5 = 113,
+ MX50_PAD_EPDC_D6 = 114,
+ MX50_PAD_EPDC_D7 = 115,
+ MX50_PAD_EPDC_D8 = 116,
+ MX50_PAD_EPDC_D9 = 117,
+ MX50_PAD_EPDC_D10 = 118,
+ MX50_PAD_EPDC_D11 = 119,
+ MX50_PAD_EPDC_D12 = 120,
+ MX50_PAD_EPDC_D13 = 121,
+ MX50_PAD_EPDC_D14 = 122,
+ MX50_PAD_EPDC_D15 = 123,
+ MX50_PAD_EPDC_GDCLK = 124,
+ MX50_PAD_EPDC_GDSP = 125,
+ MX50_PAD_EPDC_GDOE = 126,
+ MX50_PAD_EPDC_GDRL = 127,
+ MX50_PAD_EPDC_SDCLK = 128,
+ MX50_PAD_EPDC_SDOEZ = 129,
+ MX50_PAD_EPDC_SDOED = 130,
+ MX50_PAD_EPDC_SDOE = 131,
+ MX50_PAD_EPDC_SDLE = 132,
+ MX50_PAD_EPDC_SDCLKN = 133,
+ MX50_PAD_EPDC_SDSHR = 134,
+ MX50_PAD_EPDC_PWRCOM = 135,
+ MX50_PAD_EPDC_PWRSTAT = 136,
+ MX50_PAD_EPDC_PWRCTRL0 = 137,
+ MX50_PAD_EPDC_PWRCTRL1 = 138,
+ MX50_PAD_EPDC_PWRCTRL2 = 139,
+ MX50_PAD_EPDC_PWRCTRL3 = 140,
+ MX50_PAD_EPDC_VCOM0 = 141,
+ MX50_PAD_EPDC_VCOM1 = 142,
+ MX50_PAD_EPDC_BDR0 = 143,
+ MX50_PAD_EPDC_BDR1 = 144,
+ MX50_PAD_EPDC_SDCE0 = 145,
+ MX50_PAD_EPDC_SDCE1 = 146,
+ MX50_PAD_EPDC_SDCE2 = 147,
+ MX50_PAD_EPDC_SDCE3 = 148,
+ MX50_PAD_EPDC_SDCE4 = 149,
+ MX50_PAD_EPDC_SDCE5 = 150,
+ MX50_PAD_EIM_DA0 = 151,
+ MX50_PAD_EIM_DA1 = 152,
+ MX50_PAD_EIM_DA2 = 153,
+ MX50_PAD_EIM_DA3 = 154,
+ MX50_PAD_EIM_DA4 = 155,
+ MX50_PAD_EIM_DA5 = 156,
+ MX50_PAD_EIM_DA6 = 157,
+ MX50_PAD_EIM_DA7 = 158,
+ MX50_PAD_EIM_DA8 = 159,
+ MX50_PAD_EIM_DA9 = 160,
+ MX50_PAD_EIM_DA10 = 161,
+ MX50_PAD_EIM_DA11 = 162,
+ MX50_PAD_EIM_DA12 = 163,
+ MX50_PAD_EIM_DA13 = 164,
+ MX50_PAD_EIM_DA14 = 165,
+ MX50_PAD_EIM_DA15 = 166,
+ MX50_PAD_EIM_CS2 = 167,
+ MX50_PAD_EIM_CS1 = 168,
+ MX50_PAD_EIM_CS0 = 169,
+ MX50_PAD_EIM_EB0 = 170,
+ MX50_PAD_EIM_EB1 = 171,
+ MX50_PAD_EIM_WAIT = 172,
+ MX50_PAD_EIM_BCLK = 173,
+ MX50_PAD_EIM_RDY = 174,
+ MX50_PAD_EIM_OE = 175,
+ MX50_PAD_EIM_RW = 176,
+ MX50_PAD_EIM_LBA = 177,
+ MX50_PAD_EIM_CRE = 178,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX50_PAD_RESERVE0),
+ IMX_PINCTRL_PIN(MX50_PAD_RESERVE1),
+ IMX_PINCTRL_PIN(MX50_PAD_RESERVE2),
+ IMX_PINCTRL_PIN(MX50_PAD_RESERVE3),
+ IMX_PINCTRL_PIN(MX50_PAD_RESERVE4),
+ IMX_PINCTRL_PIN(MX50_PAD_RESERVE5),
+ IMX_PINCTRL_PIN(MX50_PAD_RESERVE6),
+ IMX_PINCTRL_PIN(MX50_PAD_RESERVE7),
+ IMX_PINCTRL_PIN(MX50_PAD_KEY_COL0),
+ IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW0),
+ IMX_PINCTRL_PIN(MX50_PAD_KEY_COL1),
+ IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW1),
+ IMX_PINCTRL_PIN(MX50_PAD_KEY_COL2),
+ IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW2),
+ IMX_PINCTRL_PIN(MX50_PAD_KEY_COL3),
+ IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW3),
+ IMX_PINCTRL_PIN(MX50_PAD_I2C1_SCL),
+ IMX_PINCTRL_PIN(MX50_PAD_I2C1_SDA),
+ IMX_PINCTRL_PIN(MX50_PAD_I2C2_SCL),
+ IMX_PINCTRL_PIN(MX50_PAD_I2C2_SDA),
+ IMX_PINCTRL_PIN(MX50_PAD_I2C3_SCL),
+ IMX_PINCTRL_PIN(MX50_PAD_I2C3_SDA),
+ IMX_PINCTRL_PIN(MX50_PAD_PWM1),
+ IMX_PINCTRL_PIN(MX50_PAD_PWM2),
+ IMX_PINCTRL_PIN(MX50_PAD_0WIRE),
+ IMX_PINCTRL_PIN(MX50_PAD_EPITO),
+ IMX_PINCTRL_PIN(MX50_PAD_WDOG),
+ IMX_PINCTRL_PIN(MX50_PAD_SSI_TXFS),
+ IMX_PINCTRL_PIN(MX50_PAD_SSI_TXC),
+ IMX_PINCTRL_PIN(MX50_PAD_SSI_TXD),
+ IMX_PINCTRL_PIN(MX50_PAD_SSI_RXD),
+ IMX_PINCTRL_PIN(MX50_PAD_SSI_RXF),
+ IMX_PINCTRL_PIN(MX50_PAD_SSI_RXC),
+ IMX_PINCTRL_PIN(MX50_PAD_UART1_TXD),
+ IMX_PINCTRL_PIN(MX50_PAD_UART1_RXD),
+ IMX_PINCTRL_PIN(MX50_PAD_UART1_CTS),
+ IMX_PINCTRL_PIN(MX50_PAD_UART1_RTS),
+ IMX_PINCTRL_PIN(MX50_PAD_UART2_TXD),
+ IMX_PINCTRL_PIN(MX50_PAD_UART2_RXD),
+ IMX_PINCTRL_PIN(MX50_PAD_UART2_CTS),
+ IMX_PINCTRL_PIN(MX50_PAD_UART2_RTS),
+ IMX_PINCTRL_PIN(MX50_PAD_UART3_TXD),
+ IMX_PINCTRL_PIN(MX50_PAD_UART3_RXD),
+ IMX_PINCTRL_PIN(MX50_PAD_UART4_TXD),
+ IMX_PINCTRL_PIN(MX50_PAD_UART4_RXD),
+ IMX_PINCTRL_PIN(MX50_PAD_CSPI_CLK),
+ IMX_PINCTRL_PIN(MX50_PAD_CSPI_MOSI),
+ IMX_PINCTRL_PIN(MX50_PAD_CSPI_MISO),
+ IMX_PINCTRL_PIN(MX50_PAD_CSPI_SS0),
+ IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_CLK),
+ IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MOSI),
+ IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MISO),
+ IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_SS0),
+ IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_CLK),
+ IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MOSI),
+ IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MISO),
+ IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_SS0),
+ IMX_PINCTRL_PIN(MX50_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(MX50_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(MX50_PAD_SD1_D0),
+ IMX_PINCTRL_PIN(MX50_PAD_SD1_D1),
+ IMX_PINCTRL_PIN(MX50_PAD_SD1_D2),
+ IMX_PINCTRL_PIN(MX50_PAD_SD1_D3),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_CLK),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_CMD),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_D0),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_D1),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_D2),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_D3),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_D4),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_D5),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_D6),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_D7),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_WP),
+ IMX_PINCTRL_PIN(MX50_PAD_SD2_CD),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D0),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D1),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D2),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D3),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D4),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D5),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D6),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D7),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_WR),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_RD),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_RS),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_CS),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_BUSY),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_RESET),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_CLK),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_CMD),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_D0),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_D1),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_D2),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_D3),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_D4),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_D5),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_D6),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_D7),
+ IMX_PINCTRL_PIN(MX50_PAD_SD3_WP),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D8),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D9),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D10),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D11),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D12),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D13),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D14),
+ IMX_PINCTRL_PIN(MX50_PAD_DISP_D15),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D0),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D1),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D2),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D3),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D4),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D5),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D6),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D7),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D8),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D9),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D10),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D11),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D12),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D13),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D14),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_D15),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDCLK),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDSP),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDOE),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDRL),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLK),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOEZ),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOED),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOE),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDLE),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLKN),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDSHR),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCOM),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRSTAT),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL0),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL1),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL2),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL3),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM0),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM1),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR0),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR1),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE0),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE1),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE2),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE3),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE4),
+ IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE5),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA0),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA1),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA2),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA3),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA4),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA5),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA6),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA7),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA8),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA9),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA10),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA11),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA12),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA13),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA14),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_DA15),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_CS2),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_CS1),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_CS0),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_EB0),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_EB1),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_WAIT),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_BCLK),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_RDY),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_OE),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_RW),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_LBA),
+ IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE),
+};
+
+static struct imx_pinctrl_soc_info imx50_pinctrl_info = {
+ .pins = imx50_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx50_pinctrl_pads),
+};
+
+static struct of_device_id imx50_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx50-iomuxc", },
+ { /* sentinel */ }
+};
+
+static int imx50_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx_pinctrl_probe(pdev, &imx50_pinctrl_info);
+}
+
+static struct platform_driver imx50_pinctrl_driver = {
+ .driver = {
+ .name = "imx50-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(imx50_pinctrl_of_match),
+ },
+ .probe = imx50_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+};
+
+static int __init imx50_pinctrl_init(void)
+{
+ return platform_driver_register(&imx50_pinctrl_driver);
+}
+arch_initcall(imx50_pinctrl_init);
+
+static void __exit imx50_pinctrl_exit(void)
+{
+ platform_driver_unregister(&imx50_pinctrl_driver);
+}
+module_exit(imx50_pinctrl_exit);
+MODULE_DESCRIPTION("Freescale IMX50 pinctrl driver");
+MODULE_LICENSE("GPL v2");
.driver = {
.name = "imx51-pinctrl",
.owner = THIS_MODULE,
- .of_match_table = of_match_ptr(imx51_pinctrl_of_match),
+ .of_match_table = imx51_pinctrl_of_match,
},
.probe = imx51_pinctrl_probe,
.remove = imx_pinctrl_remove,
.driver = {
.name = "imx53-pinctrl",
.owner = THIS_MODULE,
- .of_match_table = of_match_ptr(imx53_pinctrl_of_match),
+ .of_match_table = imx53_pinctrl_of_match,
},
.probe = imx53_pinctrl_probe,
.remove = imx_pinctrl_remove,
.driver = {
.name = "imx6dl-pinctrl",
.owner = THIS_MODULE,
- .of_match_table = of_match_ptr(imx6dl_pinctrl_of_match),
+ .of_match_table = imx6dl_pinctrl_of_match,
},
.probe = imx6dl_pinctrl_probe,
.remove = imx_pinctrl_remove,
.driver = {
.name = "imx6q-pinctrl",
.owner = THIS_MODULE,
- .of_match_table = of_match_ptr(imx6q_pinctrl_of_match),
+ .of_match_table = imx6q_pinctrl_of_match,
},
.probe = imx6q_pinctrl_probe,
.remove = imx_pinctrl_remove,
.driver = {
.name = "imx6sl-pinctrl",
.owner = THIS_MODULE,
- .of_match_table = of_match_ptr(imx6sl_pinctrl_of_match),
+ .of_match_table = imx6sl_pinctrl_of_match,
},
.probe = imx6sl_pinctrl_probe,
.remove = imx_pinctrl_remove,
param = pinconf_to_config_param(configs[i]);
param_val = pinconf_to_config_argument(configs[i]);
- if (param == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
- continue;
-
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
return 0;
}
-static int palmas_pinconf_group_get(struct pinctrl_dev *pctldev,
- unsigned group, unsigned long *config)
-{
- dev_err(pctldev->dev, "palmas_pinconf_group_get op not supported\n");
- return -ENOTSUPP;
-}
-
-static int palmas_pinconf_group_set(struct pinctrl_dev *pctldev,
- unsigned group, unsigned long *configs,
- unsigned num_configs)
-{
- dev_err(pctldev->dev, "palmas_pinconf_group_set op not supported\n");
- return -ENOTSUPP;
-}
-
static const struct pinconf_ops palmas_pinconf_ops = {
.pin_config_get = palmas_pinconf_get,
.pin_config_set = palmas_pinconf_set,
- .pin_config_group_get = palmas_pinconf_group_get,
- .pin_config_group_set = palmas_pinconf_group_set,
};
static struct pinctrl_desc palmas_pinctrl_desc = {
#define GPIO_EXT_PORT 0x50
#define GPIO_LS_SYNC 0x60
+enum rockchip_pinctrl_type {
+ RK2928,
+ RK3066B,
+ RK3188,
+};
+
+enum rockchip_pin_bank_type {
+ COMMON_BANK,
+ RK3188_BANK0,
+};
+
/**
* @reg_base: register base of the gpio bank
+ * @reg_pull: optional separate register for additional pull settings
* @clk: clock of the gpio bank
* @irq: interrupt of the gpio bank
* @pin_base: first pin number
*/
struct rockchip_pin_bank {
void __iomem *reg_base;
+ void __iomem *reg_pull;
struct clk *clk;
int irq;
u32 pin_base;
u8 nr_pins;
char *name;
u8 bank_num;
+ enum rockchip_pin_bank_type bank_type;
bool valid;
struct device_node *of_node;
struct rockchip_pinctrl *drvdata;
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range grange;
spinlock_t slock;
-
+ u32 toggle_edge_mode;
};
#define PIN_BANK(id, pins, label) \
}
/**
- * @pull_auto: some SoCs don't allow pulls to be specified as up or down, but
- * instead decide this automatically based on the pad-type.
*/
struct rockchip_pin_ctrl {
struct rockchip_pin_bank *pin_banks;
u32 nr_banks;
u32 nr_pins;
char *label;
+ enum rockchip_pinctrl_type type;
int mux_offset;
- int pull_offset;
- bool pull_auto;
- int pull_bank_stride;
+ void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num,
+ void __iomem **reg, u8 *bit);
};
struct rockchip_pin_config {
struct rockchip_pinctrl {
void __iomem *reg_base;
+ void __iomem *reg_pull;
struct device *dev;
struct rockchip_pin_ctrl *ctrl;
struct pinctrl_desc pctl;
spin_unlock_irqrestore(&bank->slock, flags);
}
+#define RK2928_PULL_OFFSET 0x118
+#define RK2928_PULL_PINS_PER_REG 16
+#define RK2928_PULL_BANK_STRIDE 8
+
+static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, void __iomem **reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ *reg = info->reg_base + RK2928_PULL_OFFSET;
+ *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
+ *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
+
+ *bit = pin_num % RK2928_PULL_PINS_PER_REG;
+};
+
+#define RK3188_PULL_BITS_PER_PIN 2
+#define RK3188_PULL_PINS_PER_REG 8
+#define RK3188_PULL_BANK_STRIDE 16
+
+static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, void __iomem **reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ /* The first 12 pins of the first bank are located elsewhere */
+ if (bank->bank_type == RK3188_BANK0 && pin_num < 12) {
+ *reg = bank->reg_pull +
+ ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3188_PULL_PINS_PER_REG;
+ *bit *= RK3188_PULL_BITS_PER_PIN;
+ } else {
+ *reg = info->reg_pull - 4;
+ *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+
+ /*
+ * The bits in these registers have an inverse ordering
+ * with the lowest pin being in bits 15:14 and the highest
+ * pin in bits 1:0
+ */
+ *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
+ *bit *= RK3188_PULL_BITS_PER_PIN;
+ }
+}
+
static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
void __iomem *reg;
u8 bit;
+ u32 data;
/* rk3066b does support any pulls */
- if (!ctrl->pull_offset)
+ if (ctrl->type == RK3066B)
return PIN_CONFIG_BIAS_DISABLE;
- reg = info->reg_base + ctrl->pull_offset;
-
- if (ctrl->pull_auto) {
- reg += bank->bank_num * ctrl->pull_bank_stride;
- reg += (pin_num / 16) * 4;
- bit = pin_num % 16;
+ ctrl->pull_calc_reg(bank, pin_num, ®, &bit);
+ switch (ctrl->type) {
+ case RK2928:
return !(readl_relaxed(reg) & BIT(bit))
? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
: PIN_CONFIG_BIAS_DISABLE;
- } else {
- dev_err(info->dev, "pull support for rk31xx not implemented\n");
+ case RK3188:
+ data = readl_relaxed(reg) >> bit;
+ data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
+
+ switch (data) {
+ case 0:
+ return PIN_CONFIG_BIAS_DISABLE;
+ case 1:
+ return PIN_CONFIG_BIAS_PULL_UP;
+ case 2:
+ return PIN_CONFIG_BIAS_PULL_DOWN;
+ case 3:
+ return PIN_CONFIG_BIAS_BUS_HOLD;
+ }
+
+ dev_err(info->dev, "unknown pull setting\n");
return -EIO;
- }
+ default:
+ dev_err(info->dev, "unsupported pinctrl type\n");
+ return -EINVAL;
+ };
}
static int rockchip_set_pull(struct rockchip_pin_bank *bank,
bank->bank_num, pin_num, pull);
/* rk3066b does support any pulls */
- if (!ctrl->pull_offset)
+ if (ctrl->type == RK3066B)
return pull ? -EINVAL : 0;
- reg = info->reg_base + ctrl->pull_offset;
-
- if (ctrl->pull_auto) {
- if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
- pull != PIN_CONFIG_BIAS_DISABLE) {
- dev_err(info->dev, "only PIN_DEFAULT and DISABLE allowed\n");
- return -EINVAL;
- }
-
- reg += bank->bank_num * ctrl->pull_bank_stride;
- reg += (pin_num / 16) * 4;
- bit = pin_num % 16;
+ ctrl->pull_calc_reg(bank, pin_num, ®, &bit);
+ switch (ctrl->type) {
+ case RK2928:
spin_lock_irqsave(&bank->slock, flags);
data = BIT(bit + 16);
writel(data, reg);
spin_unlock_irqrestore(&bank->slock, flags);
- } else {
- if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) {
- dev_err(info->dev, "pull direction (up/down) needs to be specified\n");
+ break;
+ case RK3188:
+ spin_lock_irqsave(&bank->slock, flags);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+
+ switch (pull) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ data |= (1 << bit);
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ data |= (2 << bit);
+ break;
+ case PIN_CONFIG_BIAS_BUS_HOLD:
+ data |= (3 << bit);
+ break;
+ default:
+ dev_err(info->dev, "unsupported pull setting %d\n",
+ pull);
return -EINVAL;
}
- dev_err(info->dev, "pull support for rk31xx not implemented\n");
- return -EIO;
+ writel(data, reg);
+
+ spin_unlock_irqrestore(&bank->slock, flags);
+ break;
+ default:
+ dev_err(info->dev, "unsupported pinctrl type\n");
+ return -EINVAL;
}
return 0;
static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
enum pin_config_param pull)
{
- /* rk3066b does support any pulls */
- if (!ctrl->pull_offset)
+ switch (ctrl->type) {
+ case RK2928:
+ return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
+ pull == PIN_CONFIG_BIAS_DISABLE);
+ case RK3066B:
return pull ? false : true;
-
- if (ctrl->pull_auto) {
- if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
- pull != PIN_CONFIG_BIAS_DISABLE)
- return false;
- } else {
- if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
- return false;
+ case RK3188:
+ return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
}
- return true;
+ return false;
}
/* set the pin config settings for a specified pin */
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
+ case PIN_CONFIG_BIAS_BUS_HOLD:
if (!rockchip_pinconf_pull_valid(info->ctrl, param))
return -ENOTSUPP;
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
+ case PIN_CONFIG_BIAS_BUS_HOLD:
if (!rockchip_pinconf_pull_valid(info->ctrl, param))
return -ENOTSUPP;
.pin_config_set = rockchip_pinconf_set,
};
-static const char *gpio_compat = "rockchip,gpio-bank";
+static const struct of_device_id rockchip_bank_match[] = {
+ { .compatible = "rockchip,gpio-bank" },
+ { .compatible = "rockchip,rk3188-gpio-bank0" },
+ {},
+};
static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
struct device_node *np)
struct device_node *child;
for_each_child_of_node(np, child) {
- if (of_device_is_compatible(child, gpio_compat))
+ if (of_match_node(rockchip_bank_match, child))
continue;
info->nfunctions++;
i = 0;
for_each_child_of_node(np, child) {
- if (of_device_is_compatible(child, gpio_compat))
+ if (of_match_node(rockchip_bank_match, child))
continue;
+
ret = rockchip_pinctrl_parse_functions(child, info, i++);
if (ret) {
dev_err(&pdev->dev, "failed to parse function\n");
{
struct irq_chip *chip = irq_get_chip(irq);
struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
+ u32 polarity = 0, data = 0;
u32 pend;
+ bool edge_changed = false;
dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
+ if (bank->toggle_edge_mode) {
+ polarity = readl_relaxed(bank->reg_base +
+ GPIO_INT_POLARITY);
+ data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
+ }
+
while (pend) {
unsigned int virq;
dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
+ /*
+ * Triggering IRQ on both rising and falling edge
+ * needs manual intervention.
+ */
+ if (bank->toggle_edge_mode & BIT(irq)) {
+ if (data & BIT(irq))
+ polarity &= ~BIT(irq);
+ else
+ polarity |= BIT(irq);
+
+ edge_changed = true;
+ }
+
generic_handle_irq(virq);
}
+ if (bank->toggle_edge_mode && edge_changed) {
+ /* Interrupt params should only be set with ints disabled */
+ data = readl_relaxed(bank->reg_base + GPIO_INTEN);
+ writel_relaxed(0, bank->reg_base + GPIO_INTEN);
+ writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
+ writel(data, bank->reg_base + GPIO_INTEN);
+ }
+
chained_irq_exit(chip, desc);
}
u32 level;
u32 data;
+ /* make sure the pin is configured as gpio input */
+ rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
+ data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
+ data &= ~mask;
+ writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
+
if (type & IRQ_TYPE_EDGE_BOTH)
__irq_set_handler_locked(d->irq, handle_edge_irq);
else
polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
switch (type) {
+ case IRQ_TYPE_EDGE_BOTH:
+ bank->toggle_edge_mode |= mask;
+ level |= mask;
+
+ /*
+ * Determine gpio state. If 1 next interrupt should be falling
+ * otherwise rising.
+ */
+ data = readl(bank->reg_base + GPIO_EXT_PORT);
+ if (data & mask)
+ polarity &= ~mask;
+ else
+ polarity |= mask;
+ break;
case IRQ_TYPE_EDGE_RISING:
+ bank->toggle_edge_mode &= ~mask;
level |= mask;
polarity |= mask;
break;
case IRQ_TYPE_EDGE_FALLING:
+ bank->toggle_edge_mode &= ~mask;
level |= mask;
polarity &= ~mask;
break;
case IRQ_TYPE_LEVEL_HIGH:
+ bank->toggle_edge_mode &= ~mask;
level &= ~mask;
polarity |= mask;
break;
case IRQ_TYPE_LEVEL_LOW:
+ bank->toggle_edge_mode &= ~mask;
level &= ~mask;
polarity &= ~mask;
break;
irq_gc_unlock(gc);
- /* make sure the pin is configured as gpio input */
- rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
- data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
- data &= ~mask;
- writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
-
return 0;
}
if (IS_ERR(bank->reg_base))
return PTR_ERR(bank->reg_base);
+ /*
+ * special case, where parts of the pull setting-registers are
+ * part of the PMU register space
+ */
+ if (of_device_is_compatible(bank->of_node,
+ "rockchip,rk3188-gpio-bank0")) {
+ bank->bank_type = RK3188_BANK0;
+
+ if (of_address_to_resource(bank->of_node, 1, &res)) {
+ dev_err(dev, "cannot find IO resource for bank\n");
+ return -ENOENT;
+ }
+
+ bank->reg_pull = devm_ioremap_resource(dev, &res);
+ if (IS_ERR(bank->reg_pull))
+ return PTR_ERR(bank->reg_pull);
+ } else {
+ bank->bank_type = COMMON_BANK;
+ }
+
bank->irq = irq_of_parse_and_map(bank->of_node, 0);
bank->clk = of_clk_get(bank->of_node, 0);
if (IS_ERR(info->reg_base))
return PTR_ERR(info->reg_base);
+ /* The RK3188 has its pull registers in a separate place */
+ if (ctrl->type == RK3188) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ info->reg_pull = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(info->reg_base))
+ return PTR_ERR(info->reg_base);
+ }
+
ret = rockchip_gpiolib_register(pdev, info);
if (ret)
return ret;
.pin_banks = rk2928_pin_banks,
.nr_banks = ARRAY_SIZE(rk2928_pin_banks),
.label = "RK2928-GPIO",
+ .type = RK2928,
.mux_offset = 0xa8,
- .pull_offset = 0x118,
- .pull_auto = 1,
- .pull_bank_stride = 8,
+ .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
};
static struct rockchip_pin_bank rk3066a_pin_banks[] = {
.pin_banks = rk3066a_pin_banks,
.nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
.label = "RK3066a-GPIO",
+ .type = RK2928,
.mux_offset = 0xa8,
- .pull_offset = 0x118,
- .pull_auto = 1,
- .pull_bank_stride = 8,
+ .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
};
static struct rockchip_pin_bank rk3066b_pin_banks[] = {
.pin_banks = rk3066b_pin_banks,
.nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
.label = "RK3066b-GPIO",
+ .type = RK3066B,
.mux_offset = 0x60,
- .pull_offset = -EINVAL,
};
static struct rockchip_pin_bank rk3188_pin_banks[] = {
.pin_banks = rk3188_pin_banks,
.nr_banks = ARRAY_SIZE(rk3188_pin_banks),
.label = "RK3188-GPIO",
+ .type = RK3188,
.mux_offset = 0x68,
- .pull_offset = 0x164,
- .pull_bank_stride = 16,
+ .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
};
static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.driver = {
.name = "samsung-pinctrl",
.owner = THIS_MODULE,
- .of_match_table = of_match_ptr(samsung_pinctrl_dt_match),
+ .of_match_table = samsung_pinctrl_dt_match,
},
};
--- /dev/null
+/*
+ * Abilis Systems TB10x pin control driver
+ *
+ * Copyright (C) Abilis Systems 2012
+ *
+ * Author: Christian Ruppert <christian.ruppert@abilis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/stringify.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+
+#include "pinctrl-utils.h"
+
+#define TB10X_PORT1 (0)
+#define TB10X_PORT2 (16)
+#define TB10X_PORT3 (32)
+#define TB10X_PORT4 (48)
+#define TB10X_PORT5 (128)
+#define TB10X_PORT6 (64)
+#define TB10X_PORT7 (80)
+#define TB10X_PORT8 (96)
+#define TB10X_PORT9 (112)
+#define TB10X_GPIOS (256)
+
+#define PCFG_PORT_BITWIDTH (2)
+#define PCFG_PORT_MASK(PORT) \
+ (((1 << PCFG_PORT_BITWIDTH) - 1) << (PCFG_PORT_BITWIDTH * (PORT)))
+
+static const struct pinctrl_pin_desc tb10x_pins[] = {
+ /* Port 1 */
+ PINCTRL_PIN(TB10X_PORT1 + 0, "MICLK_S0"),
+ PINCTRL_PIN(TB10X_PORT1 + 1, "MISTRT_S0"),
+ PINCTRL_PIN(TB10X_PORT1 + 2, "MIVAL_S0"),
+ PINCTRL_PIN(TB10X_PORT1 + 3, "MDI_S0"),
+ PINCTRL_PIN(TB10X_PORT1 + 4, "GPIOA0"),
+ PINCTRL_PIN(TB10X_PORT1 + 5, "GPIOA1"),
+ PINCTRL_PIN(TB10X_PORT1 + 6, "GPIOA2"),
+ PINCTRL_PIN(TB10X_PORT1 + 7, "MDI_S1"),
+ PINCTRL_PIN(TB10X_PORT1 + 8, "MIVAL_S1"),
+ PINCTRL_PIN(TB10X_PORT1 + 9, "MISTRT_S1"),
+ PINCTRL_PIN(TB10X_PORT1 + 10, "MICLK_S1"),
+ /* Port 2 */
+ PINCTRL_PIN(TB10X_PORT2 + 0, "MICLK_S2"),
+ PINCTRL_PIN(TB10X_PORT2 + 1, "MISTRT_S2"),
+ PINCTRL_PIN(TB10X_PORT2 + 2, "MIVAL_S2"),
+ PINCTRL_PIN(TB10X_PORT2 + 3, "MDI_S2"),
+ PINCTRL_PIN(TB10X_PORT2 + 4, "GPIOC0"),
+ PINCTRL_PIN(TB10X_PORT2 + 5, "GPIOC1"),
+ PINCTRL_PIN(TB10X_PORT2 + 6, "GPIOC2"),
+ PINCTRL_PIN(TB10X_PORT2 + 7, "MDI_S3"),
+ PINCTRL_PIN(TB10X_PORT2 + 8, "MIVAL_S3"),
+ PINCTRL_PIN(TB10X_PORT2 + 9, "MISTRT_S3"),
+ PINCTRL_PIN(TB10X_PORT2 + 10, "MICLK_S3"),
+ /* Port 3 */
+ PINCTRL_PIN(TB10X_PORT3 + 0, "MICLK_S4"),
+ PINCTRL_PIN(TB10X_PORT3 + 1, "MISTRT_S4"),
+ PINCTRL_PIN(TB10X_PORT3 + 2, "MIVAL_S4"),
+ PINCTRL_PIN(TB10X_PORT3 + 3, "MDI_S4"),
+ PINCTRL_PIN(TB10X_PORT3 + 4, "GPIOE0"),
+ PINCTRL_PIN(TB10X_PORT3 + 5, "GPIOE1"),
+ PINCTRL_PIN(TB10X_PORT3 + 6, "GPIOE2"),
+ PINCTRL_PIN(TB10X_PORT3 + 7, "MDI_S5"),
+ PINCTRL_PIN(TB10X_PORT3 + 8, "MIVAL_S5"),
+ PINCTRL_PIN(TB10X_PORT3 + 9, "MISTRT_S5"),
+ PINCTRL_PIN(TB10X_PORT3 + 10, "MICLK_S5"),
+ /* Port 4 */
+ PINCTRL_PIN(TB10X_PORT4 + 0, "MICLK_S6"),
+ PINCTRL_PIN(TB10X_PORT4 + 1, "MISTRT_S6"),
+ PINCTRL_PIN(TB10X_PORT4 + 2, "MIVAL_S6"),
+ PINCTRL_PIN(TB10X_PORT4 + 3, "MDI_S6"),
+ PINCTRL_PIN(TB10X_PORT4 + 4, "GPIOG0"),
+ PINCTRL_PIN(TB10X_PORT4 + 5, "GPIOG1"),
+ PINCTRL_PIN(TB10X_PORT4 + 6, "GPIOG2"),
+ PINCTRL_PIN(TB10X_PORT4 + 7, "MDI_S7"),
+ PINCTRL_PIN(TB10X_PORT4 + 8, "MIVAL_S7"),
+ PINCTRL_PIN(TB10X_PORT4 + 9, "MISTRT_S7"),
+ PINCTRL_PIN(TB10X_PORT4 + 10, "MICLK_S7"),
+ /* Port 5 */
+ PINCTRL_PIN(TB10X_PORT5 + 0, "PC_CE1N"),
+ PINCTRL_PIN(TB10X_PORT5 + 1, "PC_CE2N"),
+ PINCTRL_PIN(TB10X_PORT5 + 2, "PC_REGN"),
+ PINCTRL_PIN(TB10X_PORT5 + 3, "PC_INPACKN"),
+ PINCTRL_PIN(TB10X_PORT5 + 4, "PC_OEN"),
+ PINCTRL_PIN(TB10X_PORT5 + 5, "PC_WEN"),
+ PINCTRL_PIN(TB10X_PORT5 + 6, "PC_IORDN"),
+ PINCTRL_PIN(TB10X_PORT5 + 7, "PC_IOWRN"),
+ PINCTRL_PIN(TB10X_PORT5 + 8, "PC_RDYIRQN"),
+ PINCTRL_PIN(TB10X_PORT5 + 9, "PC_WAITN"),
+ PINCTRL_PIN(TB10X_PORT5 + 10, "PC_A0"),
+ PINCTRL_PIN(TB10X_PORT5 + 11, "PC_A1"),
+ PINCTRL_PIN(TB10X_PORT5 + 12, "PC_A2"),
+ PINCTRL_PIN(TB10X_PORT5 + 13, "PC_A3"),
+ PINCTRL_PIN(TB10X_PORT5 + 14, "PC_A4"),
+ PINCTRL_PIN(TB10X_PORT5 + 15, "PC_A5"),
+ PINCTRL_PIN(TB10X_PORT5 + 16, "PC_A6"),
+ PINCTRL_PIN(TB10X_PORT5 + 17, "PC_A7"),
+ PINCTRL_PIN(TB10X_PORT5 + 18, "PC_A8"),
+ PINCTRL_PIN(TB10X_PORT5 + 19, "PC_A9"),
+ PINCTRL_PIN(TB10X_PORT5 + 20, "PC_A10"),
+ PINCTRL_PIN(TB10X_PORT5 + 21, "PC_A11"),
+ PINCTRL_PIN(TB10X_PORT5 + 22, "PC_A12"),
+ PINCTRL_PIN(TB10X_PORT5 + 23, "PC_A13"),
+ PINCTRL_PIN(TB10X_PORT5 + 24, "PC_A14"),
+ PINCTRL_PIN(TB10X_PORT5 + 25, "PC_D0"),
+ PINCTRL_PIN(TB10X_PORT5 + 26, "PC_D1"),
+ PINCTRL_PIN(TB10X_PORT5 + 27, "PC_D2"),
+ PINCTRL_PIN(TB10X_PORT5 + 28, "PC_D3"),
+ PINCTRL_PIN(TB10X_PORT5 + 29, "PC_D4"),
+ PINCTRL_PIN(TB10X_PORT5 + 30, "PC_D5"),
+ PINCTRL_PIN(TB10X_PORT5 + 31, "PC_D6"),
+ PINCTRL_PIN(TB10X_PORT5 + 32, "PC_D7"),
+ PINCTRL_PIN(TB10X_PORT5 + 33, "PC_MOSTRT"),
+ PINCTRL_PIN(TB10X_PORT5 + 34, "PC_MOVAL"),
+ PINCTRL_PIN(TB10X_PORT5 + 35, "PC_MDO0"),
+ PINCTRL_PIN(TB10X_PORT5 + 36, "PC_MDO1"),
+ PINCTRL_PIN(TB10X_PORT5 + 37, "PC_MDO2"),
+ PINCTRL_PIN(TB10X_PORT5 + 38, "PC_MDO3"),
+ PINCTRL_PIN(TB10X_PORT5 + 39, "PC_MDO4"),
+ PINCTRL_PIN(TB10X_PORT5 + 40, "PC_MDO5"),
+ PINCTRL_PIN(TB10X_PORT5 + 41, "PC_MDO6"),
+ PINCTRL_PIN(TB10X_PORT5 + 42, "PC_MDO7"),
+ PINCTRL_PIN(TB10X_PORT5 + 43, "PC_MISTRT"),
+ PINCTRL_PIN(TB10X_PORT5 + 44, "PC_MIVAL"),
+ PINCTRL_PIN(TB10X_PORT5 + 45, "PC_MDI0"),
+ PINCTRL_PIN(TB10X_PORT5 + 46, "PC_MDI1"),
+ PINCTRL_PIN(TB10X_PORT5 + 47, "PC_MDI2"),
+ PINCTRL_PIN(TB10X_PORT5 + 48, "PC_MDI3"),
+ PINCTRL_PIN(TB10X_PORT5 + 49, "PC_MDI4"),
+ PINCTRL_PIN(TB10X_PORT5 + 50, "PC_MDI5"),
+ PINCTRL_PIN(TB10X_PORT5 + 51, "PC_MDI6"),
+ PINCTRL_PIN(TB10X_PORT5 + 52, "PC_MDI7"),
+ PINCTRL_PIN(TB10X_PORT5 + 53, "PC_MICLK"),
+ /* Port 6 */
+ PINCTRL_PIN(TB10X_PORT6 + 0, "T_MOSTRT_S0"),
+ PINCTRL_PIN(TB10X_PORT6 + 1, "T_MOVAL_S0"),
+ PINCTRL_PIN(TB10X_PORT6 + 2, "T_MDO_S0"),
+ PINCTRL_PIN(TB10X_PORT6 + 3, "T_MOSTRT_S1"),
+ PINCTRL_PIN(TB10X_PORT6 + 4, "T_MOVAL_S1"),
+ PINCTRL_PIN(TB10X_PORT6 + 5, "T_MDO_S1"),
+ PINCTRL_PIN(TB10X_PORT6 + 6, "T_MOSTRT_S2"),
+ PINCTRL_PIN(TB10X_PORT6 + 7, "T_MOVAL_S2"),
+ PINCTRL_PIN(TB10X_PORT6 + 8, "T_MDO_S2"),
+ PINCTRL_PIN(TB10X_PORT6 + 9, "T_MOSTRT_S3"),
+ /* Port 7 */
+ PINCTRL_PIN(TB10X_PORT7 + 0, "UART0_TXD"),
+ PINCTRL_PIN(TB10X_PORT7 + 1, "UART0_RXD"),
+ PINCTRL_PIN(TB10X_PORT7 + 2, "UART0_CTS"),
+ PINCTRL_PIN(TB10X_PORT7 + 3, "UART0_RTS"),
+ PINCTRL_PIN(TB10X_PORT7 + 4, "UART1_TXD"),
+ PINCTRL_PIN(TB10X_PORT7 + 5, "UART1_RXD"),
+ PINCTRL_PIN(TB10X_PORT7 + 6, "UART1_CTS"),
+ PINCTRL_PIN(TB10X_PORT7 + 7, "UART1_RTS"),
+ /* Port 8 */
+ PINCTRL_PIN(TB10X_PORT8 + 0, "SPI3_CLK"),
+ PINCTRL_PIN(TB10X_PORT8 + 1, "SPI3_MISO"),
+ PINCTRL_PIN(TB10X_PORT8 + 2, "SPI3_MOSI"),
+ PINCTRL_PIN(TB10X_PORT8 + 3, "SPI3_SSN"),
+ /* Port 9 */
+ PINCTRL_PIN(TB10X_PORT9 + 0, "SPI1_CLK"),
+ PINCTRL_PIN(TB10X_PORT9 + 1, "SPI1_MISO"),
+ PINCTRL_PIN(TB10X_PORT9 + 2, "SPI1_MOSI"),
+ PINCTRL_PIN(TB10X_PORT9 + 3, "SPI1_SSN0"),
+ PINCTRL_PIN(TB10X_PORT9 + 4, "SPI1_SSN1"),
+ /* Unmuxed GPIOs */
+ PINCTRL_PIN(TB10X_GPIOS + 0, "GPIOB0"),
+ PINCTRL_PIN(TB10X_GPIOS + 1, "GPIOB1"),
+
+ PINCTRL_PIN(TB10X_GPIOS + 2, "GPIOD0"),
+ PINCTRL_PIN(TB10X_GPIOS + 3, "GPIOD1"),
+
+ PINCTRL_PIN(TB10X_GPIOS + 4, "GPIOF0"),
+ PINCTRL_PIN(TB10X_GPIOS + 5, "GPIOF1"),
+
+ PINCTRL_PIN(TB10X_GPIOS + 6, "GPIOH0"),
+ PINCTRL_PIN(TB10X_GPIOS + 7, "GPIOH1"),
+
+ PINCTRL_PIN(TB10X_GPIOS + 8, "GPIOI0"),
+ PINCTRL_PIN(TB10X_GPIOS + 9, "GPIOI1"),
+ PINCTRL_PIN(TB10X_GPIOS + 10, "GPIOI2"),
+ PINCTRL_PIN(TB10X_GPIOS + 11, "GPIOI3"),
+ PINCTRL_PIN(TB10X_GPIOS + 12, "GPIOI4"),
+ PINCTRL_PIN(TB10X_GPIOS + 13, "GPIOI5"),
+ PINCTRL_PIN(TB10X_GPIOS + 14, "GPIOI6"),
+ PINCTRL_PIN(TB10X_GPIOS + 15, "GPIOI7"),
+ PINCTRL_PIN(TB10X_GPIOS + 16, "GPIOI8"),
+ PINCTRL_PIN(TB10X_GPIOS + 17, "GPIOI9"),
+ PINCTRL_PIN(TB10X_GPIOS + 18, "GPIOI10"),
+ PINCTRL_PIN(TB10X_GPIOS + 19, "GPIOI11"),
+
+ PINCTRL_PIN(TB10X_GPIOS + 20, "GPION0"),
+ PINCTRL_PIN(TB10X_GPIOS + 21, "GPION1"),
+ PINCTRL_PIN(TB10X_GPIOS + 22, "GPION2"),
+ PINCTRL_PIN(TB10X_GPIOS + 23, "GPION3"),
+#define MAX_PIN (TB10X_GPIOS + 24)
+ PINCTRL_PIN(MAX_PIN, "GPION4"),
+};
+
+
+/* Port 1 */
+static const unsigned mis0_pins[] = { TB10X_PORT1 + 0, TB10X_PORT1 + 1,
+ TB10X_PORT1 + 2, TB10X_PORT1 + 3};
+static const unsigned gpioa_pins[] = { TB10X_PORT1 + 4, TB10X_PORT1 + 5,
+ TB10X_PORT1 + 6};
+static const unsigned mis1_pins[] = { TB10X_PORT1 + 7, TB10X_PORT1 + 8,
+ TB10X_PORT1 + 9, TB10X_PORT1 + 10};
+static const unsigned mip1_pins[] = { TB10X_PORT1 + 0, TB10X_PORT1 + 1,
+ TB10X_PORT1 + 2, TB10X_PORT1 + 3,
+ TB10X_PORT1 + 4, TB10X_PORT1 + 5,
+ TB10X_PORT1 + 6, TB10X_PORT1 + 7,
+ TB10X_PORT1 + 8, TB10X_PORT1 + 9,
+ TB10X_PORT1 + 10};
+
+/* Port 2 */
+static const unsigned mis2_pins[] = { TB10X_PORT2 + 0, TB10X_PORT2 + 1,
+ TB10X_PORT2 + 2, TB10X_PORT2 + 3};
+static const unsigned gpioc_pins[] = { TB10X_PORT2 + 4, TB10X_PORT2 + 5,
+ TB10X_PORT2 + 6};
+static const unsigned mis3_pins[] = { TB10X_PORT2 + 7, TB10X_PORT2 + 8,
+ TB10X_PORT2 + 9, TB10X_PORT2 + 10};
+static const unsigned mip3_pins[] = { TB10X_PORT2 + 0, TB10X_PORT2 + 1,
+ TB10X_PORT2 + 2, TB10X_PORT2 + 3,
+ TB10X_PORT2 + 4, TB10X_PORT2 + 5,
+ TB10X_PORT2 + 6, TB10X_PORT2 + 7,
+ TB10X_PORT2 + 8, TB10X_PORT2 + 9,
+ TB10X_PORT2 + 10};
+
+/* Port 3 */
+static const unsigned mis4_pins[] = { TB10X_PORT3 + 0, TB10X_PORT3 + 1,
+ TB10X_PORT3 + 2, TB10X_PORT3 + 3};
+static const unsigned gpioe_pins[] = { TB10X_PORT3 + 4, TB10X_PORT3 + 5,
+ TB10X_PORT3 + 6};
+static const unsigned mis5_pins[] = { TB10X_PORT3 + 7, TB10X_PORT3 + 8,
+ TB10X_PORT3 + 9, TB10X_PORT3 + 10};
+static const unsigned mip5_pins[] = { TB10X_PORT3 + 0, TB10X_PORT3 + 1,
+ TB10X_PORT3 + 2, TB10X_PORT3 + 3,
+ TB10X_PORT3 + 4, TB10X_PORT3 + 5,
+ TB10X_PORT3 + 6, TB10X_PORT3 + 7,
+ TB10X_PORT3 + 8, TB10X_PORT3 + 9,
+ TB10X_PORT3 + 10};
+
+/* Port 4 */
+static const unsigned mis6_pins[] = { TB10X_PORT4 + 0, TB10X_PORT4 + 1,
+ TB10X_PORT4 + 2, TB10X_PORT4 + 3};
+static const unsigned gpiog_pins[] = { TB10X_PORT4 + 4, TB10X_PORT4 + 5,
+ TB10X_PORT4 + 6};
+static const unsigned mis7_pins[] = { TB10X_PORT4 + 7, TB10X_PORT4 + 8,
+ TB10X_PORT4 + 9, TB10X_PORT4 + 10};
+static const unsigned mip7_pins[] = { TB10X_PORT4 + 0, TB10X_PORT4 + 1,
+ TB10X_PORT4 + 2, TB10X_PORT4 + 3,
+ TB10X_PORT4 + 4, TB10X_PORT4 + 5,
+ TB10X_PORT4 + 6, TB10X_PORT4 + 7,
+ TB10X_PORT4 + 8, TB10X_PORT4 + 9,
+ TB10X_PORT4 + 10};
+
+/* Port 6 */
+static const unsigned mop_pins[] = { TB10X_PORT6 + 0, TB10X_PORT6 + 1,
+ TB10X_PORT6 + 2, TB10X_PORT6 + 3,
+ TB10X_PORT6 + 4, TB10X_PORT6 + 5,
+ TB10X_PORT6 + 6, TB10X_PORT6 + 7,
+ TB10X_PORT6 + 8, TB10X_PORT6 + 9};
+static const unsigned mos0_pins[] = { TB10X_PORT6 + 0, TB10X_PORT6 + 1,
+ TB10X_PORT6 + 2};
+static const unsigned mos1_pins[] = { TB10X_PORT6 + 3, TB10X_PORT6 + 4,
+ TB10X_PORT6 + 5};
+static const unsigned mos2_pins[] = { TB10X_PORT6 + 6, TB10X_PORT6 + 7,
+ TB10X_PORT6 + 8};
+static const unsigned mos3_pins[] = { TB10X_PORT6 + 9};
+
+/* Port 7 */
+static const unsigned uart0_pins[] = { TB10X_PORT7 + 0, TB10X_PORT7 + 1,
+ TB10X_PORT7 + 2, TB10X_PORT7 + 3};
+static const unsigned uart1_pins[] = { TB10X_PORT7 + 4, TB10X_PORT7 + 5,
+ TB10X_PORT7 + 6, TB10X_PORT7 + 7};
+static const unsigned gpiol_pins[] = { TB10X_PORT7 + 0, TB10X_PORT7 + 1,
+ TB10X_PORT7 + 2, TB10X_PORT7 + 3};
+static const unsigned gpiom_pins[] = { TB10X_PORT7 + 4, TB10X_PORT7 + 5,
+ TB10X_PORT7 + 6, TB10X_PORT7 + 7};
+
+/* Port 8 */
+static const unsigned spi3_pins[] = { TB10X_PORT8 + 0, TB10X_PORT8 + 1,
+ TB10X_PORT8 + 2, TB10X_PORT8 + 3};
+static const unsigned jtag_pins[] = { TB10X_PORT8 + 0, TB10X_PORT8 + 1,
+ TB10X_PORT8 + 2, TB10X_PORT8 + 3};
+
+/* Port 9 */
+static const unsigned spi1_pins[] = { TB10X_PORT9 + 0, TB10X_PORT9 + 1,
+ TB10X_PORT9 + 2, TB10X_PORT9 + 3,
+ TB10X_PORT9 + 4};
+static const unsigned gpion_pins[] = { TB10X_PORT9 + 0, TB10X_PORT9 + 1,
+ TB10X_PORT9 + 2, TB10X_PORT9 + 3,
+ TB10X_PORT9 + 4};
+
+/* Port 5 */
+static const unsigned gpioj_pins[] = { TB10X_PORT5 + 0, TB10X_PORT5 + 1,
+ TB10X_PORT5 + 2, TB10X_PORT5 + 3,
+ TB10X_PORT5 + 4, TB10X_PORT5 + 5,
+ TB10X_PORT5 + 6, TB10X_PORT5 + 7,
+ TB10X_PORT5 + 8, TB10X_PORT5 + 9,
+ TB10X_PORT5 + 10, TB10X_PORT5 + 11,
+ TB10X_PORT5 + 12, TB10X_PORT5 + 13,
+ TB10X_PORT5 + 14, TB10X_PORT5 + 15,
+ TB10X_PORT5 + 16, TB10X_PORT5 + 17,
+ TB10X_PORT5 + 18, TB10X_PORT5 + 19,
+ TB10X_PORT5 + 20, TB10X_PORT5 + 21,
+ TB10X_PORT5 + 22, TB10X_PORT5 + 23,
+ TB10X_PORT5 + 24, TB10X_PORT5 + 25,
+ TB10X_PORT5 + 26, TB10X_PORT5 + 27,
+ TB10X_PORT5 + 28, TB10X_PORT5 + 29,
+ TB10X_PORT5 + 30, TB10X_PORT5 + 31};
+static const unsigned gpiok_pins[] = { TB10X_PORT5 + 32, TB10X_PORT5 + 33,
+ TB10X_PORT5 + 34, TB10X_PORT5 + 35,
+ TB10X_PORT5 + 36, TB10X_PORT5 + 37,
+ TB10X_PORT5 + 38, TB10X_PORT5 + 39,
+ TB10X_PORT5 + 40, TB10X_PORT5 + 41,
+ TB10X_PORT5 + 42, TB10X_PORT5 + 43,
+ TB10X_PORT5 + 44, TB10X_PORT5 + 45,
+ TB10X_PORT5 + 46, TB10X_PORT5 + 47,
+ TB10X_PORT5 + 48, TB10X_PORT5 + 49,
+ TB10X_PORT5 + 50, TB10X_PORT5 + 51,
+ TB10X_PORT5 + 52, TB10X_PORT5 + 53};
+static const unsigned ciplus_pins[] = { TB10X_PORT5 + 0, TB10X_PORT5 + 1,
+ TB10X_PORT5 + 2, TB10X_PORT5 + 3,
+ TB10X_PORT5 + 4, TB10X_PORT5 + 5,
+ TB10X_PORT5 + 6, TB10X_PORT5 + 7,
+ TB10X_PORT5 + 8, TB10X_PORT5 + 9,
+ TB10X_PORT5 + 10, TB10X_PORT5 + 11,
+ TB10X_PORT5 + 12, TB10X_PORT5 + 13,
+ TB10X_PORT5 + 14, TB10X_PORT5 + 15,
+ TB10X_PORT5 + 16, TB10X_PORT5 + 17,
+ TB10X_PORT5 + 18, TB10X_PORT5 + 19,
+ TB10X_PORT5 + 20, TB10X_PORT5 + 21,
+ TB10X_PORT5 + 22, TB10X_PORT5 + 23,
+ TB10X_PORT5 + 24, TB10X_PORT5 + 25,
+ TB10X_PORT5 + 26, TB10X_PORT5 + 27,
+ TB10X_PORT5 + 28, TB10X_PORT5 + 29,
+ TB10X_PORT5 + 30, TB10X_PORT5 + 31,
+ TB10X_PORT5 + 32, TB10X_PORT5 + 33,
+ TB10X_PORT5 + 34, TB10X_PORT5 + 35,
+ TB10X_PORT5 + 36, TB10X_PORT5 + 37,
+ TB10X_PORT5 + 38, TB10X_PORT5 + 39,
+ TB10X_PORT5 + 40, TB10X_PORT5 + 41,
+ TB10X_PORT5 + 42, TB10X_PORT5 + 43,
+ TB10X_PORT5 + 44, TB10X_PORT5 + 45,
+ TB10X_PORT5 + 46, TB10X_PORT5 + 47,
+ TB10X_PORT5 + 48, TB10X_PORT5 + 49,
+ TB10X_PORT5 + 50, TB10X_PORT5 + 51,
+ TB10X_PORT5 + 52, TB10X_PORT5 + 53};
+static const unsigned mcard_pins[] = { TB10X_PORT5 + 3, TB10X_PORT5 + 10,
+ TB10X_PORT5 + 11, TB10X_PORT5 + 12,
+ TB10X_PORT5 + 22, TB10X_PORT5 + 23,
+ TB10X_PORT5 + 33, TB10X_PORT5 + 35,
+ TB10X_PORT5 + 36, TB10X_PORT5 + 37,
+ TB10X_PORT5 + 38, TB10X_PORT5 + 39,
+ TB10X_PORT5 + 40, TB10X_PORT5 + 41,
+ TB10X_PORT5 + 42, TB10X_PORT5 + 43,
+ TB10X_PORT5 + 45, TB10X_PORT5 + 46,
+ TB10X_PORT5 + 47, TB10X_PORT5 + 48,
+ TB10X_PORT5 + 49, TB10X_PORT5 + 50,
+ TB10X_PORT5 + 51, TB10X_PORT5 + 52,
+ TB10X_PORT5 + 53};
+static const unsigned stc0_pins[] = { TB10X_PORT5 + 34, TB10X_PORT5 + 35,
+ TB10X_PORT5 + 36, TB10X_PORT5 + 37,
+ TB10X_PORT5 + 38, TB10X_PORT5 + 39,
+ TB10X_PORT5 + 40};
+static const unsigned stc1_pins[] = { TB10X_PORT5 + 25, TB10X_PORT5 + 26,
+ TB10X_PORT5 + 27, TB10X_PORT5 + 28,
+ TB10X_PORT5 + 29, TB10X_PORT5 + 30,
+ TB10X_PORT5 + 44};
+
+/* Unmuxed GPIOs */
+static const unsigned gpiob_pins[] = { TB10X_GPIOS + 0, TB10X_GPIOS + 1};
+static const unsigned gpiod_pins[] = { TB10X_GPIOS + 2, TB10X_GPIOS + 3};
+static const unsigned gpiof_pins[] = { TB10X_GPIOS + 4, TB10X_GPIOS + 5};
+static const unsigned gpioh_pins[] = { TB10X_GPIOS + 6, TB10X_GPIOS + 7};
+static const unsigned gpioi_pins[] = { TB10X_GPIOS + 8, TB10X_GPIOS + 9,
+ TB10X_GPIOS + 10, TB10X_GPIOS + 11,
+ TB10X_GPIOS + 12, TB10X_GPIOS + 13,
+ TB10X_GPIOS + 14, TB10X_GPIOS + 15,
+ TB10X_GPIOS + 16, TB10X_GPIOS + 17,
+ TB10X_GPIOS + 18, TB10X_GPIOS + 19};
+
+struct tb10x_pinfuncgrp {
+ const char *name;
+ const unsigned int *pins;
+ const unsigned int pincnt;
+ const int port;
+ const unsigned int mode;
+ const int isgpio;
+};
+#define DEFPINFUNCGRP(NAME, PORT, MODE, ISGPIO) { \
+ .name = __stringify(NAME), \
+ .pins = NAME##_pins, .pincnt = ARRAY_SIZE(NAME##_pins), \
+ .port = (PORT), .mode = (MODE), \
+ .isgpio = (ISGPIO), \
+ }
+static const struct tb10x_pinfuncgrp tb10x_pingroups[] = {
+ DEFPINFUNCGRP(mis0, 0, 0, 0),
+ DEFPINFUNCGRP(gpioa, 0, 0, 1),
+ DEFPINFUNCGRP(mis1, 0, 0, 0),
+ DEFPINFUNCGRP(mip1, 0, 1, 0),
+ DEFPINFUNCGRP(mis2, 1, 0, 0),
+ DEFPINFUNCGRP(gpioc, 1, 0, 1),
+ DEFPINFUNCGRP(mis3, 1, 0, 0),
+ DEFPINFUNCGRP(mip3, 1, 1, 0),
+ DEFPINFUNCGRP(mis4, 2, 0, 0),
+ DEFPINFUNCGRP(gpioe, 2, 0, 1),
+ DEFPINFUNCGRP(mis5, 2, 0, 0),
+ DEFPINFUNCGRP(mip5, 2, 1, 0),
+ DEFPINFUNCGRP(mis6, 3, 0, 0),
+ DEFPINFUNCGRP(gpiog, 3, 0, 1),
+ DEFPINFUNCGRP(mis7, 3, 0, 0),
+ DEFPINFUNCGRP(mip7, 3, 1, 0),
+ DEFPINFUNCGRP(gpioj, 4, 0, 1),
+ DEFPINFUNCGRP(gpiok, 4, 0, 1),
+ DEFPINFUNCGRP(ciplus, 4, 1, 0),
+ DEFPINFUNCGRP(mcard, 4, 2, 0),
+ DEFPINFUNCGRP(stc0, 4, 3, 0),
+ DEFPINFUNCGRP(stc1, 4, 3, 0),
+ DEFPINFUNCGRP(mop, 5, 0, 0),
+ DEFPINFUNCGRP(mos0, 5, 1, 0),
+ DEFPINFUNCGRP(mos1, 5, 1, 0),
+ DEFPINFUNCGRP(mos2, 5, 1, 0),
+ DEFPINFUNCGRP(mos3, 5, 1, 0),
+ DEFPINFUNCGRP(uart0, 6, 0, 0),
+ DEFPINFUNCGRP(uart1, 6, 0, 0),
+ DEFPINFUNCGRP(gpiol, 6, 1, 1),
+ DEFPINFUNCGRP(gpiom, 6, 1, 1),
+ DEFPINFUNCGRP(spi3, 7, 0, 0),
+ DEFPINFUNCGRP(jtag, 7, 1, 0),
+ DEFPINFUNCGRP(spi1, 8, 0, 0),
+ DEFPINFUNCGRP(gpion, 8, 1, 1),
+ DEFPINFUNCGRP(gpiob, -1, 0, 1),
+ DEFPINFUNCGRP(gpiod, -1, 0, 1),
+ DEFPINFUNCGRP(gpiof, -1, 0, 1),
+ DEFPINFUNCGRP(gpioh, -1, 0, 1),
+ DEFPINFUNCGRP(gpioi, -1, 0, 1),
+};
+#undef DEFPINFUNCGRP
+
+struct tb10x_of_pinfunc {
+ const char *name;
+ const char *group;
+};
+
+#define TB10X_PORTS (9)
+
+/**
+ * struct tb10x_port - state of an I/O port
+ * @mode: Node this port is currently in.
+ * @count: Number of enabled functions which require this port to be
+ * configured in @mode.
+ */
+struct tb10x_port {
+ unsigned int mode;
+ unsigned int count;
+};
+
+/**
+ * struct tb10x_pinctrl - TB10x pin controller internal state
+ * @pctl: pointer to the pinctrl_dev structure of this pin controller.
+ * @base: register set base address.
+ * @pingroups: pointer to an array of the pin groups this driver manages.
+ * @pinfuncgrpcnt: number of pingroups in @pingroups.
+ * @pinfuncs: pointer to an array of pin functions this driver manages.
+ * @pinfuncnt: number of pin functions in @pinfuncs.
+ * @mutex: mutex for exclusive access to a pin controller's state.
+ * @ports: current state of each port.
+ * @gpios: Indicates if a given pin is currently used as GPIO (1) or not (0).
+ */
+struct tb10x_pinctrl {
+ struct pinctrl_dev *pctl;
+ void *base;
+ const struct tb10x_pinfuncgrp *pingroups;
+ unsigned int pinfuncgrpcnt;
+ struct tb10x_of_pinfunc *pinfuncs;
+ unsigned int pinfuncnt;
+ struct mutex mutex;
+ struct tb10x_port ports[TB10X_PORTS];
+ DECLARE_BITMAP(gpios, MAX_PIN + 1);
+};
+
+static inline void tb10x_pinctrl_set_config(struct tb10x_pinctrl *state,
+ unsigned int port, unsigned int mode)
+{
+ u32 pcfg;
+
+ if (state->ports[port].count)
+ return;
+
+ state->ports[port].mode = mode;
+
+ pcfg = ioread32(state->base) & ~(PCFG_PORT_MASK(port));
+ pcfg |= (mode << (PCFG_PORT_BITWIDTH * port)) & PCFG_PORT_MASK(port);
+ iowrite32(pcfg, state->base);
+}
+
+static inline unsigned int tb10x_pinctrl_get_config(
+ struct tb10x_pinctrl *state,
+ unsigned int port)
+{
+ return (ioread32(state->base) & PCFG_PORT_MASK(port))
+ >> (PCFG_PORT_BITWIDTH * port);
+}
+
+static int tb10x_get_groups_count(struct pinctrl_dev *pctl)
+{
+ struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
+ return state->pinfuncgrpcnt;
+}
+
+static const char *tb10x_get_group_name(struct pinctrl_dev *pctl, unsigned n)
+{
+ struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
+ return state->pingroups[n].name;
+}
+
+static int tb10x_get_group_pins(struct pinctrl_dev *pctl, unsigned n,
+ unsigned const **pins,
+ unsigned * const num_pins)
+{
+ struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
+
+ *pins = state->pingroups[n].pins;
+ *num_pins = state->pingroups[n].pincnt;
+
+ return 0;
+}
+
+static int tb10x_dt_node_to_map(struct pinctrl_dev *pctl,
+ struct device_node *np_config,
+ struct pinctrl_map **map, unsigned *num_maps)
+{
+ const char *string;
+ unsigned reserved_maps = 0;
+ int ret = 0;
+
+ if (of_property_read_string(np_config, "abilis,function", &string)) {
+ pr_err("%s: No abilis,function property in device tree.\n",
+ np_config->full_name);
+ return -EINVAL;
+ }
+
+ *map = NULL;
+ *num_maps = 0;
+
+ ret = pinctrl_utils_reserve_map(pctl, map, &reserved_maps,
+ num_maps, 1);
+ if (ret)
+ goto out;
+
+ ret = pinctrl_utils_add_map_mux(pctl, map, &reserved_maps,
+ num_maps, string, np_config->name);
+
+out:
+ return ret;
+}
+
+static struct pinctrl_ops tb10x_pinctrl_ops = {
+ .get_groups_count = tb10x_get_groups_count,
+ .get_group_name = tb10x_get_group_name,
+ .get_group_pins = tb10x_get_group_pins,
+ .dt_node_to_map = tb10x_dt_node_to_map,
+ .dt_free_map = pinctrl_utils_dt_free_map,
+};
+
+static int tb10x_get_functions_count(struct pinctrl_dev *pctl)
+{
+ struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
+ return state->pinfuncnt;
+}
+
+static const char *tb10x_get_function_name(struct pinctrl_dev *pctl,
+ unsigned n)
+{
+ struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
+ return state->pinfuncs[n].name;
+}
+
+static int tb10x_get_function_groups(struct pinctrl_dev *pctl,
+ unsigned n, const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
+
+ *groups = &state->pinfuncs[n].group;
+ *num_groups = 1;
+
+ return 0;
+}
+
+static int tb10x_gpio_request_enable(struct pinctrl_dev *pctl,
+ struct pinctrl_gpio_range *range,
+ unsigned pin)
+{
+ struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
+ int muxport = -1;
+ int muxmode = -1;
+ int i;
+
+ mutex_lock(&state->mutex);
+
+ /*
+ * Figure out to which port the requested GPIO belongs and how to
+ * configure that port.
+ * This loop also checks for pin conflicts between GPIOs and other
+ * functions.
+ */
+ for (i = 0; i < state->pinfuncgrpcnt; i++) {
+ const struct tb10x_pinfuncgrp *pfg = &state->pingroups[i];
+ unsigned int port = pfg->port;
+ unsigned int mode = pfg->mode;
+ int j;
+
+ /*
+ * Skip pin groups which are always mapped and don't need
+ * to be configured.
+ */
+ if (port < 0)
+ continue;
+
+ for (j = 0; j < pfg->pincnt; j++) {
+ if (pin == pfg->pins[j]) {
+ if (pfg->isgpio) {
+ /*
+ * Remember the GPIO-only setting of
+ * the port this pin belongs to.
+ */
+ muxport = port;
+ muxmode = mode;
+ } else if (state->ports[port].count
+ && (state->ports[port].mode == mode)) {
+ /*
+ * Error: The requested pin is already
+ * used for something else.
+ */
+ mutex_unlock(&state->mutex);
+ return -EBUSY;
+ }
+ break;
+ }
+ }
+ }
+
+ /*
+ * If we haven't returned an error at this point, the GPIO pin is not
+ * used by another function and the GPIO request can be granted:
+ * Register pin as being used as GPIO so we don't allocate it to
+ * another function later.
+ */
+ set_bit(pin, state->gpios);
+
+ /*
+ * Potential conflicts between GPIOs and pin functions were caught
+ * earlier in this function and tb10x_pinctrl_set_config will do the
+ * Right Thing, either configure the port in GPIO only mode or leave
+ * another mode compatible with this GPIO request untouched.
+ */
+ if (muxport >= 0)
+ tb10x_pinctrl_set_config(state, muxport, muxmode);
+
+ mutex_unlock(&state->mutex);
+
+ return 0;
+}
+
+static void tb10x_gpio_disable_free(struct pinctrl_dev *pctl,
+ struct pinctrl_gpio_range *range,
+ unsigned pin)
+{
+ struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
+
+ mutex_lock(&state->mutex);
+
+ clear_bit(pin, state->gpios);
+
+ mutex_unlock(&state->mutex);
+}
+
+static int tb10x_pctl_enable(struct pinctrl_dev *pctl,
+ unsigned func_selector, unsigned group_selector)
+{
+ struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
+ const struct tb10x_pinfuncgrp *grp = &state->pingroups[group_selector];
+ int i;
+
+ if (grp->port < 0)
+ return 0;
+
+ mutex_lock(&state->mutex);
+
+ /*
+ * Check if the requested function is compatible with previously
+ * requested functions.
+ */
+ if (state->ports[grp->port].count
+ && (state->ports[grp->port].mode != grp->mode)) {
+ mutex_unlock(&state->mutex);
+ return -EBUSY;
+ }
+
+ /*
+ * Check if the requested function is compatible with previously
+ * requested GPIOs.
+ */
+ for (i = 0; i < grp->pincnt; i++)
+ if (test_bit(grp->pins[i], state->gpios)) {
+ mutex_unlock(&state->mutex);
+ return -EBUSY;
+ }
+
+ tb10x_pinctrl_set_config(state, grp->port, grp->mode);
+
+ state->ports[grp->port].count++;
+
+ mutex_unlock(&state->mutex);
+
+ return 0;
+}
+
+static void tb10x_pctl_disable(struct pinctrl_dev *pctl,
+ unsigned func_selector, unsigned group_selector)
+{
+ struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
+ const struct tb10x_pinfuncgrp *grp = &state->pingroups[group_selector];
+
+ if (grp->port < 0)
+ return;
+
+ mutex_lock(&state->mutex);
+
+ state->ports[grp->port].count--;
+
+ mutex_unlock(&state->mutex);
+}
+
+static struct pinmux_ops tb10x_pinmux_ops = {
+ .get_functions_count = tb10x_get_functions_count,
+ .get_function_name = tb10x_get_function_name,
+ .get_function_groups = tb10x_get_function_groups,
+ .gpio_request_enable = tb10x_gpio_request_enable,
+ .gpio_disable_free = tb10x_gpio_disable_free,
+ .enable = tb10x_pctl_enable,
+ .disable = tb10x_pctl_disable,
+};
+
+static struct pinctrl_desc tb10x_pindesc = {
+ .name = "TB10x",
+ .pins = tb10x_pins,
+ .npins = ARRAY_SIZE(tb10x_pins),
+ .owner = THIS_MODULE,
+ .pctlops = &tb10x_pinctrl_ops,
+ .pmxops = &tb10x_pinmux_ops,
+};
+
+static int tb10x_pinctrl_probe(struct platform_device *pdev)
+{
+ int ret = -EINVAL;
+ struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ struct device *dev = &pdev->dev;
+ struct device_node *of_node = dev->of_node;
+ struct device_node *child;
+ struct tb10x_pinctrl *state;
+ int i;
+
+ if (!of_node) {
+ dev_err(dev, "No device tree node found.\n");
+ return -EINVAL;
+ }
+
+ if (!mem) {
+ dev_err(dev, "No memory resource defined.\n");
+ return -EINVAL;
+ }
+
+ state = devm_kzalloc(dev, sizeof(struct tb10x_pinctrl) +
+ of_get_child_count(of_node)
+ * sizeof(struct tb10x_of_pinfunc),
+ GFP_KERNEL);
+ if (!state)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, state);
+ state->pinfuncs = (struct tb10x_of_pinfunc *)(state + 1);
+ mutex_init(&state->mutex);
+
+ state->base = devm_ioremap_resource(dev, mem);
+ if (IS_ERR(state->base)) {
+ ret = PTR_ERR(state->base);
+ goto fail;
+ }
+
+ state->pingroups = tb10x_pingroups;
+ state->pinfuncgrpcnt = ARRAY_SIZE(tb10x_pingroups);
+
+ for (i = 0; i < TB10X_PORTS; i++)
+ state->ports[i].mode = tb10x_pinctrl_get_config(state, i);
+
+ for_each_child_of_node(of_node, child) {
+ const char *name;
+
+ if (!of_property_read_string(child, "abilis,function",
+ &name)) {
+ state->pinfuncs[state->pinfuncnt].name = child->name;
+ state->pinfuncs[state->pinfuncnt].group = name;
+ state->pinfuncnt++;
+ }
+ }
+
+ state->pctl = pinctrl_register(&tb10x_pindesc, dev, state);
+ if (!state->pctl) {
+ dev_err(dev, "could not register TB10x pin driver\n");
+ ret = -EINVAL;
+ goto fail;
+ }
+
+ return 0;
+
+fail:
+ mutex_destroy(&state->mutex);
+ return ret;
+}
+
+static int tb10x_pinctrl_remove(struct platform_device *pdev)
+{
+ struct tb10x_pinctrl *state = platform_get_drvdata(pdev);
+
+ pinctrl_unregister(state->pctl);
+ mutex_destroy(&state->mutex);
+
+ return 0;
+}
+
+
+static const struct of_device_id tb10x_pinctrl_dt_ids[] = {
+ { .compatible = "abilis,tb10x-iomux" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, tb10x_pinctrl_dt_ids);
+
+static struct platform_driver tb10x_pinctrl_pdrv = {
+ .probe = tb10x_pinctrl_probe,
+ .remove = tb10x_pinctrl_remove,
+ .driver = {
+ .name = "tb10x_pinctrl",
+ .of_match_table = of_match_ptr(tb10x_pinctrl_dt_ids),
+ .owner = THIS_MODULE
+ }
+};
+
+module_platform_driver(tb10x_pinctrl_pdrv);
+
+MODULE_AUTHOR("Christian Ruppert <christian.ruppert@abilis.com>");
+MODULE_LICENSE("GPL");
.driver = {
.name = "vf610-pinctrl",
.owner = THIS_MODULE,
- .of_match_table = of_match_ptr(vf610_pinctrl_of_match),
+ .of_match_table = vf610_pinctrl_of_match,
},
.probe = vf610_pinctrl_probe,
.remove = imx_pinctrl_remove,
pin_free(pctldev, pins[i], NULL);
} else {
const char *gname;
- const char *pname;
- pname = desc ? desc->name : "non-existing";
gname = pctlops->get_group_name(pctldev,
setting->data.mux.group);
dev_warn(pctldev->dev,
"not freeing pin %d (%s) as part of "
"deactivating group %s - it is already "
"used for some other setting",
- pins[i], pname, gname);
+ pins[i], desc->name, gname);
}
}
depends on ARCH_R8A7790
select PINCTRL_SH_PFC
+config PINCTRL_PFC_R8A7791
+ def_bool y
+ depends on ARCH_R8A7791
+ select PINCTRL_SH_PFC
+
config PINCTRL_PFC_SH7203
def_bool y
depends on CPU_SUBTYPE_SH7203
obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o
obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
.data = &r8a7790_pinmux_info,
},
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7791
+ {
+ .compatible = "renesas,pfc-r8a7791",
+ .data = &r8a7791_pinmux_info,
+ },
+#endif
#ifdef CONFIG_PINCTRL_PFC_SH7372
{
.compatible = "renesas,pfc-sh7372",
#ifdef CONFIG_PINCTRL_PFC_R8A7790
{ "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7791
+ { "pfc-r8a7791", (kernel_ulong_t)&r8a7791_pinmux_info },
+#endif
#ifdef CONFIG_PINCTRL_PFC_SH7203
{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
#endif
extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
extern const struct sh_pfc_soc_info sh7203_pinmux_info;
extern const struct sh_pfc_soc_info sh7264_pinmux_info;
extern const struct sh_pfc_soc_info sh7269_pinmux_info;
arg5##_MARK, arg6##_MARK, \
arg7##_MARK, arg8##_MARK, }
+/* - AUDIO macro -------------------------------------------------------------*/
+#define AUDIO_PFC_PIN(name, pin) SH_PFC_PINS(name, pin)
+#define AUDIO_PFC_DAT(name, pin) SH_PFC_MUX1(name, pin)
+
+/* - AUDIO clock -------------------------------------------------------------*/
+AUDIO_PFC_PIN(audio_clk_a, RCAR_GP_PIN(2, 22));
+AUDIO_PFC_DAT(audio_clk_a, AUDIO_CLKA);
+AUDIO_PFC_PIN(audio_clk_b, RCAR_GP_PIN(2, 23));
+AUDIO_PFC_DAT(audio_clk_b, AUDIO_CLKB);
+AUDIO_PFC_PIN(audio_clk_c, RCAR_GP_PIN(2, 7));
+AUDIO_PFC_DAT(audio_clk_c, AUDIO_CLKC);
+AUDIO_PFC_PIN(audio_clkout_a, RCAR_GP_PIN(2, 16));
+AUDIO_PFC_DAT(audio_clkout_a, AUDIO_CLKOUT_A);
+AUDIO_PFC_PIN(audio_clkout_b, RCAR_GP_PIN(1, 16));
+AUDIO_PFC_DAT(audio_clkout_b, AUDIO_CLKOUT_B);
+
+/* - CAN macro --------_----------------------------------------------------- */
+#define CAN_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
+#define CAN_PFC_DATA(name, tx, rx) SH_PFC_MUX2(name, tx, rx)
+#define CAN_PFC_CLK(name, clk) SH_PFC_MUX1(name, clk)
+
+/* - CAN0 ------------------------------------------------------------------- */
+CAN_PFC_PINS(can0_data_a, RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31));
+CAN_PFC_DATA(can0_data_a, CAN0_TX_A, CAN0_RX_A);
+CAN_PFC_PINS(can0_data_b, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27));
+CAN_PFC_DATA(can0_data_b, CAN0_TX_B, CAN0_RX_B);
+
+/* - CAN1 ------------------------------------------------------------------- */
+CAN_PFC_PINS(can1_data_a, RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19));
+CAN_PFC_DATA(can1_data_a, CAN1_TX_A, CAN1_RX_A);
+CAN_PFC_PINS(can1_data_b, RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 29));
+CAN_PFC_DATA(can1_data_b, CAN1_TX_B, CAN1_RX_B);
+
+/* - CAN_CLK --------------------------------------------------------------- */
+CAN_PFC_PINS(can_clk_a, RCAR_GP_PIN(3, 24));
+CAN_PFC_CLK(can_clk_a, CAN_CLK_A);
+CAN_PFC_PINS(can_clk_b, RCAR_GP_PIN(1, 16));
+CAN_PFC_CLK(can_clk_b, CAN_CLK_B);
+CAN_PFC_PINS(can_clk_c, RCAR_GP_PIN(4, 24));
+CAN_PFC_CLK(can_clk_c, CAN_CLK_C);
+CAN_PFC_PINS(can_clk_d, RCAR_GP_PIN(2, 25));
+CAN_PFC_CLK(can_clk_d, CAN_CLK_D);
+
/* - Ether ------------------------------------------------------------------ */
SH_PFC_PINS(ether_rmii, RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 9),
SDHI_PFC_PINS(sdhi2_wp_b, RCAR_GP_PIN(3, 28));
SDHI_PFC_WPPN(sdhi2_wp_b, SD2_WP_B);
+/* - SSI macro -------------------------------------------------------------- */
+#define SSI_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
+#define SSI_PFC_CTRL(name, sck, ws) SH_PFC_MUX2(name, sck, ws)
+#define SSI_PFC_DATA(name, d) SH_PFC_MUX1(name, d)
+
+/* - SSI 0/1/2 -------------------------------------------------------------- */
+SSI_PFC_PINS(ssi012_ctrl, RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7));
+SSI_PFC_CTRL(ssi012_ctrl, SSI_SCK012, SSI_WS012);
+SSI_PFC_PINS(ssi0_data, RCAR_GP_PIN(3, 10));
+SSI_PFC_DATA(ssi0_data, SSI_SDATA0);
+SSI_PFC_PINS(ssi1_a_ctrl, RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21));
+SSI_PFC_CTRL(ssi1_a_ctrl, SSI_SCK1_A, SSI_WS1_A);
+SSI_PFC_PINS(ssi1_b_ctrl, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3));
+SSI_PFC_CTRL(ssi1_b_ctrl, SSI_SCK1_B, SSI_WS1_B);
+SSI_PFC_PINS(ssi1_data, RCAR_GP_PIN(3, 9));
+SSI_PFC_DATA(ssi1_data, SSI_SDATA1);
+SSI_PFC_PINS(ssi2_a_ctrl, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(3, 4));
+SSI_PFC_CTRL(ssi2_a_ctrl, SSI_SCK2_A, SSI_WS2_A);
+SSI_PFC_PINS(ssi2_b_ctrl, RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 17));
+SSI_PFC_CTRL(ssi2_b_ctrl, SSI_SCK2_B, SSI_WS2_B);
+SSI_PFC_PINS(ssi2_data, RCAR_GP_PIN(3, 8));
+SSI_PFC_DATA(ssi2_data, SSI_SDATA2);
+
+/* - SSI 3/4 ---------------------------------------------------------------- */
+SSI_PFC_PINS(ssi34_ctrl, RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3));
+SSI_PFC_CTRL(ssi34_ctrl, SSI_SCK34, SSI_WS34);
+SSI_PFC_PINS(ssi3_data, RCAR_GP_PIN(3, 5));
+SSI_PFC_DATA(ssi3_data, SSI_SDATA3);
+SSI_PFC_PINS(ssi4_ctrl, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23));
+SSI_PFC_CTRL(ssi4_ctrl, SSI_SCK4, SSI_WS4);
+SSI_PFC_PINS(ssi4_data, RCAR_GP_PIN(3, 4));
+SSI_PFC_DATA(ssi4_data, SSI_SDATA4);
+
+/* - SSI 5 ------------------------------------------------------------------ */
+SSI_PFC_PINS(ssi5_ctrl, RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0));
+SSI_PFC_CTRL(ssi5_ctrl, SSI_SCK5, SSI_WS5);
+SSI_PFC_PINS(ssi5_data, RCAR_GP_PIN(3, 1));
+SSI_PFC_DATA(ssi5_data, SSI_SDATA5);
+
+/* - SSI 6 ------------------------------------------------------------------ */
+SSI_PFC_PINS(ssi6_ctrl, RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 29));
+SSI_PFC_CTRL(ssi6_ctrl, SSI_SCK6, SSI_WS6);
+SSI_PFC_PINS(ssi6_data, RCAR_GP_PIN(2, 30));
+SSI_PFC_DATA(ssi6_data, SSI_SDATA6);
+
+/* - SSI 7/8 --------------------------------------------------------------- */
+SSI_PFC_PINS(ssi78_ctrl, RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25));
+SSI_PFC_CTRL(ssi78_ctrl, SSI_SCK78, SSI_WS78);
+SSI_PFC_PINS(ssi7_data, RCAR_GP_PIN(2, 27));
+SSI_PFC_DATA(ssi7_data, SSI_SDATA7);
+SSI_PFC_PINS(ssi8_data, RCAR_GP_PIN(2, 26));
+SSI_PFC_DATA(ssi8_data, SSI_SDATA8);
+
/* - USB0 ------------------------------------------------------------------- */
SH_PFC_PINS(usb0, RCAR_GP_PIN(0, 1));
SH_PFC_MUX1(usb0, PENC0);
VIN_PFC_SYNC(vin1_sync, VI1_HSYNC, VI1_VSYNC);
static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(audio_clk_a),
+ SH_PFC_PIN_GROUP(audio_clk_b),
+ SH_PFC_PIN_GROUP(audio_clk_c),
+ SH_PFC_PIN_GROUP(audio_clkout_a),
+ SH_PFC_PIN_GROUP(audio_clkout_b),
+ SH_PFC_PIN_GROUP(can0_data_a),
+ SH_PFC_PIN_GROUP(can0_data_b),
+ SH_PFC_PIN_GROUP(can1_data_a),
+ SH_PFC_PIN_GROUP(can1_data_b),
+ SH_PFC_PIN_GROUP(can_clk_a),
+ SH_PFC_PIN_GROUP(can_clk_b),
+ SH_PFC_PIN_GROUP(can_clk_c),
+ SH_PFC_PIN_GROUP(can_clk_d),
SH_PFC_PIN_GROUP(ether_rmii),
SH_PFC_PIN_GROUP(ether_link),
SH_PFC_PIN_GROUP(ether_magic),
SH_PFC_PIN_GROUP(sdhi2_data4_b),
SH_PFC_PIN_GROUP(sdhi2_wp_a),
SH_PFC_PIN_GROUP(sdhi2_wp_b),
+ SH_PFC_PIN_GROUP(ssi012_ctrl),
+ SH_PFC_PIN_GROUP(ssi0_data),
+ SH_PFC_PIN_GROUP(ssi1_a_ctrl),
+ SH_PFC_PIN_GROUP(ssi1_b_ctrl),
+ SH_PFC_PIN_GROUP(ssi1_data),
+ SH_PFC_PIN_GROUP(ssi2_a_ctrl),
+ SH_PFC_PIN_GROUP(ssi2_b_ctrl),
+ SH_PFC_PIN_GROUP(ssi2_data),
+ SH_PFC_PIN_GROUP(ssi34_ctrl),
+ SH_PFC_PIN_GROUP(ssi3_data),
+ SH_PFC_PIN_GROUP(ssi4_ctrl),
+ SH_PFC_PIN_GROUP(ssi4_data),
+ SH_PFC_PIN_GROUP(ssi5_ctrl),
+ SH_PFC_PIN_GROUP(ssi5_data),
+ SH_PFC_PIN_GROUP(ssi6_ctrl),
+ SH_PFC_PIN_GROUP(ssi6_data),
+ SH_PFC_PIN_GROUP(ssi78_ctrl),
+ SH_PFC_PIN_GROUP(ssi7_data),
+ SH_PFC_PIN_GROUP(ssi8_data),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb0_ovc),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(vin1_sync),
};
+static const char * const audio_clk_groups[] = {
+ "audio_clk_a",
+ "audio_clk_b",
+ "audio_clk_c",
+ "audio_clkout_a",
+ "audio_clkout_b",
+};
+
+static const char * const can0_groups[] = {
+ "can0_data_a",
+ "can0_data_b",
+ "can_clk_a",
+ "can_clk_b",
+ "can_clk_c",
+ "can_clk_d",
+};
+
+static const char * const can1_groups[] = {
+ "can1_data_a",
+ "can1_data_b",
+ "can_clk_a",
+ "can_clk_b",
+ "can_clk_c",
+ "can_clk_d",
+};
+
static const char * const ether_groups[] = {
"ether_rmii",
"ether_link",
"sdhi2_wp_b",
};
+static const char * const ssi_groups[] = {
+ "ssi012_ctrl",
+ "ssi0_data",
+ "ssi1_a_ctrl",
+ "ssi1_b_ctrl",
+ "ssi1_data",
+ "ssi2_a_ctrl",
+ "ssi2_b_ctrl",
+ "ssi2_data",
+ "ssi34_ctrl",
+ "ssi3_data",
+ "ssi4_ctrl",
+ "ssi4_data",
+ "ssi5_ctrl",
+ "ssi5_data",
+ "ssi6_ctrl",
+ "ssi6_data",
+ "ssi78_ctrl",
+ "ssi7_data",
+ "ssi8_data",
+};
+
static const char * const usb0_groups[] = {
"usb0",
"usb0_ovc",
};
static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(audio_clk),
+ SH_PFC_FUNCTION(can0),
+ SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(ether),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(sdhi0),
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),
+ SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(vin0),
ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
TCLK1_B_MARK,
+
+ I2C3_SCL_MARK, I2C3_SDA_MARK,
PINMUX_MARK_END,
};
PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
+
+ PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
+ PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
};
+/* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */
+#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
+#define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200)
+#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
+
static struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
+
+ /* Pins not associated with a GPIO port */
+ SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15),
+ SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),
};
/* - DU RGB ----------------------------------------------------------------- */
static const unsigned int hscif1_ctrl_b_mux[] = {
HRTS1_N_B_MARK, HCTS1_N_B_MARK,
};
+/* - I2C1 ------------------------------------------------------------------- */
+static const unsigned int i2c1_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
+};
+static const unsigned int i2c1_mux[] = {
+ I2C1_SCL_MARK, I2C1_SDA_MARK,
+};
+static const unsigned int i2c1_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+static const unsigned int i2c1_b_mux[] = {
+ I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
+};
+static const unsigned int i2c1_c_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
+};
+static const unsigned int i2c1_c_mux[] = {
+ I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
+};
+/* - I2C2 ------------------------------------------------------------------- */
+static const unsigned int i2c2_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int i2c2_mux[] = {
+ I2C2_SCL_MARK, I2C2_SDA_MARK,
+};
+static const unsigned int i2c2_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
+};
+static const unsigned int i2c2_b_mux[] = {
+ I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
+};
+static const unsigned int i2c2_c_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int i2c2_c_mux[] = {
+ I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
+};
+static const unsigned int i2c2_d_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
+};
+static const unsigned int i2c2_d_mux[] = {
+ I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
+};
+static const unsigned int i2c2_e_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
+};
+static const unsigned int i2c2_e_mux[] = {
+ I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
+};
+/* - I2C3 ------------------------------------------------------------------- */
+static const unsigned int i2c3_pins[] = {
+ /* SCL, SDA */
+ PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
+};
+static const unsigned int i2c3_mux[] = {
+ I2C3_SCL_MARK, I2C3_SDA_MARK,
+};
/* - INTC ------------------------------------------------------------------- */
static const unsigned int intc_irq0_pins[] = {
/* IRQ */
SH_PFC_PIN_GROUP(hscif1_data_b),
SH_PFC_PIN_GROUP(hscif1_clk_b),
SH_PFC_PIN_GROUP(hscif1_ctrl_b),
+ SH_PFC_PIN_GROUP(i2c1),
+ SH_PFC_PIN_GROUP(i2c1_b),
+ SH_PFC_PIN_GROUP(i2c1_c),
+ SH_PFC_PIN_GROUP(i2c2),
+ SH_PFC_PIN_GROUP(i2c2_b),
+ SH_PFC_PIN_GROUP(i2c2_c),
+ SH_PFC_PIN_GROUP(i2c2_d),
+ SH_PFC_PIN_GROUP(i2c2_e),
+ SH_PFC_PIN_GROUP(i2c3),
SH_PFC_PIN_GROUP(intc_irq0),
SH_PFC_PIN_GROUP(intc_irq1),
SH_PFC_PIN_GROUP(intc_irq2),
"hscif1_ctrl_b",
};
+static const char * const i2c1_groups[] = {
+ "i2c1",
+ "i2c1_b",
+ "i2c1_c",
+};
+
+static const char * const i2c2_groups[] = {
+ "i2c2",
+ "i2c2_b",
+ "i2c2_c",
+ "i2c2_d",
+ "i2c2_e",
+};
+
+static const char * const i2c3_groups[] = {
+ "i2c3",
+};
+
static const char * const intc_groups[] = {
"intc_irq0",
"intc_irq1",
SH_PFC_FUNCTION(eth),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
+ SH_PFC_FUNCTION(i2c1),
+ SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(intc),
SH_PFC_FUNCTION(mmc0),
SH_PFC_FUNCTION(mmc1),
--- /dev/null
+/*
+ * r8a7791 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_data/gpio-rcar.h>
+
+#include "core.h"
+#include "sh_pfc.h"
+
+#define CPU_ALL_PORT(fn, sfx) \
+ PORT_GP_32(0, fn, sfx), \
+ PORT_GP_32(1, fn, sfx), \
+ PORT_GP_32(2, fn, sfx), \
+ PORT_GP_32(3, fn, sfx), \
+ PORT_GP_32(4, fn, sfx), \
+ PORT_GP_32(5, fn, sfx), \
+ PORT_GP_32(6, fn, sfx), \
+ PORT_GP_32(7, fn, sfx)
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ PINMUX_DATA_BEGIN,
+ GP_ALL(DATA),
+ PINMUX_DATA_END,
+
+ PINMUX_FUNCTION_BEGIN,
+ GP_ALL(FN),
+
+ /* GPSR0 */
+ FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
+ FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
+ FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
+ FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
+ FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
+ FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
+
+ /* GPSR1 */
+ FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
+ FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
+ FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
+ FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
+ FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
+ FN_IP3_21_20,
+
+ /* GPSR2 */
+ FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
+ FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
+ FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
+ FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
+ FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
+ FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
+ FN_IP6_5_3, FN_IP6_7_6,
+
+ /* GPSR3 */
+ FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
+ FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
+ FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
+ FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
+ FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
+ FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
+ FN_IP9_18_17,
+
+ /* GPSR4 */
+ FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
+ FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
+ FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
+ FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
+ FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
+ FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
+ FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
+ FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
+
+ /* GPSR5 */
+ FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
+ FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
+ FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
+ FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
+ FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
+ FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
+ FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
+
+ /* GPSR6 */
+ FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
+ FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23,
+ FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
+ FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
+ FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
+ FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
+ FN_USB1_OVC, FN_DU0_DOTCLKIN,
+
+ /* GPSR7 */
+ FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
+ FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
+ FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
+ FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
+ FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
+ FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
+
+ /* IPSR0 */
+ FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
+ FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
+ FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
+ FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
+ FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
+ FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
+
+ /* IPSR1 */
+ FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_SCL0,
+ FN_A9, FN_MSIOF1_SS2, FN_SDA0,
+ FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
+ FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
+ FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
+ FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
+ FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
+ FN_A15, FN_BPFCLK_C,
+ FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
+ FN_A17, FN_DACK2_B, FN_SDA0_C,
+ FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
+
+ /* IPSR2 */
+ FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
+ FN_A20, FN_SPCLK,
+ FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
+ FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
+ FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
+ FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
+ FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
+ FN_CS0_N, FN_ATAG0_N_B, FN_SCL1,
+ FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1,
+ FN_EX_CS1_N, FN_MSIOF2_SCK,
+ FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
+ FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
+
+ /* IPSR3 */
+ FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
+ FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
+ FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
+ FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
+ FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
+ FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
+ FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
+ FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
+ FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
+ FN_DREQ0, FN_PWM3, FN_TPU_TO3,
+ FN_DACK0, FN_DRACK0, FN_REMOCON,
+ FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
+ FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
+ FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
+ FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
+
+ /* IPSR4 */
+ FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C,
+ FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B, FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
+ FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
+ FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
+ FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
+ FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
+ FN_GLO_Q1_D, FN_HCTS1_N_E,
+ FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
+ FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
+ FN_SSI_SCK4, FN_GLO_SS_D,
+ FN_SSI_WS4, FN_GLO_RFON_D,
+ FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
+ FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
+ FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
+
+ /* IPSR5 */
+ FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
+ FN_MSIOF2_TXD_D, FN_VI1_R3_B,
+ FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
+ FN_MSIOF2_SS1_D, FN_VI1_R4_B,
+ FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
+ FN_MSIOF2_RXD_D, FN_VI1_R5_B,
+ FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
+ FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
+ FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
+ FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
+ FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
+ FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
+ FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
+ FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
+ FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
+
+ /* IPSR6 */
+ FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
+ FN_SCIF_CLK, FN_BPFCLK_E,
+ FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
+ FN_SCIFA2_RXD, FN_FMIN_E,
+ FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
+ FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
+ FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
+ FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
+ FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
+ FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
+ FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
+ FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E,
+ FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
+ FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
+
+ /* IPSR7 */
+ FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
+ FN_SCIF_CLK_B, FN_GPS_MAG_D,
+ FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
+ FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
+ FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
+ FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
+ FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
+ FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
+ FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
+ FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
+ FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
+ FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
+ FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
+ FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
+ FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
+ FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
+ FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
+ FN_SCIFA1_SCK, FN_SSI_SCK78_B,
+
+ /* IPSR8 */
+ FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
+ FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
+ FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
+ FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
+ FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
+ FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
+ FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
+ FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
+ FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
+ FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
+ FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
+ FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
+ FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
+ FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
+ FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
+ FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
+ FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
+
+ /* IPSR9 */
+ FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
+ FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
+ FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
+ FN_DU1_DOTCLKOUT0, FN_QCLK,
+ FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
+ FN_TX3_B, FN_SCL2_B, FN_PWM4,
+ FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
+ FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
+ FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
+ FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
+ FN_DU1_DISP, FN_QPOLA,
+ FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
+ FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
+ FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
+ FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
+ FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
+ FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
+ FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
+ FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
+
+ /* IPSR10 */
+ FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
+ FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
+ FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
+ FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
+ FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
+ FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
+ FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
+ FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
+ FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
+ FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
+ FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
+ FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
+ FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
+ FN_TS_SDATA0_C, FN_ATACS11_N,
+ FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
+ FN_TS_SCK0_C, FN_ATAG1_N,
+ FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
+ FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
+ FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
+
+ /* IPSR11 */
+ FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
+ FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
+ FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
+ FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
+ FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
+ FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
+ FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
+ FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
+ FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
+ FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
+ FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
+ FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
+ FN_VI1_DATA7, FN_AVB_MDC,
+ FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
+ FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
+
+ /* IPSR12 */
+ FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
+ FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
+ FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
+ FN_SCL2_D, FN_MSIOF1_RXD_E,
+ FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
+ FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
+ FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
+ FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
+ FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
+ FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
+ FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
+ FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
+ FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
+ FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
+ FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
+ FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
+ FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
+
+ /* IPSR13 */
+ FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
+ FN_ADICLK_B, FN_MSIOF0_SS1_C,
+ FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
+ FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
+ FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
+ FN_ADICHS2_B, FN_MSIOF0_TXD_C,
+ FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
+ FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
+ FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
+ FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
+ FN_SCIFA5_TXD_B, FN_TX3_C,
+ FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
+ FN_SCIFA5_RXD_B, FN_RX3_C,
+ FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
+ FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
+ FN_SD1_DATA3, FN_IERX_B,
+ FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
+
+ /* IPSR14 */
+ FN_SD1_WP, FN_PWM1_B, FN_SDA1_C,
+ FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
+ FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
+ FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
+ FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
+ FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
+ FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
+ FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
+ FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
+ FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
+ FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
+ FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B,
+ FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
+ FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B,
+
+ /* IPSR15 */
+ FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
+ FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
+ FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
+ FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
+ FN_PWM5_B, FN_SCIFA3_TXD_C,
+ FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
+ FN_VI1_G6_B, FN_SCIFA3_RXD_C,
+ FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
+ FN_VI1_G7_B, FN_SCIFA3_SCK_C,
+ FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
+ FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
+ FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
+ FN_TCLK2, FN_VI1_DATA3_C,
+ FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
+ FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
+
+ /* IPSR16 */
+ FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
+ FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
+ FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
+ FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
+ FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
+
+ /* MOD_SEL */
+ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+ FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
+ FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
+ FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
+ FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
+ FN_SEL_SSI9_0, FN_SEL_SSI9_1,
+ FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+ FN_SEL_QSP_0, FN_SEL_QSP_1,
+ FN_SEL_SSI7_0, FN_SEL_SSI7_1,
+ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
+ FN_SEL_HSCIF1_4,
+ FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
+ FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+ FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
+ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+ FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
+
+ /* MOD_SEL2 */
+ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
+ FN_SEL_SCIF0_4,
+ FN_SEL_SCIF_0, FN_SEL_SCIF_1,
+ FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+ FN_SEL_CAN0_4, FN_SEL_CAN0_5,
+ FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+ FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
+ FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
+ FN_SEL_ADG_0, FN_SEL_ADG_1,
+ FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
+ FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
+ FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
+ FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
+ FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
+ FN_SEL_SIM_0, FN_SEL_SIM_1,
+ FN_SEL_SSI8_0, FN_SEL_SSI8_1,
+
+ /* MOD_SEL3 */
+ FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
+ FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
+ FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
+ FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
+ FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
+ FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
+ FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
+ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+ FN_SEL_MMC_0, FN_SEL_MMC_1,
+ FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
+ FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+ FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
+ FN_SEL_IIC1_4,
+ FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
+
+ /* MOD_SEL4 */
+ FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
+ FN_SEL_SOF1_4,
+ FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
+ FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
+ FN_SEL_RAD_0, FN_SEL_RAD_1,
+ FN_SEL_RCN_0, FN_SEL_RCN_1,
+ FN_SEL_RSP_0, FN_SEL_RSP_1,
+ FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
+ FN_SEL_SCIF2_4,
+ FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
+ FN_SEL_SOF2_4,
+ FN_SEL_SSI1_0, FN_SEL_SSI1_1,
+ FN_SEL_SSI0_0, FN_SEL_SSI0_1,
+ FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
+ PINMUX_FUNCTION_END,
+
+ PINMUX_MARK_BEGIN,
+
+ EX_CS0_N_MARK, RD_N_MARK,
+
+ AUDIO_CLKA_MARK,
+
+ VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
+ VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
+ VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
+
+ SD1_CLK_MARK,
+
+ USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
+ DU0_DOTCLKIN_MARK,
+
+ /* IPSR0 */
+ D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
+ D6_MARK, D7_MARK, D8_MARK,
+ D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
+ A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, SCL0_C_MARK, PWM2_B_MARK,
+ A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
+ A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
+ A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
+
+ /* IPSR1 */
+ A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, SCL0_MARK,
+ A9_MARK, MSIOF1_SS2_MARK, SDA0_MARK,
+ A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
+ A11_MARK, MSIOF1_RXD_MARK, SCL3_D_MARK, MSIOF1_RXD_D_MARK,
+ A12_MARK, FMCLK_MARK, SDA3_D_MARK, MSIOF1_SCK_D_MARK,
+ A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
+ A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
+ A15_MARK, BPFCLK_C_MARK,
+ A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
+ A17_MARK, DACK2_B_MARK, SDA0_C_MARK,
+ A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
+
+ /* IPSR2 */
+ A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
+ SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
+ A20_MARK, SPCLK_MARK,
+ A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
+ A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
+ A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
+ A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
+ A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
+ RX1_MARK, SCIFA1_RXD_MARK,
+ CS0_N_MARK, ATAG0_N_B_MARK, SCL1_MARK,
+ CS1_N_A26_MARK, ATADIR0_N_B_MARK, SDA1_MARK,
+ EX_CS1_N_MARK, MSIOF2_SCK_MARK,
+ EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
+ EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
+ ATAG0_N_MARK, EX_WAIT1_MARK,
+
+ /* IPSR3 */
+ EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
+ EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
+ SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
+ BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
+ SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
+ RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
+ SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
+ WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
+ WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
+ EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
+ DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
+ DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
+ SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
+ SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
+ SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
+ SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
+ SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
+ SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
+
+ /* IPSR4 */
+ SSI_SDATA0_MARK, SCL0_B_MARK, SCL7_B_MARK, MSIOF2_SCK_C_MARK,
+ SSI_SCK1_MARK, SDA0_B_MARK, SDA7_B_MARK,
+ MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
+ SSI_WS1_MARK, SCL1_B_MARK, SCL8_B_MARK,
+ MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
+ SSI_SDATA1_MARK, SDA1_B_MARK, SDA8_B_MARK, MSIOF2_RXD_C_MARK,
+ SSI_SCK2_MARK, SCL2_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, HSCK1_E_MARK,
+ SSI_WS2_MARK, SDA2_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
+ GLO_Q1_D_MARK, HCTS1_N_E_MARK,
+ SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
+ SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
+ SSI_SCK4_MARK, GLO_SS_D_MARK,
+ SSI_WS4_MARK, GLO_RFON_D_MARK,
+ SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
+ SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
+ MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
+
+ /* IPSR5 */
+ SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
+ MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
+ SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
+ MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
+ SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
+ MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
+ SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
+ SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
+ SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
+ SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
+ SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
+ SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
+ SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
+ SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
+ SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
+
+ /* IPSR6 */
+ AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
+ SCIF_CLK_MARK, BPFCLK_E_MARK,
+ AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
+ SCIFA2_RXD_MARK, FMIN_E_MARK,
+ AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
+ IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
+ IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
+ IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
+ IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
+ IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK,
+ MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
+ IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK,
+ IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
+ SDA1_E_MARK, MSIOF2_SYNC_E_MARK,
+ IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
+ GPS_CLK_C_MARK, GPS_CLK_D_MARK,
+ IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
+ GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
+
+ /* IPSR7 */
+ IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
+ SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
+ DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
+ SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
+ DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
+ SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
+ DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
+ DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
+ DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
+ DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
+ DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
+ DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
+ DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
+ SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
+ DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
+ SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
+ DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
+ SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
+
+ /* IPSR8 */
+ DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
+ DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
+ SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
+ DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
+ SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
+ DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
+ SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
+ DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
+ SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
+ DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
+ SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
+ DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
+ SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
+ DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
+ SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
+ DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
+ DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
+ DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
+
+ /* IPSR9 */
+ DU1_DB6_MARK, LCDOUT22_MARK, SCL3_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
+ DU1_DB7_MARK, LCDOUT23_MARK, SDA3_C_MARK,
+ SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
+ DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
+ DU1_DOTCLKOUT0_MARK, QCLK_MARK,
+ DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
+ TX3_B_MARK, SCL2_B_MARK, PWM4_MARK,
+ DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
+ DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
+ DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
+ CAN0_RX_MARK, RX3_B_MARK, SDA2_B_MARK,
+ DU1_DISP_MARK, QPOLA_MARK,
+ DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
+ VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
+ VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
+ VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
+ VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
+ VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
+ VI0_G0_MARK, SCL8_MARK, STP_IVCXO27_0_C_MARK, SCL4_MARK,
+ HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
+
+ /* IPSR10 */
+ VI0_G1_MARK, SDA8_MARK, STP_ISCLK_0_C_MARK, SDA4_MARK,
+ HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
+ VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, SCL3_B_MARK,
+ HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
+ VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, SDA3_B_MARK,
+ HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
+ VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
+ HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
+ VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
+ CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
+ VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
+ VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
+ VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
+ TS_SDATA0_C_MARK, ATACS11_N_MARK,
+ VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
+ TS_SCK0_C_MARK, ATAG1_N_MARK,
+ VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
+ VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
+ VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, SCL1_D_MARK,
+
+ /* IPSR11 */
+ VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
+ VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
+ VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
+ SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
+ VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
+ TX4_B_MARK, SCIFA4_TXD_B_MARK,
+ VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
+ RX4_B_MARK, SCIFA4_RXD_B_MARK,
+ VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
+ VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
+ VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
+ VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
+ VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
+ VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
+ VI1_DATA7_MARK, AVB_MDC_MARK,
+ ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
+ ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
+
+ /* IPSR12 */
+ ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
+ ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
+ ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
+ SCL2_D_MARK, MSIOF1_RXD_E_MARK,
+ ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
+ SDA2_D_MARK, MSIOF1_SCK_E_MARK,
+ ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
+ CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
+ ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
+ CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
+ ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
+ ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
+ ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
+ ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
+ STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
+ ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
+ STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
+ ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
+
+ /* IPSR13 */
+ STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
+ ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
+ STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
+ STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
+ STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
+ ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
+ SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
+ SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
+ SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
+ SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
+ SCIFA5_TXD_B_MARK, TX3_C_MARK,
+ SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
+ SCIFA5_RXD_B_MARK, RX3_C_MARK,
+ SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
+ SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
+ SD1_DATA3_MARK, IERX_B_MARK,
+ SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK,
+
+ /* IPSR14 */
+ SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK,
+ SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
+ SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
+ SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
+ SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK,
+ SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK,
+ MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
+ VI1_CLK_C_MARK, VI1_G0_B_MARK,
+ MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
+ VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
+ MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
+ MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
+ MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
+ VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK,
+ MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
+ VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK,
+
+ /* IPSR15 */
+ SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
+ SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
+ SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
+ GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
+ PWM5_B_MARK, SCIFA3_TXD_C_MARK,
+ GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
+ VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
+ GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
+ VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
+ HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
+ TCLK1_MARK, VI1_DATA1_C_MARK,
+ HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
+ HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
+ TCLK2_MARK, VI1_DATA3_C_MARK,
+ HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
+ CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
+ HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
+ CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
+
+ /* IPSR16 */
+ HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
+ GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
+ HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
+ GLO_SS_C_MARK, VI1_DATA7_C_MARK,
+ HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CK_MARK, GLO_RFON_C_MARK,
+ HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
+ HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
+ PINMUX_MARK_END,
+};
+
+static const u16 pinmux_data[] = {
+ PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+ PINMUX_DATA(EX_CS0_N_MARK, FN_EX_CS0_N),
+ PINMUX_DATA(RD_N_MARK, FN_RD_N),
+ PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA),
+ PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK),
+ PINMUX_DATA(VI0_DATA0_VI0_B0_MARK, FN_VI0_DATA0_VI0_B0),
+ PINMUX_DATA(VI0_DATA1_VI0_B1_MARK, FN_VI0_DATA1_VI0_B1),
+ PINMUX_DATA(VI0_DATA2_VI0_B2_MARK, FN_VI0_DATA2_VI0_B2),
+ PINMUX_DATA(VI0_DATA4_VI0_B4_MARK, FN_VI0_DATA4_VI0_B4),
+ PINMUX_DATA(VI0_DATA5_VI0_B5_MARK, FN_VI0_DATA5_VI0_B5),
+ PINMUX_DATA(VI0_DATA6_VI0_B6_MARK, FN_VI0_DATA6_VI0_B6),
+ PINMUX_DATA(VI0_DATA7_VI0_B7_MARK, FN_VI0_DATA7_VI0_B7),
+ PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
+ PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
+ PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
+ PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
+ PINMUX_DATA(DU0_DOTCLKIN_MARK, FN_DU0_DOTCLKIN),
+
+ /* IPSR0 */
+ PINMUX_IPSR_DATA(IP0_0, D0),
+ PINMUX_IPSR_DATA(IP0_1, D1),
+ PINMUX_IPSR_DATA(IP0_2, D2),
+ PINMUX_IPSR_DATA(IP0_3, D3),
+ PINMUX_IPSR_DATA(IP0_4, D4),
+ PINMUX_IPSR_DATA(IP0_5, D5),
+ PINMUX_IPSR_DATA(IP0_6, D6),
+ PINMUX_IPSR_DATA(IP0_7, D7),
+ PINMUX_IPSR_DATA(IP0_8, D8),
+ PINMUX_IPSR_DATA(IP0_9, D9),
+ PINMUX_IPSR_DATA(IP0_10, D10),
+ PINMUX_IPSR_DATA(IP0_11, D11),
+ PINMUX_IPSR_DATA(IP0_12, D12),
+ PINMUX_IPSR_DATA(IP0_13, D13),
+ PINMUX_IPSR_DATA(IP0_14, D14),
+ PINMUX_IPSR_DATA(IP0_15, D15),
+ PINMUX_IPSR_DATA(IP0_18_16, A0),
+ PINMUX_IPSR_MODSEL_DATA(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
+ PINMUX_IPSR_MODSEL_DATA(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SCL0_C, SEL_IIC0_2),
+ PINMUX_IPSR_DATA(IP0_18_16, PWM2_B),
+ PINMUX_IPSR_DATA(IP0_20_19, A1),
+ PINMUX_IPSR_MODSEL_DATA(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
+ PINMUX_IPSR_DATA(IP0_22_21, A2),
+ PINMUX_IPSR_MODSEL_DATA(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
+ PINMUX_IPSR_DATA(IP0_24_23, A3),
+ PINMUX_IPSR_MODSEL_DATA(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
+ PINMUX_IPSR_DATA(IP0_26_25, A4),
+ PINMUX_IPSR_MODSEL_DATA(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
+ PINMUX_IPSR_DATA(IP0_28_27, A5),
+ PINMUX_IPSR_MODSEL_DATA(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
+ PINMUX_IPSR_DATA(IP0_30_29, A6),
+ PINMUX_IPSR_MODSEL_DATA(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
+
+ /* IPSR1 */
+ PINMUX_IPSR_DATA(IP1_1_0, A7),
+ PINMUX_IPSR_MODSEL_DATA(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
+ PINMUX_IPSR_DATA(IP1_3_2, A8),
+ PINMUX_IPSR_MODSEL_DATA(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP1_3_2, SCL0, SEL_IIC0_0),
+ PINMUX_IPSR_DATA(IP1_5_4, A9),
+ PINMUX_IPSR_MODSEL_DATA(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP1_5_4, SDA0, SEL_IIC0_0),
+ PINMUX_IPSR_DATA(IP1_7_6, A10),
+ PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
+ PINMUX_IPSR_DATA(IP1_10_8, A11),
+ PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCL3_D, SEL_IIC3_3),
+ PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
+ PINMUX_IPSR_DATA(IP1_13_11, A12),
+ PINMUX_IPSR_MODSEL_DATA(IP1_13_11, FMCLK, SEL_FM_0),
+ PINMUX_IPSR_MODSEL_DATA(IP1_13_11, SDA3_D, SEL_IIC3_3),
+ PINMUX_IPSR_MODSEL_DATA(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
+ PINMUX_IPSR_DATA(IP1_16_14, A13),
+ PINMUX_IPSR_MODSEL_DATA(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
+ PINMUX_IPSR_MODSEL_DATA(IP1_16_14, BPFCLK, SEL_FM_0),
+ PINMUX_IPSR_MODSEL_DATA(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
+ PINMUX_IPSR_DATA(IP1_19_17, A14),
+ PINMUX_IPSR_MODSEL_DATA(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
+ PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN, SEL_FM_0),
+ PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN_C, SEL_FM_2),
+ PINMUX_IPSR_MODSEL_DATA(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
+ PINMUX_IPSR_DATA(IP1_22_20, A15),
+ PINMUX_IPSR_MODSEL_DATA(IP1_22_20, BPFCLK_C, SEL_FM_2),
+ PINMUX_IPSR_DATA(IP1_25_23, A16),
+ PINMUX_IPSR_MODSEL_DATA(IP1_25_23, DREQ2_B, SEL_LBS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP1_25_23, FMCLK_C, SEL_FM_2),
+ PINMUX_IPSR_MODSEL_DATA(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
+ PINMUX_IPSR_DATA(IP1_28_26, A17),
+ PINMUX_IPSR_MODSEL_DATA(IP1_28_26, DACK2_B, SEL_LBS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP1_28_26, SDA0_C, SEL_IIC0_2),
+ PINMUX_IPSR_DATA(IP1_31_29, A18),
+ PINMUX_IPSR_MODSEL_DATA(IP1_31_29, DREQ1, SEL_LBS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
+
+ /* IPSR2 */
+ PINMUX_IPSR_DATA(IP2_2_0, A19),
+ PINMUX_IPSR_DATA(IP2_2_0, DACK1),
+ PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_0),
+ PINMUX_IPSR_DATA(IP2_2_0, A20),
+ PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SPCLK, SEL_QSP_0),
+ PINMUX_IPSR_DATA(IP2_6_5, A21),
+ PINMUX_IPSR_MODSEL_DATA(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP2_6_5, MOSI_IO0, SEL_QSP_0),
+ PINMUX_IPSR_DATA(IP2_9_7, A22),
+ PINMUX_IPSR_MODSEL_DATA(IP2_9_7, MISO_IO1, SEL_QSP_0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_9_7, FMCLK_B, SEL_FM_1),
+ PINMUX_IPSR_MODSEL_DATA(IP2_9_7, TX0, SEL_SCIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
+ PINMUX_IPSR_DATA(IP2_12_10, A23),
+ PINMUX_IPSR_MODSEL_DATA(IP2_12_10, IO2, SEL_QSP_0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_12_10, BPFCLK_B, SEL_FM_1),
+ PINMUX_IPSR_MODSEL_DATA(IP2_12_10, RX0, SEL_SCIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
+ PINMUX_IPSR_DATA(IP2_15_13, A24),
+ PINMUX_IPSR_MODSEL_DATA(IP2_15_13, DREQ2, SEL_LBS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_15_13, IO3, SEL_QSP_0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_15_13, TX1, SEL_SCIF1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
+ PINMUX_IPSR_DATA(IP2_18_16, A25),
+ PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DACK2, SEL_LBS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SSL, SEL_QSP_0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ1_C, SEL_LBS_2),
+ PINMUX_IPSR_MODSEL_DATA(IP2_18_16, RX1, SEL_SCIF1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
+ PINMUX_IPSR_DATA(IP2_20_19, CS0_N),
+ PINMUX_IPSR_MODSEL_DATA(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP2_20_19, SCL1, SEL_IIC1_0),
+ PINMUX_IPSR_DATA(IP2_22_21, CS1_N_A26),
+ PINMUX_IPSR_MODSEL_DATA(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP2_22_21, SDA1, SEL_IIC1_0),
+ PINMUX_IPSR_DATA(IP2_24_23, EX_CS1_N),
+ PINMUX_IPSR_MODSEL_DATA(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
+ PINMUX_IPSR_DATA(IP2_26_25, EX_CS2_N),
+ PINMUX_IPSR_MODSEL_DATA(IP2_26_25, ATAWR0_N, SEL_LBS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
+ PINMUX_IPSR_DATA(IP2_29_27, EX_CS3_N),
+ PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATADIR0_N, SEL_LBS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATAG0_N, SEL_LBS_0),
+ PINMUX_IPSR_DATA(IP2_29_27, EX_WAIT1),
+
+ /* IPSR3 */
+ PINMUX_IPSR_DATA(IP3_2_0, EX_CS4_N),
+ PINMUX_IPSR_MODSEL_DATA(IP3_2_0, ATARD0_N, SEL_LBS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
+ PINMUX_IPSR_DATA(IP3_2_0, EX_WAIT2),
+ PINMUX_IPSR_DATA(IP3_5_3, EX_CS5_N),
+ PINMUX_IPSR_DATA(IP3_5_3, ATACS00_N),
+ PINMUX_IPSR_MODSEL_DATA(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
+ PINMUX_IPSR_MODSEL_DATA(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_DATA(IP3_5_3, PWM1),
+ PINMUX_IPSR_DATA(IP3_5_3, TPU_TO1),
+ PINMUX_IPSR_DATA(IP3_8_6, BS_N),
+ PINMUX_IPSR_DATA(IP3_8_6, ATACS10_N),
+ PINMUX_IPSR_MODSEL_DATA(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
+ PINMUX_IPSR_MODSEL_DATA(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
+ PINMUX_IPSR_DATA(IP3_8_6, PWM2),
+ PINMUX_IPSR_DATA(IP3_8_6, TPU_TO2),
+ PINMUX_IPSR_DATA(IP3_11_9, RD_WR_N),
+ PINMUX_IPSR_MODSEL_DATA(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP3_11_9, FMIN_B, SEL_FM_1),
+ PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
+ PINMUX_IPSR_MODSEL_DATA(IP3_11_9, DREQ1_D, SEL_LBS_1),
+ PINMUX_IPSR_DATA(IP3_13_12, WE0_N),
+ PINMUX_IPSR_MODSEL_DATA(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
+ PINMUX_IPSR_DATA(IP3_15_14, WE1_N),
+ PINMUX_IPSR_MODSEL_DATA(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
+ PINMUX_IPSR_DATA(IP3_17_16, EX_WAIT0),
+ PINMUX_IPSR_MODSEL_DATA(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
+ PINMUX_IPSR_DATA(IP3_19_18, DREQ0),
+ PINMUX_IPSR_DATA(IP3_19_18, PWM3),
+ PINMUX_IPSR_DATA(IP3_19_18, TPU_TO3),
+ PINMUX_IPSR_DATA(IP3_21_20, DACK0),
+ PINMUX_IPSR_DATA(IP3_21_20, DRACK0),
+ PINMUX_IPSR_MODSEL_DATA(IP3_21_20, REMOCON, SEL_RCN_0),
+ PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SPEEDIN, SEL_RSP_0),
+ PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
+ PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
+ PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP3_24_22, DREQ2_C, SEL_LBS_2),
+ PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
+ PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
+ PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
+ PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
+ PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
+ PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
+ PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
+
+ /* IPSR4 */
+ PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL0_B, SEL_IIC0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL7_B, SEL_IIC7_1),
+ PINMUX_IPSR_MODSEL_DATA(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
+ PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA0_B, SEL_IIC0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA7_B, SEL_IIC7_1),
+ PINMUX_IPSR_MODSEL_DATA(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
+ PINMUX_IPSR_MODSEL_DATA(IP4_4_2, GLO_I0_D, SEL_GPS_3),
+ PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SSI_WS1, SEL_SSI1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL1_B, SEL_IIC1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL8_B, SEL_IIC8_1),
+ PINMUX_IPSR_MODSEL_DATA(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
+ PINMUX_IPSR_MODSEL_DATA(IP4_7_5, GLO_I1_D, SEL_GPS_3),
+ PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA1_B, SEL_IIC1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA8_B, SEL_IIC8_1),
+ PINMUX_IPSR_MODSEL_DATA(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
+ PINMUX_IPSR_DATA(IP4_12_10, SSI_SCK2),
+ PINMUX_IPSR_MODSEL_DATA(IP4_12_10, SCL2, SEL_IIC2_0),
+ PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
+ PINMUX_IPSR_DATA(IP4_15_13, SSI_WS2),
+ PINMUX_IPSR_MODSEL_DATA(IP4_15_13, SDA2, SEL_IIC2_0),
+ PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP4_15_13, RX2_E, SEL_SCIF2_4),
+ PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
+ PINMUX_IPSR_DATA(IP4_18_16, SSI_SDATA2),
+ PINMUX_IPSR_MODSEL_DATA(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP4_18_16, TX2_E, SEL_SCIF2_4),
+ PINMUX_IPSR_DATA(IP4_19, SSI_SCK34),
+ PINMUX_IPSR_DATA(IP4_20, SSI_WS34),
+ PINMUX_IPSR_DATA(IP4_21, SSI_SDATA3),
+ PINMUX_IPSR_DATA(IP4_23_22, SSI_SCK4),
+ PINMUX_IPSR_MODSEL_DATA(IP4_23_22, GLO_SS_D, SEL_GPS_3),
+ PINMUX_IPSR_DATA(IP4_25_24, SSI_WS4),
+ PINMUX_IPSR_MODSEL_DATA(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
+ PINMUX_IPSR_DATA(IP4_27_26, SSI_SDATA4),
+ PINMUX_IPSR_MODSEL_DATA(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
+ PINMUX_IPSR_DATA(IP4_30_28, SSI_SCK5),
+ PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP4_30_28, GLO_I0, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
+ PINMUX_IPSR_DATA(IP4_30_28, VI1_R2_B),
+
+ /* IPSR5 */
+ PINMUX_IPSR_DATA(IP5_2_0, SSI_WS5),
+ PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP5_2_0, GLO_I1, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
+ PINMUX_IPSR_DATA(IP5_2_0, VI1_R3_B),
+ PINMUX_IPSR_DATA(IP5_5_3, SSI_SDATA5),
+ PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP5_5_3, GLO_Q0, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
+ PINMUX_IPSR_DATA(IP5_5_3, VI1_R4_B),
+ PINMUX_IPSR_DATA(IP5_8_6, SSI_SCK6),
+ PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP5_8_6, GLO_Q1, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
+ PINMUX_IPSR_DATA(IP5_8_6, VI1_R5_B),
+ PINMUX_IPSR_DATA(IP5_11_9, SSI_WS6),
+ PINMUX_IPSR_MODSEL_DATA(IP5_11_9, GLO_SCLK, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
+ PINMUX_IPSR_DATA(IP5_11_9, VI1_R6_B),
+ PINMUX_IPSR_DATA(IP5_14_12, SSI_SDATA6),
+ PINMUX_IPSR_MODSEL_DATA(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MODSEL_DATA(IP5_14_12, GLO_SDATA, SEL_GPS_0),
+ PINMUX_IPSR_DATA(IP5_14_12, VI1_R7_B),
+ PINMUX_IPSR_MODSEL_DATA(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
+ PINMUX_IPSR_MODSEL_DATA(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MODSEL_DATA(IP5_16_15, GLO_SS, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP5_19_17, SSI_WS78, SEL_SSI7_0),
+ PINMUX_IPSR_MODSEL_DATA(IP5_19_17, TX0_D, SEL_SCIF0_3),
+ PINMUX_IPSR_MODSEL_DATA(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MODSEL_DATA(IP5_19_17, GLO_RFON, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
+ PINMUX_IPSR_MODSEL_DATA(IP5_21_20, RX0_D, SEL_SCIF0_3),
+ PINMUX_IPSR_MODSEL_DATA(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MODSEL_DATA(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
+ PINMUX_IPSR_MODSEL_DATA(IP5_23_22, TX1_D, SEL_SCIF1_3),
+ PINMUX_IPSR_MODSEL_DATA(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MODSEL_DATA(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
+ PINMUX_IPSR_MODSEL_DATA(IP5_25_24, RX1_D, SEL_SCIF1_3),
+ PINMUX_IPSR_MODSEL_DATA(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
+ PINMUX_IPSR_MODSEL_DATA(IP5_28_26, SSI_WS9, SEL_SSI9_0),
+ PINMUX_IPSR_MODSEL_DATA(IP5_28_26, TX3_D, SEL_SCIF3_3),
+ PINMUX_IPSR_MODSEL_DATA(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
+ PINMUX_IPSR_MODSEL_DATA(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
+ PINMUX_IPSR_MODSEL_DATA(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
+ PINMUX_IPSR_MODSEL_DATA(IP5_31_29, RX3_D, SEL_SCIF3_3),
+ PINMUX_IPSR_MODSEL_DATA(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
+
+ /* IPSR6 */
+ PINMUX_IPSR_MODSEL_DATA(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
+ PINMUX_IPSR_MODSEL_DATA(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
+ PINMUX_IPSR_MODSEL_DATA(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
+ PINMUX_IPSR_MODSEL_DATA(IP6_2_0, BPFCLK_E, SEL_FM_4),
+ PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC),
+ PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
+ PINMUX_IPSR_MODSEL_DATA(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP6_5_3, RX2, SEL_SCIF2_0),
+ PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
+ PINMUX_IPSR_MODSEL_DATA(IP6_5_3, FMIN_E, SEL_FM_4),
+ PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT),
+ PINMUX_IPSR_MODSEL_DATA(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TX2, SEL_SCIF2_0),
+ PINMUX_IPSR_MODSEL_DATA(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
+ PINMUX_IPSR_DATA(IP6_9_8, IRQ0),
+ PINMUX_IPSR_MODSEL_DATA(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
+ PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N),
+ PINMUX_IPSR_DATA(IP6_11_10, IRQ1),
+ PINMUX_IPSR_MODSEL_DATA(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
+ PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N),
+ PINMUX_IPSR_DATA(IP6_13_12, IRQ2),
+ PINMUX_IPSR_MODSEL_DATA(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
+ PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N),
+ PINMUX_IPSR_DATA(IP6_15_14, IRQ3),
+ PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCL4_C, SEL_IIC4_2),
+ PINMUX_IPSR_MODSEL_DATA(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
+ PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N),
+ PINMUX_IPSR_DATA(IP6_18_16, IRQ4),
+ PINMUX_IPSR_MODSEL_DATA(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP6_18_16, SDA4_C, SEL_IIC4_2),
+ PINMUX_IPSR_MODSEL_DATA(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
+ PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N),
+ PINMUX_IPSR_DATA(IP6_20_19, IRQ5),
+ PINMUX_IPSR_MODSEL_DATA(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP6_20_19, SCL1_E, SEL_IIC1_4),
+ PINMUX_IPSR_MODSEL_DATA(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
+ PINMUX_IPSR_DATA(IP6_23_21, IRQ6),
+ PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP6_23_21, SDA1_E, SEL_IIC1_4),
+ PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
+ PINMUX_IPSR_DATA(IP6_26_24, IRQ7),
+ PINMUX_IPSR_MODSEL_DATA(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
+ PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
+ PINMUX_IPSR_DATA(IP6_29_27, IRQ8),
+ PINMUX_IPSR_MODSEL_DATA(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
+ PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
+
+ /* IPSR7 */
+ PINMUX_IPSR_DATA(IP7_2_0, IRQ9),
+ PINMUX_IPSR_MODSEL_DATA(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
+ PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
+ PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
+ PINMUX_IPSR_DATA(IP7_5_3, DU1_DR0),
+ PINMUX_IPSR_DATA(IP7_5_3, LCDOUT0),
+ PINMUX_IPSR_MODSEL_DATA(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_5_3, TX0_B, SEL_SCIF0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
+ PINMUX_IPSR_DATA(IP7_8_6, DU1_DR1),
+ PINMUX_IPSR_DATA(IP7_8_6, LCDOUT1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RX0_B, SEL_SCIF0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
+ PINMUX_IPSR_DATA(IP7_10_9, DU1_DR2),
+ PINMUX_IPSR_DATA(IP7_10_9, LCDOUT2),
+ PINMUX_IPSR_MODSEL_DATA(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
+ PINMUX_IPSR_DATA(IP7_12_11, DU1_DR3),
+ PINMUX_IPSR_DATA(IP7_12_11, LCDOUT3),
+ PINMUX_IPSR_MODSEL_DATA(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
+ PINMUX_IPSR_DATA(IP7_14_13, DU1_DR4),
+ PINMUX_IPSR_DATA(IP7_14_13, LCDOUT4),
+ PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
+ PINMUX_IPSR_DATA(IP7_16_15, DU1_DR5),
+ PINMUX_IPSR_DATA(IP7_16_15, LCDOUT5),
+ PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
+ PINMUX_IPSR_DATA(IP7_18_17, DU1_DR6),
+ PINMUX_IPSR_DATA(IP7_18_17, LCDOUT6),
+ PINMUX_IPSR_MODSEL_DATA(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
+ PINMUX_IPSR_DATA(IP7_20_19, DU1_DR7),
+ PINMUX_IPSR_DATA(IP7_20_19, LCDOUT7),
+ PINMUX_IPSR_MODSEL_DATA(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
+ PINMUX_IPSR_DATA(IP7_23_21, DU1_DG0),
+ PINMUX_IPSR_DATA(IP7_23_21, LCDOUT8),
+ PINMUX_IPSR_MODSEL_DATA(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TX1_B, SEL_SCIF1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
+ PINMUX_IPSR_DATA(IP7_26_24, DU1_DG1),
+ PINMUX_IPSR_DATA(IP7_26_24, LCDOUT9),
+ PINMUX_IPSR_MODSEL_DATA(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RX1_B, SEL_SCIF1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
+ PINMUX_IPSR_DATA(IP7_29_27, DU1_DG2),
+ PINMUX_IPSR_DATA(IP7_29_27, LCDOUT10),
+ PINMUX_IPSR_MODSEL_DATA(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
+ PINMUX_IPSR_DATA(IP7_29_27, SCIF1_SCK_B),
+ PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
+
+ /* IPSR8 */
+ PINMUX_IPSR_DATA(IP8_2_0, DU1_DG3),
+ PINMUX_IPSR_DATA(IP8_2_0, LCDOUT11),
+ PINMUX_IPSR_MODSEL_DATA(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
+ PINMUX_IPSR_DATA(IP8_5_3, DU1_DG4),
+ PINMUX_IPSR_DATA(IP8_5_3, LCDOUT12),
+ PINMUX_IPSR_MODSEL_DATA(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
+ PINMUX_IPSR_DATA(IP8_8_6, DU1_DG5),
+ PINMUX_IPSR_DATA(IP8_8_6, LCDOUT13),
+ PINMUX_IPSR_MODSEL_DATA(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
+ PINMUX_IPSR_DATA(IP8_11_9, DU1_DG6),
+ PINMUX_IPSR_DATA(IP8_11_9, LCDOUT14),
+ PINMUX_IPSR_MODSEL_DATA(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
+ PINMUX_IPSR_DATA(IP8_14_12, DU1_DG7),
+ PINMUX_IPSR_DATA(IP8_14_12, LCDOUT15),
+ PINMUX_IPSR_MODSEL_DATA(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
+ PINMUX_IPSR_DATA(IP8_17_15, DU1_DB0),
+ PINMUX_IPSR_DATA(IP8_17_15, LCDOUT16),
+ PINMUX_IPSR_MODSEL_DATA(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_17_15, TX2_B, SEL_SCIF2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
+ PINMUX_IPSR_DATA(IP8_20_18, DU1_DB1),
+ PINMUX_IPSR_DATA(IP8_20_18, LCDOUT17),
+ PINMUX_IPSR_MODSEL_DATA(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_20_18, RX2_B, SEL_SCIF2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
+ PINMUX_IPSR_DATA(IP8_23_21, DU1_DB2),
+ PINMUX_IPSR_DATA(IP8_23_21, LCDOUT18),
+ PINMUX_IPSR_MODSEL_DATA(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
+ PINMUX_IPSR_DATA(IP8_23_21, SCIF2_SCK_B),
+ PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
+ PINMUX_IPSR_DATA(IP8_25_24, DU1_DB3),
+ PINMUX_IPSR_DATA(IP8_25_24, LCDOUT19),
+ PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
+ PINMUX_IPSR_DATA(IP8_27_26, DU1_DB4),
+ PINMUX_IPSR_DATA(IP8_27_26, LCDOUT20),
+ PINMUX_IPSR_MODSEL_DATA(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_27_26, CAN1_RX, SEL_CAN1_0),
+ PINMUX_IPSR_DATA(IP8_30_28, DU1_DB5),
+ PINMUX_IPSR_DATA(IP8_30_28, LCDOUT21),
+ PINMUX_IPSR_MODSEL_DATA(IP8_30_28, TX3, SEL_SCIF3_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_30_28, CAN1_TX, SEL_CAN1_0),
+
+ /* IPSR9 */
+ PINMUX_IPSR_DATA(IP9_2_0, DU1_DB6),
+ PINMUX_IPSR_DATA(IP9_2_0, LCDOUT22),
+ PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCL3_C, SEL_IIC3_2),
+ PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RX3, SEL_SCIF3_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
+ PINMUX_IPSR_DATA(IP9_5_3, DU1_DB7),
+ PINMUX_IPSR_DATA(IP9_5_3, LCDOUT23),
+ PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SDA3_C, SEL_IIC3_2),
+ PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
+ PINMUX_IPSR_DATA(IP9_6, QSTVA_QVS),
+ PINMUX_IPSR_DATA(IP9_7, DU1_DOTCLKOUT0),
+ PINMUX_IPSR_DATA(IP9_7, QCLK),
+ PINMUX_IPSR_DATA(IP9_10_8, DU1_DOTCLKOUT1),
+ PINMUX_IPSR_DATA(IP9_10_8, QSTVB_QVE),
+ PINMUX_IPSR_MODSEL_DATA(IP9_10_8, CAN0_TX, SEL_CAN0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_10_8, TX3_B, SEL_SCIF3_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_10_8, SCL2_B, SEL_IIC2_1),
+ PINMUX_IPSR_DATA(IP9_10_8, PWM4),
+ PINMUX_IPSR_DATA(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
+ PINMUX_IPSR_DATA(IP9_11, QSTH_QHS),
+ PINMUX_IPSR_DATA(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
+ PINMUX_IPSR_DATA(IP9_12, QSTB_QHE),
+ PINMUX_IPSR_DATA(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
+ PINMUX_IPSR_DATA(IP9_15_13, QCPV_QDE),
+ PINMUX_IPSR_MODSEL_DATA(IP9_15_13, CAN0_RX, SEL_CAN0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_15_13, RX3_B, SEL_SCIF3_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_15_13, SDA2_B, SEL_IIC2_1),
+ PINMUX_IPSR_DATA(IP9_16, DU1_DISP),
+ PINMUX_IPSR_DATA(IP9_16, QPOLA),
+ PINMUX_IPSR_DATA(IP9_18_17, DU1_CDE),
+ PINMUX_IPSR_DATA(IP9_18_17, QPOLB),
+ PINMUX_IPSR_DATA(IP9_18_17, PWM4_B),
+ PINMUX_IPSR_DATA(IP9_20_19, VI0_CLKENB),
+ PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TX4, SEL_SCIF4_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_DATA(IP9_22_21, VI0_FIELD),
+ PINMUX_IPSR_MODSEL_DATA(IP9_22_21, RX4, SEL_SCIF4_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_DATA(IP9_24_23, VI0_HSYNC_N),
+ PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TX5, SEL_SCIF5_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_DATA(IP9_26_25, VI0_VSYNC_N),
+ PINMUX_IPSR_MODSEL_DATA(IP9_26_25, RX5, SEL_SCIF5_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
+ PINMUX_IPSR_DATA(IP9_28_27, VI0_DATA3_VI0_B3),
+ PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
+ PINMUX_IPSR_DATA(IP9_31_29, VI0_G0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL8, SEL_IIC8_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
+ PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL4, SEL_IIC4_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
+ PINMUX_IPSR_DATA(IP9_31_29, ATAWR1_N),
+
+ /* IPSR10 */
+ PINMUX_IPSR_DATA(IP10_2_0, VI0_G1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA8, SEL_IIC8_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA4, SEL_IIC4_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
+ PINMUX_IPSR_DATA(IP10_2_0, ATADIR1_N),
+ PINMUX_IPSR_DATA(IP10_5_3, VI0_G2),
+ PINMUX_IPSR_DATA(IP10_5_3, VI2_HSYNC_N),
+ PINMUX_IPSR_MODSEL_DATA(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCL3_B, SEL_IIC3_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_5_3, HSCK2, SEL_HSCIF2_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
+ PINMUX_IPSR_DATA(IP10_5_3, ATARD1_N),
+ PINMUX_IPSR_DATA(IP10_8_6, VI0_G3),
+ PINMUX_IPSR_DATA(IP10_8_6, VI2_VSYNC_N),
+ PINMUX_IPSR_MODSEL_DATA(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SDA3_B, SEL_IIC3_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_8_6, HRX2, SEL_HSCIF2_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
+ PINMUX_IPSR_DATA(IP10_8_6, ATACS01_N),
+ PINMUX_IPSR_DATA(IP10_11_9, VI0_G4),
+ PINMUX_IPSR_DATA(IP10_11_9, VI2_CLKENB),
+ PINMUX_IPSR_MODSEL_DATA(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_11_9, HTX2, SEL_HSCIF2_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
+ PINMUX_IPSR_DATA(IP10_14_12, VI0_G5),
+ PINMUX_IPSR_DATA(IP10_14_12, VI2_FIELD),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_12, FMCLK_D, SEL_FM_3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
+ PINMUX_IPSR_DATA(IP10_16_15, VI0_G6),
+ PINMUX_IPSR_DATA(IP10_16_15, VI2_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP10_16_15, BPFCLK_D, SEL_FM_3),
+ PINMUX_IPSR_DATA(IP10_18_17, VI0_G7),
+ PINMUX_IPSR_DATA(IP10_18_17, VI2_DATA0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_18_17, FMIN_D, SEL_FM_3),
+ PINMUX_IPSR_DATA(IP10_21_19, VI0_R0),
+ PINMUX_IPSR_DATA(IP10_21_19, VI2_DATA1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_21_19, GLO_I0_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_DATA(IP10_21_19, ATACS11_N),
+ PINMUX_IPSR_DATA(IP10_24_22, VI0_R1),
+ PINMUX_IPSR_DATA(IP10_24_22, VI2_DATA2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_24_22, GLO_I1_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_DATA(IP10_24_22, ATAG1_N),
+ PINMUX_IPSR_DATA(IP10_26_25, VI0_R2),
+ PINMUX_IPSR_DATA(IP10_26_25, VI2_DATA3),
+ PINMUX_IPSR_MODSEL_DATA(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_DATA(IP10_28_27, VI0_R3),
+ PINMUX_IPSR_DATA(IP10_28_27, VI2_DATA4),
+ PINMUX_IPSR_MODSEL_DATA(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
+ PINMUX_IPSR_DATA(IP10_31_29, VI0_R4),
+ PINMUX_IPSR_DATA(IP10_31_29, VI2_DATA5),
+ PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_31_29, TX0_C, SEL_SCIF0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL1_D, SEL_IIC1_3),
+
+ /* IPSR11 */
+ PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
+ PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
+ PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3),
+ PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
+ PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
+ PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1),
+ PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
+ PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
+ PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
+ PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
+ PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
+ PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
+ PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
+ PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
+ PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0),
+ PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
+ PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0),
+ PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
+ PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0),
+ PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
+ PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0),
+ PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
+ PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0),
+ PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
+ PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0),
+ PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
+ PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0),
+ PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
+ PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0),
+ PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
+ PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0),
+ PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
+ PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0),
+ PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
+ PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
+ PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2),
+ PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
+ PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
+ PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2),
+
+ /* IPSR12 */
+ PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
+ PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
+ PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0),
+ PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0),
+ PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
+ PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
+ PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0),
+ PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0),
+ PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
+ PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
+ PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3),
+ PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
+ PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
+ PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
+ PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3),
+ PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
+ PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
+ PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
+ PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
+ PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
+ PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
+ PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
+ PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
+ PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
+ PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
+ PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
+ PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
+ PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
+ PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
+ PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2),
+ PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
+ PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
+ PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2),
+ PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
+ PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
+ PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2),
+ PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
+ PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
+ PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
+ PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1),
+ PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
+ PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
+ PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
+ PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
+ PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
+
+ /* IPSR13 */
+ PINMUX_IPSR_MODSEL_DATA(IP13_2_0, STP_ISD_0, SEL_SSP_0),
+ PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER),
+ PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
+ PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ADICLK_B, SEL_RAD_1),
+ PINMUX_IPSR_MODSEL_DATA(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
+ PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP13_4_3, ADICHS0_B, SEL_RAD_1),
+ PINMUX_IPSR_MODSEL_DATA(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
+ PINMUX_IPSR_DATA(IP13_6_5, AVB_COL),
+ PINMUX_IPSR_MODSEL_DATA(IP13_6_5, ADICHS1_B, SEL_RAD_1),
+ PINMUX_IPSR_MODSEL_DATA(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
+ PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK),
+ PINMUX_IPSR_DATA(IP13_9_7, PWM0_B),
+ PINMUX_IPSR_MODSEL_DATA(IP13_9_7, ADICHS2_B, SEL_RAD_1),
+ PINMUX_IPSR_MODSEL_DATA(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
+ PINMUX_IPSR_DATA(IP13_10, SD0_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP13_10, SPCLK_B, SEL_QSP_1),
+ PINMUX_IPSR_DATA(IP13_11, SD0_CMD),
+ PINMUX_IPSR_MODSEL_DATA(IP13_11, MOSI_IO0_B, SEL_QSP_1),
+ PINMUX_IPSR_DATA(IP13_12, SD0_DATA0),
+ PINMUX_IPSR_MODSEL_DATA(IP13_12, MISO_IO1_B, SEL_QSP_1),
+ PINMUX_IPSR_DATA(IP13_13, SD0_DATA1),
+ PINMUX_IPSR_MODSEL_DATA(IP13_13, IO2_B, SEL_QSP_1),
+ PINMUX_IPSR_DATA(IP13_14, SD0_DATA2),
+ PINMUX_IPSR_MODSEL_DATA(IP13_14, IO3_B, SEL_QSP_1),
+ PINMUX_IPSR_DATA(IP13_15, SD0_DATA3),
+ PINMUX_IPSR_MODSEL_DATA(IP13_15, SSL_B, SEL_QSP_1),
+ PINMUX_IPSR_DATA(IP13_18_16, SD0_CD),
+ PINMUX_IPSR_MODSEL_DATA(IP13_18_16, MMC_D6_B, SEL_MMC_1),
+ PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
+ PINMUX_IPSR_MODSEL_DATA(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
+ PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
+ PINMUX_IPSR_MODSEL_DATA(IP13_18_16, TX3_C, SEL_SCIF3_2),
+ PINMUX_IPSR_DATA(IP13_21_19, SD0_WP),
+ PINMUX_IPSR_MODSEL_DATA(IP13_21_19, MMC_D7_B, SEL_MMC_1),
+ PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SIM0_D_B, SEL_SIM_1),
+ PINMUX_IPSR_MODSEL_DATA(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
+ PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
+ PINMUX_IPSR_MODSEL_DATA(IP13_21_19, RX3_C, SEL_SCIF3_2),
+ PINMUX_IPSR_DATA(IP13_22, SD1_CMD),
+ PINMUX_IPSR_MODSEL_DATA(IP13_22, REMOCON_B, SEL_RCN_1),
+ PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0),
+ PINMUX_IPSR_MODSEL_DATA(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
+ PINMUX_IPSR_DATA(IP13_25, SD1_DATA1),
+ PINMUX_IPSR_MODSEL_DATA(IP13_25, IETX_B, SEL_IEB_1),
+ PINMUX_IPSR_DATA(IP13_26, SD1_DATA2),
+ PINMUX_IPSR_MODSEL_DATA(IP13_26, IECLK_B, SEL_IEB_1),
+ PINMUX_IPSR_DATA(IP13_27, SD1_DATA3),
+ PINMUX_IPSR_MODSEL_DATA(IP13_27, IERX_B, SEL_IEB_1),
+ PINMUX_IPSR_DATA(IP13_30_28, SD1_CD),
+ PINMUX_IPSR_DATA(IP13_30_28, PWM0),
+ PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0),
+ PINMUX_IPSR_MODSEL_DATA(IP13_30_28, SCL1_C, SEL_IIC1_2),
+
+ /* IPSR14 */
+ PINMUX_IPSR_DATA(IP14_1_0, SD1_WP),
+ PINMUX_IPSR_DATA(IP14_1_0, PWM1_B),
+ PINMUX_IPSR_MODSEL_DATA(IP14_1_0, SDA1_C, SEL_IIC1_2),
+ PINMUX_IPSR_DATA(IP14_2, SD2_CLK),
+ PINMUX_IPSR_DATA(IP14_2, MMC_CLK),
+ PINMUX_IPSR_DATA(IP14_3, SD2_CMD),
+ PINMUX_IPSR_DATA(IP14_3, MMC_CMD),
+ PINMUX_IPSR_DATA(IP14_4, SD2_DATA0),
+ PINMUX_IPSR_DATA(IP14_4, MMC_D0),
+ PINMUX_IPSR_DATA(IP14_5, SD2_DATA1),
+ PINMUX_IPSR_DATA(IP14_5, MMC_D1),
+ PINMUX_IPSR_DATA(IP14_6, SD2_DATA2),
+ PINMUX_IPSR_DATA(IP14_6, MMC_D2),
+ PINMUX_IPSR_DATA(IP14_7, SD2_DATA3),
+ PINMUX_IPSR_DATA(IP14_7, MMC_D3),
+ PINMUX_IPSR_DATA(IP14_10_8, SD2_CD),
+ PINMUX_IPSR_DATA(IP14_10_8, MMC_D4),
+ PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCL8_C, SEL_IIC8_2),
+ PINMUX_IPSR_MODSEL_DATA(IP14_10_8, TX5_B, SEL_SCIF5_1),
+ PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
+ PINMUX_IPSR_DATA(IP14_13_11, SD2_WP),
+ PINMUX_IPSR_DATA(IP14_13_11, MMC_D5),
+ PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SDA8_C, SEL_IIC8_2),
+ PINMUX_IPSR_MODSEL_DATA(IP14_13_11, RX5_B, SEL_SCIF5_1),
+ PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
+ PINMUX_IPSR_MODSEL_DATA(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP14_16_14, RX2_C, SEL_SCIF2_2),
+ PINMUX_IPSR_MODSEL_DATA(IP14_16_14, ADIDATA, SEL_RAD_0),
+ PINMUX_IPSR_MODSEL_DATA(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
+ PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B),
+ PINMUX_IPSR_MODSEL_DATA(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP14_19_17, TX2_C, SEL_SCIF2_2),
+ PINMUX_IPSR_MODSEL_DATA(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
+ PINMUX_IPSR_MODSEL_DATA(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
+ PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B),
+ PINMUX_IPSR_MODSEL_DATA(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP14_22_20, ADICLK, SEL_RAD_0),
+ PINMUX_IPSR_MODSEL_DATA(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
+ PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B),
+ PINMUX_IPSR_MODSEL_DATA(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP14_25_23, ADICHS0, SEL_RAD_0),
+ PINMUX_IPSR_MODSEL_DATA(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
+ PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B),
+ PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MMC_D6, SEL_MMC_0),
+ PINMUX_IPSR_MODSEL_DATA(IP14_28_26, ADICHS1, SEL_RAD_0),
+ PINMUX_IPSR_MODSEL_DATA(IP14_28_26, TX0_E, SEL_SCIF0_4),
+ PINMUX_IPSR_MODSEL_DATA(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP14_28_26, SCL7_C, SEL_IIC7_2),
+ PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B),
+ PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MMC_D7, SEL_MMC_0),
+ PINMUX_IPSR_MODSEL_DATA(IP14_31_29, ADICHS2, SEL_RAD_0),
+ PINMUX_IPSR_MODSEL_DATA(IP14_31_29, RX0_E, SEL_SCIF0_4),
+ PINMUX_IPSR_MODSEL_DATA(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP14_31_29, SDA7_C, SEL_IIC7_2),
+ PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B),
+
+ /* IPSR15 */
+ PINMUX_IPSR_MODSEL_DATA(IP15_1_0, SIM0_RST, SEL_SIM_0),
+ PINMUX_IPSR_MODSEL_DATA(IP15_1_0, IETX, SEL_IEB_0),
+ PINMUX_IPSR_MODSEL_DATA(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
+ PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP15_3_2, IECLK, SEL_IEB_0),
+ PINMUX_IPSR_MODSEL_DATA(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
+ PINMUX_IPSR_MODSEL_DATA(IP15_5_4, SIM0_D, SEL_SIM_0),
+ PINMUX_IPSR_MODSEL_DATA(IP15_5_4, IERX, SEL_IEB_0),
+ PINMUX_IPSR_MODSEL_DATA(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
+ PINMUX_IPSR_MODSEL_DATA(IP15_8_6, GPS_CLK, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
+ PINMUX_IPSR_MODSEL_DATA(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
+ PINMUX_IPSR_DATA(IP15_8_6, PWM5_B),
+ PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
+ PINMUX_IPSR_MODSEL_DATA(IP15_11_9, GPS_SIGN, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TX4_C, SEL_SCIF4_2),
+ PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
+ PINMUX_IPSR_DATA(IP15_11_9, PWM5),
+ PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B),
+ PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
+ PINMUX_IPSR_MODSEL_DATA(IP15_14_12, GPS_MAG, SEL_GPS_0),
+ PINMUX_IPSR_MODSEL_DATA(IP15_14_12, RX4_C, SEL_SCIF4_2),
+ PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
+ PINMUX_IPSR_DATA(IP15_14_12, PWM6),
+ PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B),
+ PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
+ PINMUX_IPSR_MODSEL_DATA(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
+ PINMUX_IPSR_MODSEL_DATA(IP15_17_15, GLO_I0_C, SEL_GPS_2),
+ PINMUX_IPSR_MODSEL_DATA(IP15_17_15, TCLK1, SEL_TMU1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
+ PINMUX_IPSR_MODSEL_DATA(IP15_20_18, GLO_I1_C, SEL_GPS_2),
+ PINMUX_IPSR_MODSEL_DATA(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP15_23_21, HSCK0, SEL_HSCIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
+ PINMUX_IPSR_MODSEL_DATA(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
+ PINMUX_IPSR_MODSEL_DATA(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
+ PINMUX_IPSR_DATA(IP15_23_21, TCLK2),
+ PINMUX_IPSR_MODSEL_DATA(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP15_26_24, HRX0, SEL_HSCIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
+ PINMUX_IPSR_MODSEL_DATA(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
+ PINMUX_IPSR_MODSEL_DATA(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP15_29_27, HTX0, SEL_HSCIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
+ PINMUX_IPSR_MODSEL_DATA(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
+ PINMUX_IPSR_MODSEL_DATA(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
+
+ /* IPSR16 */
+ PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HRX1, SEL_HSCIF1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
+ PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B),
+ PINMUX_IPSR_MODSEL_DATA(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
+ PINMUX_IPSR_MODSEL_DATA(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HTX1, SEL_HSCIF1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
+ PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B),
+ PINMUX_IPSR_MODSEL_DATA(IP16_5_3, GLO_SS_C, SEL_GPS_2),
+ PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
+ PINMUX_IPSR_DATA(IP16_7_6, MLB_CK),
+ PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
+ PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
+ PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N),
+ PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG),
+ PINMUX_IPSR_MODSEL_DATA(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
+ PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N),
+ PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT),
+ PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
+};
+
+static struct sh_pfc_pin pinmux_pins[] = {
+ PINMUX_GPIO_GP_ALL(),
+};
+
+/* - DU --------------------------------------------------------------------- */
+static const unsigned int du_rgb666_pins[] = {
+ /* R[7:2], G[7:2], B[7:2] */
+ RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
+ RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
+ RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
+ RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
+};
+static const unsigned int du_rgb666_mux[] = {
+ DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
+ DU1_DR3_MARK, DU1_DR2_MARK,
+ DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
+ DU1_DG3_MARK, DU1_DG2_MARK,
+ DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
+ DU1_DB3_MARK, DU1_DB2_MARK,
+};
+static const unsigned int du_rgb888_pins[] = {
+ /* R[7:0], G[7:0], B[7:0] */
+ RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
+ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
+ RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
+ RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
+ RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
+ RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
+ RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
+};
+static const unsigned int du_rgb888_mux[] = {
+ DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
+ DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
+ DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
+ DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
+ DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
+ DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
+};
+static const unsigned int du_clk_out_0_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(3, 25),
+};
+static const unsigned int du_clk_out_0_mux[] = {
+ DU1_DOTCLKOUT0_MARK
+};
+static const unsigned int du_clk_out_1_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(3, 26),
+};
+static const unsigned int du_clk_out_1_mux[] = {
+ DU1_DOTCLKOUT1_MARK
+};
+static const unsigned int du_sync_1_pins[] = {
+ /* EXVSYNC/VSYNC, EXHSYNC/HSYNC, EXDISP/EXODDF/EXCDE */
+ RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
+};
+static const unsigned int du_sync_1_mux[] = {
+ DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
+ DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
+};
+static const unsigned int du_cde_disp_pins[] = {
+ /* CDE DISP */
+ RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
+};
+static const unsigned int du0_clk_in_pins[] = {
+ /* CLKIN */
+ RCAR_GP_PIN(6, 31),
+};
+static const unsigned int du0_clk_in_mux[] = {
+ DU0_DOTCLKIN_MARK
+};
+static const unsigned int du_cde_disp_mux[] = {
+ DU1_CDE_MARK, DU1_DISP_MARK
+};
+static const unsigned int du1_clk_in_pins[] = {
+ /* CLKIN */
+ RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19), RCAR_GP_PIN(3, 24),
+};
+static const unsigned int du1_clk_in_mux[] = {
+ DU1_DOTCLKIN_C_MARK, DU1_DOTCLKIN_B_MARK, DU1_DOTCLKIN_MARK
+};
+/* - ETH -------------------------------------------------------------------- */
+static const unsigned int eth_link_pins[] = {
+ /* LINK */
+ RCAR_GP_PIN(5, 18),
+};
+static const unsigned int eth_link_mux[] = {
+ ETH_LINK_MARK,
+};
+static const unsigned int eth_magic_pins[] = {
+ /* MAGIC */
+ RCAR_GP_PIN(5, 22),
+};
+static const unsigned int eth_magic_mux[] = {
+ ETH_MAGIC_MARK,
+};
+static const unsigned int eth_mdio_pins[] = {
+ /* MDC, MDIO */
+ RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
+};
+static const unsigned int eth_mdio_mux[] = {
+ ETH_MDC_MARK, ETH_MDIO_MARK,
+};
+static const unsigned int eth_rmii_pins[] = {
+ /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
+ RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
+ RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
+ RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
+};
+static const unsigned int eth_rmii_mux[] = {
+ ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
+ ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
+};
+/* - INTC ------------------------------------------------------------------- */
+static const unsigned int intc_irq0_pins[] = {
+ /* IRQ */
+ RCAR_GP_PIN(7, 10),
+};
+static const unsigned int intc_irq0_mux[] = {
+ IRQ0_MARK,
+};
+static const unsigned int intc_irq1_pins[] = {
+ /* IRQ */
+ RCAR_GP_PIN(7, 11),
+};
+static const unsigned int intc_irq1_mux[] = {
+ IRQ1_MARK,
+};
+static const unsigned int intc_irq2_pins[] = {
+ /* IRQ */
+ RCAR_GP_PIN(7, 12),
+};
+static const unsigned int intc_irq2_mux[] = {
+ IRQ2_MARK,
+};
+static const unsigned int intc_irq3_pins[] = {
+ /* IRQ */
+ RCAR_GP_PIN(7, 13),
+};
+static const unsigned int intc_irq3_mux[] = {
+ IRQ3_MARK,
+};
+/* - MMCIF ------------------------------------------------------------------ */
+static const unsigned int mmc_data1_pins[] = {
+ /* D[0] */
+ RCAR_GP_PIN(6, 18),
+};
+static const unsigned int mmc_data1_mux[] = {
+ MMC_D0_MARK,
+};
+static const unsigned int mmc_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
+ RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
+};
+static const unsigned int mmc_data4_mux[] = {
+ MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
+};
+static const unsigned int mmc_data8_pins[] = {
+ /* D[0:7] */
+ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
+ RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
+ RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
+ RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
+};
+static const unsigned int mmc_data8_mux[] = {
+ MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
+ MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
+};
+static const unsigned int mmc_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
+};
+static const unsigned int mmc_ctrl_mux[] = {
+ MMC_CLK_MARK, MMC_CMD_MARK,
+};
+/* - MSIOF0 ----------------------------------------------------------------- */
+static const unsigned int msiof0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(6, 24),
+};
+static const unsigned int msiof0_clk_mux[] = {
+ MSIOF0_SCK_MARK,
+};
+static const unsigned int msiof0_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(6, 25),
+};
+static const unsigned int msiof0_sync_mux[] = {
+ MSIOF0_SYNC_MARK,
+};
+static const unsigned int msiof0_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(6, 28),
+};
+static const unsigned int msiof0_ss1_mux[] = {
+ MSIOF0_SS1_MARK,
+};
+static const unsigned int msiof0_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(6, 29),
+};
+static const unsigned int msiof0_ss2_mux[] = {
+ MSIOF0_SS2_MARK,
+};
+static const unsigned int msiof0_rx_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(6, 27),
+};
+static const unsigned int msiof0_rx_mux[] = {
+ MSIOF0_RXD_MARK,
+};
+static const unsigned int msiof0_tx_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(6, 26),
+};
+static const unsigned int msiof0_tx_mux[] = {
+ MSIOF0_TXD_MARK,
+};
+/* - MSIOF1 ----------------------------------------------------------------- */
+static const unsigned int msiof1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 22),
+};
+static const unsigned int msiof1_clk_mux[] = {
+ MSIOF1_SCK_MARK,
+};
+static const unsigned int msiof1_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(0, 23),
+};
+static const unsigned int msiof1_sync_mux[] = {
+ MSIOF1_SYNC_MARK,
+};
+static const unsigned int msiof1_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(0, 24),
+};
+static const unsigned int msiof1_ss1_mux[] = {
+ MSIOF1_SS1_MARK,
+};
+static const unsigned int msiof1_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(0, 25),
+};
+static const unsigned int msiof1_ss2_mux[] = {
+ MSIOF1_SS2_MARK,
+};
+static const unsigned int msiof1_rx_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(0, 27),
+};
+static const unsigned int msiof1_rx_mux[] = {
+ MSIOF1_RXD_MARK,
+};
+static const unsigned int msiof1_tx_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(0, 26),
+};
+static const unsigned int msiof1_tx_mux[] = {
+ MSIOF1_TXD_MARK,
+};
+/* - MSIOF2 ----------------------------------------------------------------- */
+static const unsigned int msiof2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 13),
+};
+static const unsigned int msiof2_clk_mux[] = {
+ MSIOF2_SCK_MARK,
+};
+static const unsigned int msiof2_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(1, 14),
+};
+static const unsigned int msiof2_sync_mux[] = {
+ MSIOF2_SYNC_MARK,
+};
+static const unsigned int msiof2_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(1, 17),
+};
+static const unsigned int msiof2_ss1_mux[] = {
+ MSIOF2_SS1_MARK,
+};
+static const unsigned int msiof2_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(1, 18),
+};
+static const unsigned int msiof2_ss2_mux[] = {
+ MSIOF2_SS2_MARK,
+};
+static const unsigned int msiof2_rx_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(1, 16),
+};
+static const unsigned int msiof2_rx_mux[] = {
+ MSIOF2_RXD_MARK,
+};
+static const unsigned int msiof2_tx_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(1, 15),
+};
+static const unsigned int msiof2_tx_mux[] = {
+ MSIOF2_TXD_MARK,
+};
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int scif0_data_mux[] = {
+ RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
+};
+static const unsigned int scif0_data_b_mux[] = {
+ RX0_B_MARK, TX0_B_MARK,
+};
+static const unsigned int scif0_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
+};
+static const unsigned int scif0_data_c_mux[] = {
+ RX0_C_MARK, TX0_C_MARK,
+};
+static const unsigned int scif0_data_d_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
+};
+static const unsigned int scif0_data_d_mux[] = {
+ RX0_D_MARK, TX0_D_MARK,
+};
+static const unsigned int scif0_data_e_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
+};
+static const unsigned int scif0_data_e_mux[] = {
+ RX0_E_MARK, TX0_E_MARK,
+};
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
+};
+static const unsigned int scif1_data_mux[] = {
+ RX1_MARK, TX1_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
+};
+static const unsigned int scif1_data_b_mux[] = {
+ RX1_B_MARK, TX1_B_MARK,
+};
+static const unsigned int scif1_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 10),
+};
+static const unsigned int scif1_clk_b_mux[] = {
+ SCIF1_SCK_B_MARK,
+};
+static const unsigned int scif1_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
+};
+static const unsigned int scif1_data_c_mux[] = {
+ RX1_C_MARK, TX1_C_MARK,
+};
+static const unsigned int scif1_data_d_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
+};
+static const unsigned int scif1_data_d_mux[] = {
+ RX1_D_MARK, TX1_D_MARK,
+};
+/* - SCIF2 ------------------------------------------------------------------ */
+static const unsigned int scif2_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
+};
+static const unsigned int scif2_data_mux[] = {
+ RX2_MARK, TX2_MARK,
+};
+static const unsigned int scif2_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
+};
+static const unsigned int scif2_data_b_mux[] = {
+ RX2_B_MARK, TX2_B_MARK,
+};
+static const unsigned int scif2_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 18),
+};
+static const unsigned int scif2_clk_b_mux[] = {
+ SCIF2_SCK_B_MARK,
+};
+static const unsigned int scif2_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
+};
+static const unsigned int scif2_data_c_mux[] = {
+ RX2_C_MARK, TX2_C_MARK,
+};
+static const unsigned int scif2_data_e_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+};
+static const unsigned int scif2_data_e_mux[] = {
+ RX2_E_MARK, TX2_E_MARK,
+};
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
+};
+static const unsigned int scif3_data_mux[] = {
+ RX3_MARK, TX3_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 23),
+};
+static const unsigned int scif3_clk_mux[] = {
+ SCIF3_SCK_MARK,
+};
+static const unsigned int scif3_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
+};
+static const unsigned int scif3_data_b_mux[] = {
+ RX3_B_MARK, TX3_B_MARK,
+};
+static const unsigned int scif3_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 8),
+};
+static const unsigned int scif3_clk_b_mux[] = {
+ SCIF3_SCK_B_MARK,
+};
+static const unsigned int scif3_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
+};
+static const unsigned int scif3_data_c_mux[] = {
+ RX3_C_MARK, TX3_C_MARK,
+};
+static const unsigned int scif3_data_d_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
+};
+static const unsigned int scif3_data_d_mux[] = {
+ RX3_D_MARK, TX3_D_MARK,
+};
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
+};
+static const unsigned int scif4_data_mux[] = {
+ RX4_MARK, TX4_MARK,
+};
+static const unsigned int scif4_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
+};
+static const unsigned int scif4_data_b_mux[] = {
+ RX4_B_MARK, TX4_B_MARK,
+};
+static const unsigned int scif4_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
+};
+static const unsigned int scif4_data_c_mux[] = {
+ RX4_C_MARK, TX4_C_MARK,
+};
+/* - SCIF5 ------------------------------------------------------------------ */
+static const unsigned int scif5_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
+};
+static const unsigned int scif5_data_mux[] = {
+ RX5_MARK, TX5_MARK,
+};
+static const unsigned int scif5_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
+};
+static const unsigned int scif5_data_b_mux[] = {
+ RX5_B_MARK, TX5_B_MARK,
+};
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int scifa0_data_mux[] = {
+ SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
+};
+static const unsigned int scifa0_data_b_mux[] = {
+ SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
+};
+static const unsigned int scifa1_data_mux[] = {
+ SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 10),
+};
+static const unsigned int scifa1_clk_mux[] = {
+ SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
+};
+static const unsigned int scifa1_data_b_mux[] = {
+ SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
+};
+static const unsigned int scifa1_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 0),
+};
+static const unsigned int scifa1_clk_b_mux[] = {
+ SCIFA1_SCK_B_MARK,
+};
+static const unsigned int scifa1_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+};
+static const unsigned int scifa1_data_c_mux[] = {
+ SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
+};
+static const unsigned int scifa2_data_mux[] = {
+ SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
+};
+static const unsigned int scifa2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 18),
+};
+static const unsigned int scifa2_clk_mux[] = {
+ SCIFA2_SCK_MARK,
+};
+static const unsigned int scifa2_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
+};
+static const unsigned int scifa2_data_b_mux[] = {
+ SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
+};
+/* - SCIFA3 ----------------------------------------------------------------- */
+static const unsigned int scifa3_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
+};
+static const unsigned int scifa3_data_mux[] = {
+ SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
+};
+static const unsigned int scifa3_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 23),
+};
+static const unsigned int scifa3_clk_mux[] = {
+ SCIFA3_SCK_MARK,
+};
+static const unsigned int scifa3_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
+};
+static const unsigned int scifa3_data_b_mux[] = {
+ SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
+};
+static const unsigned int scifa3_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 8),
+};
+static const unsigned int scifa3_clk_b_mux[] = {
+ SCIFA3_SCK_B_MARK,
+};
+static const unsigned int scifa3_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
+};
+static const unsigned int scifa3_data_c_mux[] = {
+ SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
+};
+static const unsigned int scifa3_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(7, 22),
+};
+static const unsigned int scifa3_clk_c_mux[] = {
+ SCIFA3_SCK_C_MARK,
+};
+/* - SCIFA4 ----------------------------------------------------------------- */
+static const unsigned int scifa4_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
+};
+static const unsigned int scifa4_data_mux[] = {
+ SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
+};
+static const unsigned int scifa4_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
+};
+static const unsigned int scifa4_data_b_mux[] = {
+ SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
+};
+static const unsigned int scifa4_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
+};
+static const unsigned int scifa4_data_c_mux[] = {
+ SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
+};
+/* - SCIFA5 ----------------------------------------------------------------- */
+static const unsigned int scifa5_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
+};
+static const unsigned int scifa5_data_mux[] = {
+ SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
+};
+static const unsigned int scifa5_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
+};
+static const unsigned int scifa5_data_b_mux[] = {
+ SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
+};
+static const unsigned int scifa5_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
+};
+static const unsigned int scifa5_data_c_mux[] = {
+ SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
+};
+/* - SCIFB0 ----------------------------------------------------------------- */
+static const unsigned int scifb0_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
+};
+static const unsigned int scifb0_data_mux[] = {
+ SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
+};
+static const unsigned int scifb0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(7, 2),
+};
+static const unsigned int scifb0_clk_mux[] = {
+ SCIFB0_SCK_MARK,
+};
+static const unsigned int scifb0_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
+};
+static const unsigned int scifb0_ctrl_mux[] = {
+ SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
+};
+static const unsigned int scifb0_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
+};
+static const unsigned int scifb0_data_b_mux[] = {
+ SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
+};
+static const unsigned int scifb0_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 31),
+};
+static const unsigned int scifb0_clk_b_mux[] = {
+ SCIFB0_SCK_B_MARK,
+};
+static const unsigned int scifb0_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
+};
+static const unsigned int scifb0_ctrl_b_mux[] = {
+ SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
+};
+static const unsigned int scifb0_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+};
+static const unsigned int scifb0_data_c_mux[] = {
+ SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
+};
+static const unsigned int scifb0_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 30),
+};
+static const unsigned int scifb0_clk_c_mux[] = {
+ SCIFB0_SCK_C_MARK,
+};
+static const unsigned int scifb0_data_d_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
+};
+static const unsigned int scifb0_data_d_mux[] = {
+ SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
+};
+static const unsigned int scifb0_clk_d_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 17),
+};
+static const unsigned int scifb0_clk_d_mux[] = {
+ SCIFB0_SCK_D_MARK,
+};
+/* - SCIFB1 ----------------------------------------------------------------- */
+static const unsigned int scifb1_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
+};
+static const unsigned int scifb1_data_mux[] = {
+ SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
+};
+static const unsigned int scifb1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(7, 7),
+};
+static const unsigned int scifb1_clk_mux[] = {
+ SCIFB1_SCK_MARK,
+};
+static const unsigned int scifb1_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
+};
+static const unsigned int scifb1_ctrl_mux[] = {
+ SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
+};
+static const unsigned int scifb1_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
+};
+static const unsigned int scifb1_data_b_mux[] = {
+ SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
+};
+static const unsigned int scifb1_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 3),
+};
+static const unsigned int scifb1_clk_b_mux[] = {
+ SCIFB1_SCK_B_MARK,
+};
+static const unsigned int scifb1_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+};
+static const unsigned int scifb1_data_c_mux[] = {
+ SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
+};
+static const unsigned int scifb1_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(7, 11),
+};
+static const unsigned int scifb1_clk_c_mux[] = {
+ SCIFB1_SCK_C_MARK,
+};
+static const unsigned int scifb1_data_d_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
+};
+static const unsigned int scifb1_data_d_mux[] = {
+ SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
+};
+/* - SCIFB2 ----------------------------------------------------------------- */
+static const unsigned int scifb2_data_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
+};
+static const unsigned int scifb2_data_mux[] = {
+ SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
+};
+static const unsigned int scifb2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 15),
+};
+static const unsigned int scifb2_clk_mux[] = {
+ SCIFB2_SCK_MARK,
+};
+static const unsigned int scifb2_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
+};
+static const unsigned int scifb2_ctrl_mux[] = {
+ SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
+};
+static const unsigned int scifb2_data_b_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+};
+static const unsigned int scifb2_data_b_mux[] = {
+ SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
+};
+static const unsigned int scifb2_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 31),
+};
+static const unsigned int scifb2_clk_b_mux[] = {
+ SCIFB2_SCK_B_MARK,
+};
+static const unsigned int scifb2_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
+};
+static const unsigned int scifb2_ctrl_b_mux[] = {
+ SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
+};
+static const unsigned int scifb2_data_c_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+};
+static const unsigned int scifb2_data_c_mux[] = {
+ SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
+};
+static const unsigned int scifb2_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 27),
+};
+static const unsigned int scifb2_clk_c_mux[] = {
+ SCIFB2_SCK_C_MARK,
+};
+static const unsigned int scifb2_data_d_pins[] = {
+ /* RXD, TXD */
+ RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
+};
+static const unsigned int scifb2_data_d_mux[] = {
+ SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
+};
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(6, 2),
+};
+static const unsigned int sdhi0_data1_mux[] = {
+ SD0_DATA0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
+ RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
+};
+static const unsigned int sdhi0_data4_mux[] = {
+ SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+ SD0_CLK_MARK, SD0_CMD_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+ /* CD */
+ RCAR_GP_PIN(6, 6),
+};
+static const unsigned int sdhi0_cd_mux[] = {
+ SD0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+ /* WP */
+ RCAR_GP_PIN(6, 7),
+};
+static const unsigned int sdhi0_wp_mux[] = {
+ SD0_WP_MARK,
+};
+/* - SDHI1 ------------------------------------------------------------------ */
+static const unsigned int sdhi1_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(6, 10),
+};
+static const unsigned int sdhi1_data1_mux[] = {
+ SD1_DATA0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
+ RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
+};
+static const unsigned int sdhi1_data4_mux[] = {
+ SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+ SD1_CLK_MARK, SD1_CMD_MARK,
+};
+static const unsigned int sdhi1_cd_pins[] = {
+ /* CD */
+ RCAR_GP_PIN(6, 14),
+};
+static const unsigned int sdhi1_cd_mux[] = {
+ SD1_CD_MARK,
+};
+static const unsigned int sdhi1_wp_pins[] = {
+ /* WP */
+ RCAR_GP_PIN(6, 15),
+};
+static const unsigned int sdhi1_wp_mux[] = {
+ SD1_WP_MARK,
+};
+/* - SDHI2 ------------------------------------------------------------------ */
+static const unsigned int sdhi2_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(6, 18),
+};
+static const unsigned int sdhi2_data1_mux[] = {
+ SD2_DATA0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
+ RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
+};
+static const unsigned int sdhi2_data4_mux[] = {
+ SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+ SD2_CLK_MARK, SD2_CMD_MARK,
+};
+static const unsigned int sdhi2_cd_pins[] = {
+ /* CD */
+ RCAR_GP_PIN(6, 22),
+};
+static const unsigned int sdhi2_cd_mux[] = {
+ SD2_CD_MARK,
+};
+static const unsigned int sdhi2_wp_pins[] = {
+ /* WP */
+ RCAR_GP_PIN(6, 23),
+};
+static const unsigned int sdhi2_wp_mux[] = {
+ SD2_WP_MARK,
+};
+/* - USB0 ------------------------------------------------------------------- */
+static const unsigned int usb0_pwen_pins[] = {
+ /* PWEN */
+ RCAR_GP_PIN(7, 23),
+};
+static const unsigned int usb0_pwen_mux[] = {
+ USB0_PWEN_MARK,
+};
+static const unsigned int usb0_ovc_pins[] = {
+ /* OVC */
+ RCAR_GP_PIN(7, 24),
+};
+static const unsigned int usb0_ovc_mux[] = {
+ USB0_OVC_MARK,
+};
+/* - USB1 ------------------------------------------------------------------- */
+static const unsigned int usb1_pwen_pins[] = {
+ /* PWEN */
+ RCAR_GP_PIN(7, 25),
+};
+static const unsigned int usb1_pwen_mux[] = {
+ USB1_PWEN_MARK,
+};
+static const unsigned int usb1_ovc_pins[] = {
+ /* OVC */
+ RCAR_GP_PIN(6, 30),
+};
+static const unsigned int usb1_ovc_mux[] = {
+ USB1_OVC_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(du_rgb666),
+ SH_PFC_PIN_GROUP(du_rgb888),
+ SH_PFC_PIN_GROUP(du_clk_out_0),
+ SH_PFC_PIN_GROUP(du_clk_out_1),
+ SH_PFC_PIN_GROUP(du_sync_1),
+ SH_PFC_PIN_GROUP(du_cde_disp),
+ SH_PFC_PIN_GROUP(du0_clk_in),
+ SH_PFC_PIN_GROUP(du1_clk_in),
+ SH_PFC_PIN_GROUP(eth_link),
+ SH_PFC_PIN_GROUP(eth_magic),
+ SH_PFC_PIN_GROUP(eth_mdio),
+ SH_PFC_PIN_GROUP(eth_rmii),
+ SH_PFC_PIN_GROUP(intc_irq0),
+ SH_PFC_PIN_GROUP(intc_irq1),
+ SH_PFC_PIN_GROUP(intc_irq2),
+ SH_PFC_PIN_GROUP(intc_irq3),
+ SH_PFC_PIN_GROUP(mmc_data1),
+ SH_PFC_PIN_GROUP(mmc_data4),
+ SH_PFC_PIN_GROUP(mmc_data8),
+ SH_PFC_PIN_GROUP(mmc_ctrl),
+ SH_PFC_PIN_GROUP(msiof0_clk),
+ SH_PFC_PIN_GROUP(msiof0_sync),
+ SH_PFC_PIN_GROUP(msiof0_ss1),
+ SH_PFC_PIN_GROUP(msiof0_ss2),
+ SH_PFC_PIN_GROUP(msiof0_rx),
+ SH_PFC_PIN_GROUP(msiof0_tx),
+ SH_PFC_PIN_GROUP(msiof1_clk),
+ SH_PFC_PIN_GROUP(msiof1_sync),
+ SH_PFC_PIN_GROUP(msiof1_ss1),
+ SH_PFC_PIN_GROUP(msiof1_ss2),
+ SH_PFC_PIN_GROUP(msiof1_rx),
+ SH_PFC_PIN_GROUP(msiof1_tx),
+ SH_PFC_PIN_GROUP(msiof2_clk),
+ SH_PFC_PIN_GROUP(msiof2_sync),
+ SH_PFC_PIN_GROUP(msiof2_ss1),
+ SH_PFC_PIN_GROUP(msiof2_ss2),
+ SH_PFC_PIN_GROUP(msiof2_rx),
+ SH_PFC_PIN_GROUP(msiof2_tx),
+ SH_PFC_PIN_GROUP(scif0_data),
+ SH_PFC_PIN_GROUP(scif0_data_b),
+ SH_PFC_PIN_GROUP(scif0_data_c),
+ SH_PFC_PIN_GROUP(scif0_data_d),
+ SH_PFC_PIN_GROUP(scif0_data_e),
+ SH_PFC_PIN_GROUP(scif1_data),
+ SH_PFC_PIN_GROUP(scif1_data_b),
+ SH_PFC_PIN_GROUP(scif1_clk_b),
+ SH_PFC_PIN_GROUP(scif1_data_c),
+ SH_PFC_PIN_GROUP(scif1_data_d),
+ SH_PFC_PIN_GROUP(scif2_data),
+ SH_PFC_PIN_GROUP(scif2_data_b),
+ SH_PFC_PIN_GROUP(scif2_clk_b),
+ SH_PFC_PIN_GROUP(scif2_data_c),
+ SH_PFC_PIN_GROUP(scif2_data_e),
+ SH_PFC_PIN_GROUP(scif3_data),
+ SH_PFC_PIN_GROUP(scif3_clk),
+ SH_PFC_PIN_GROUP(scif3_data_b),
+ SH_PFC_PIN_GROUP(scif3_clk_b),
+ SH_PFC_PIN_GROUP(scif3_data_c),
+ SH_PFC_PIN_GROUP(scif3_data_d),
+ SH_PFC_PIN_GROUP(scif4_data),
+ SH_PFC_PIN_GROUP(scif4_data_b),
+ SH_PFC_PIN_GROUP(scif4_data_c),
+ SH_PFC_PIN_GROUP(scif5_data),
+ SH_PFC_PIN_GROUP(scif5_data_b),
+ SH_PFC_PIN_GROUP(scifa0_data),
+ SH_PFC_PIN_GROUP(scifa0_data_b),
+ SH_PFC_PIN_GROUP(scifa1_data),
+ SH_PFC_PIN_GROUP(scifa1_clk),
+ SH_PFC_PIN_GROUP(scifa1_data_b),
+ SH_PFC_PIN_GROUP(scifa1_clk_b),
+ SH_PFC_PIN_GROUP(scifa1_data_c),
+ SH_PFC_PIN_GROUP(scifa2_data),
+ SH_PFC_PIN_GROUP(scifa2_clk),
+ SH_PFC_PIN_GROUP(scifa2_data_b),
+ SH_PFC_PIN_GROUP(scifa3_data),
+ SH_PFC_PIN_GROUP(scifa3_clk),
+ SH_PFC_PIN_GROUP(scifa3_data_b),
+ SH_PFC_PIN_GROUP(scifa3_clk_b),
+ SH_PFC_PIN_GROUP(scifa3_data_c),
+ SH_PFC_PIN_GROUP(scifa3_clk_c),
+ SH_PFC_PIN_GROUP(scifa4_data),
+ SH_PFC_PIN_GROUP(scifa4_data_b),
+ SH_PFC_PIN_GROUP(scifa4_data_c),
+ SH_PFC_PIN_GROUP(scifa5_data),
+ SH_PFC_PIN_GROUP(scifa5_data_b),
+ SH_PFC_PIN_GROUP(scifa5_data_c),
+ SH_PFC_PIN_GROUP(scifb0_data),
+ SH_PFC_PIN_GROUP(scifb0_clk),
+ SH_PFC_PIN_GROUP(scifb0_ctrl),
+ SH_PFC_PIN_GROUP(scifb0_data_b),
+ SH_PFC_PIN_GROUP(scifb0_clk_b),
+ SH_PFC_PIN_GROUP(scifb0_ctrl_b),
+ SH_PFC_PIN_GROUP(scifb0_data_c),
+ SH_PFC_PIN_GROUP(scifb0_clk_c),
+ SH_PFC_PIN_GROUP(scifb0_data_d),
+ SH_PFC_PIN_GROUP(scifb0_clk_d),
+ SH_PFC_PIN_GROUP(scifb1_data),
+ SH_PFC_PIN_GROUP(scifb1_clk),
+ SH_PFC_PIN_GROUP(scifb1_ctrl),
+ SH_PFC_PIN_GROUP(scifb1_data_b),
+ SH_PFC_PIN_GROUP(scifb1_clk_b),
+ SH_PFC_PIN_GROUP(scifb1_data_c),
+ SH_PFC_PIN_GROUP(scifb1_clk_c),
+ SH_PFC_PIN_GROUP(scifb1_data_d),
+ SH_PFC_PIN_GROUP(scifb2_data),
+ SH_PFC_PIN_GROUP(scifb2_clk),
+ SH_PFC_PIN_GROUP(scifb2_ctrl),
+ SH_PFC_PIN_GROUP(scifb2_data_b),
+ SH_PFC_PIN_GROUP(scifb2_clk_b),
+ SH_PFC_PIN_GROUP(scifb2_ctrl_b),
+ SH_PFC_PIN_GROUP(scifb2_data_c),
+ SH_PFC_PIN_GROUP(scifb2_clk_c),
+ SH_PFC_PIN_GROUP(scifb2_data_d),
+ SH_PFC_PIN_GROUP(sdhi0_data1),
+ SH_PFC_PIN_GROUP(sdhi0_data4),
+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_cd),
+ SH_PFC_PIN_GROUP(sdhi0_wp),
+ SH_PFC_PIN_GROUP(sdhi1_data1),
+ SH_PFC_PIN_GROUP(sdhi1_data4),
+ SH_PFC_PIN_GROUP(sdhi1_ctrl),
+ SH_PFC_PIN_GROUP(sdhi1_cd),
+ SH_PFC_PIN_GROUP(sdhi1_wp),
+ SH_PFC_PIN_GROUP(sdhi2_data1),
+ SH_PFC_PIN_GROUP(sdhi2_data4),
+ SH_PFC_PIN_GROUP(sdhi2_ctrl),
+ SH_PFC_PIN_GROUP(sdhi2_cd),
+ SH_PFC_PIN_GROUP(sdhi2_wp),
+ SH_PFC_PIN_GROUP(usb0_pwen),
+ SH_PFC_PIN_GROUP(usb0_ovc),
+ SH_PFC_PIN_GROUP(usb1_pwen),
+ SH_PFC_PIN_GROUP(usb1_ovc),
+};
+
+static const char * const du_groups[] = {
+ "du_rgb666",
+ "du_rgb888",
+ "du_clk_out_0",
+ "du_clk_out_1",
+ "du_sync_1",
+ "du_cde_disp",
+};
+
+static const char * const du0_groups[] = {
+ "du0_clk_in",
+};
+
+static const char * const du1_groups[] = {
+ "du1_clk_in",
+};
+
+static const char * const eth_groups[] = {
+ "eth_link",
+ "eth_magic",
+ "eth_mdio",
+ "eth_rmii",
+};
+
+static const char * const intc_groups[] = {
+ "intc_irq0",
+ "intc_irq1",
+ "intc_irq2",
+ "intc_irq3",
+};
+
+static const char * const mmc_groups[] = {
+ "mmc_data1",
+ "mmc_data4",
+ "mmc_data8",
+ "mmc_ctrl",
+};
+
+static const char * const msiof0_groups[] = {
+ "msiof0_clk",
+ "msiof0_ctrl",
+ "msiof0_data",
+};
+
+static const char * const msiof1_groups[] = {
+ "msiof1_clk",
+ "msiof1_ctrl",
+ "msiof1_data",
+};
+
+static const char * const msiof2_groups[] = {
+ "msiof2_clk",
+ "msiof2_ctrl",
+ "msiof2_data",
+};
+
+static const char * const scif0_groups[] = {
+ "scif0_data",
+ "scif0_data_b",
+ "scif0_data_c",
+ "scif0_data_d",
+ "scif0_data_e",
+};
+
+static const char * const scif1_groups[] = {
+ "scif1_data",
+ "scif1_data_b",
+ "scif1_clk_b",
+ "scif1_data_c",
+ "scif1_data_d",
+};
+
+static const char * const scif2_groups[] = {
+ "scif2_data",
+ "scif2_data_b",
+ "scif2_clk_b",
+ "scif2_data_c",
+ "scif2_data_e",
+};
+static const char * const scif3_groups[] = {
+ "scif3_data",
+ "scif3_clk",
+ "scif3_data_b",
+ "scif3_clk_b",
+ "scif3_data_c",
+ "scif3_data_d",
+};
+static const char * const scif4_groups[] = {
+ "scif4_data",
+ "scif4_data_b",
+ "scif4_data_c",
+};
+static const char * const scif5_groups[] = {
+ "scif5_data",
+ "scif5_data_b",
+};
+static const char * const scifa0_groups[] = {
+ "scifa0_data",
+ "scifa0_data_b",
+};
+static const char * const scifa1_groups[] = {
+ "scifa1_data",
+ "scifa1_clk",
+ "scifa1_data_b",
+ "scifa1_clk_b",
+ "scifa1_data_c",
+};
+static const char * const scifa2_groups[] = {
+ "scifa2_data",
+ "scifa2_clk",
+ "scifa2_data_b",
+};
+static const char * const scifa3_groups[] = {
+ "scifa3_data",
+ "scifa3_clk",
+ "scifa3_data_b",
+ "scifa3_clk_b",
+ "scifa3_data_c",
+ "scifa3_clk_c",
+};
+static const char * const scifa4_groups[] = {
+ "scifa4_data",
+ "scifa4_data_b",
+ "scifa4_data_c",
+};
+static const char * const scifa5_groups[] = {
+ "scifa5_data",
+ "scifa5_data_b",
+ "scifa5_data_c",
+};
+static const char * const scifb0_groups[] = {
+ "scifb0_data",
+ "scifb0_clk",
+ "scifb0_ctrl",
+ "scifb0_data_b",
+ "scifb0_clk_b",
+ "scifb0_ctrl_b",
+ "scifb0_data_c",
+ "scifb0_clk_c",
+ "scifb0_data_d",
+ "scifb0_clk_d",
+};
+static const char * const scifb1_groups[] = {
+ "scifb1_data",
+ "scifb1_clk",
+ "scifb1_ctrl",
+ "scifb1_data_b",
+ "scifb1_clk_b",
+ "scifb1_data_c",
+ "scifb1_clk_c",
+ "scifb1_data_d",
+};
+static const char * const scifb2_groups[] = {
+ "scifb2_data",
+ "scifb2_clk",
+ "scifb2_ctrl",
+ "scifb2_data_b",
+ "scifb2_clk_b",
+ "scifb2_ctrl_b",
+ "scifb0_data_c",
+ "scifb2_clk_c",
+ "scifb2_data_d",
+};
+
+static const char * const sdhi0_groups[] = {
+ "sdhi0_data1",
+ "sdhi0_data4",
+ "sdhi0_ctrl",
+ "sdhi0_cd",
+ "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+ "sdhi1_data1",
+ "sdhi1_data4",
+ "sdhi1_ctrl",
+ "sdhi1_cd",
+ "sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+ "sdhi2_data1",
+ "sdhi2_data4",
+ "sdhi2_ctrl",
+ "sdhi2_cd",
+ "sdhi2_wp",
+};
+
+static const char * const usb0_groups[] = {
+ "usb0_pwen",
+ "usb0_ovc",
+};
+static const char * const usb1_groups[] = {
+ "usb1_pwen",
+ "usb1_ovc",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(du),
+ SH_PFC_FUNCTION(du0),
+ SH_PFC_FUNCTION(du1),
+ SH_PFC_FUNCTION(eth),
+ SH_PFC_FUNCTION(intc),
+ SH_PFC_FUNCTION(mmc),
+ SH_PFC_FUNCTION(msiof0),
+ SH_PFC_FUNCTION(msiof1),
+ SH_PFC_FUNCTION(msiof2),
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif2),
+ SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(scif4),
+ SH_PFC_FUNCTION(scif5),
+ SH_PFC_FUNCTION(scifa0),
+ SH_PFC_FUNCTION(scifa1),
+ SH_PFC_FUNCTION(scifa2),
+ SH_PFC_FUNCTION(scifa3),
+ SH_PFC_FUNCTION(scifa4),
+ SH_PFC_FUNCTION(scifa5),
+ SH_PFC_FUNCTION(scifb0),
+ SH_PFC_FUNCTION(scifb1),
+ SH_PFC_FUNCTION(scifb2),
+ SH_PFC_FUNCTION(sdhi0),
+ SH_PFC_FUNCTION(sdhi1),
+ SH_PFC_FUNCTION(sdhi2),
+ SH_PFC_FUNCTION(usb0),
+ SH_PFC_FUNCTION(usb1),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+ { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+ GP_0_31_FN, FN_IP1_22_20,
+ GP_0_30_FN, FN_IP1_19_17,
+ GP_0_29_FN, FN_IP1_16_14,
+ GP_0_28_FN, FN_IP1_13_11,
+ GP_0_27_FN, FN_IP1_10_8,
+ GP_0_26_FN, FN_IP1_7_6,
+ GP_0_25_FN, FN_IP1_5_4,
+ GP_0_24_FN, FN_IP1_3_2,
+ GP_0_23_FN, FN_IP1_1_0,
+ GP_0_22_FN, FN_IP0_30_29,
+ GP_0_21_FN, FN_IP0_28_27,
+ GP_0_20_FN, FN_IP0_26_25,
+ GP_0_19_FN, FN_IP0_24_23,
+ GP_0_18_FN, FN_IP0_22_21,
+ GP_0_17_FN, FN_IP0_20_19,
+ GP_0_16_FN, FN_IP0_18_16,
+ GP_0_15_FN, FN_IP0_15,
+ GP_0_14_FN, FN_IP0_14,
+ GP_0_13_FN, FN_IP0_13,
+ GP_0_12_FN, FN_IP0_12,
+ GP_0_11_FN, FN_IP0_11,
+ GP_0_10_FN, FN_IP0_10,
+ GP_0_9_FN, FN_IP0_9,
+ GP_0_8_FN, FN_IP0_8,
+ GP_0_7_FN, FN_IP0_7,
+ GP_0_6_FN, FN_IP0_6,
+ GP_0_5_FN, FN_IP0_5,
+ GP_0_4_FN, FN_IP0_4,
+ GP_0_3_FN, FN_IP0_3,
+ GP_0_2_FN, FN_IP0_2,
+ GP_0_1_FN, FN_IP0_1,
+ GP_0_0_FN, FN_IP0_0, }
+ },
+ { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_1_25_FN, FN_IP3_21_20,
+ GP_1_24_FN, FN_IP3_19_18,
+ GP_1_23_FN, FN_IP3_17_16,
+ GP_1_22_FN, FN_IP3_15_14,
+ GP_1_21_FN, FN_IP3_13_12,
+ GP_1_20_FN, FN_IP3_11_9,
+ GP_1_19_FN, FN_RD_N,
+ GP_1_18_FN, FN_IP3_8_6,
+ GP_1_17_FN, FN_IP3_5_3,
+ GP_1_16_FN, FN_IP3_2_0,
+ GP_1_15_FN, FN_IP2_29_27,
+ GP_1_14_FN, FN_IP2_26_25,
+ GP_1_13_FN, FN_IP2_24_23,
+ GP_1_12_FN, FN_EX_CS0_N,
+ GP_1_11_FN, FN_IP2_22_21,
+ GP_1_10_FN, FN_IP2_20_19,
+ GP_1_9_FN, FN_IP2_18_16,
+ GP_1_8_FN, FN_IP2_15_13,
+ GP_1_7_FN, FN_IP2_12_10,
+ GP_1_6_FN, FN_IP2_9_7,
+ GP_1_5_FN, FN_IP2_6_5,
+ GP_1_4_FN, FN_IP2_4_3,
+ GP_1_3_FN, FN_IP2_2_0,
+ GP_1_2_FN, FN_IP1_31_29,
+ GP_1_1_FN, FN_IP1_28_26,
+ GP_1_0_FN, FN_IP1_25_23, }
+ },
+ { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+ GP_2_31_FN, FN_IP6_7_6,
+ GP_2_30_FN, FN_IP6_5_3,
+ GP_2_29_FN, FN_IP6_2_0,
+ GP_2_28_FN, FN_AUDIO_CLKA,
+ GP_2_27_FN, FN_IP5_31_29,
+ GP_2_26_FN, FN_IP5_28_26,
+ GP_2_25_FN, FN_IP5_25_24,
+ GP_2_24_FN, FN_IP5_23_22,
+ GP_2_23_FN, FN_IP5_21_20,
+ GP_2_22_FN, FN_IP5_19_17,
+ GP_2_21_FN, FN_IP5_16_15,
+ GP_2_20_FN, FN_IP5_14_12,
+ GP_2_19_FN, FN_IP5_11_9,
+ GP_2_18_FN, FN_IP5_8_6,
+ GP_2_17_FN, FN_IP5_5_3,
+ GP_2_16_FN, FN_IP5_2_0,
+ GP_2_15_FN, FN_IP4_30_28,
+ GP_2_14_FN, FN_IP4_27_26,
+ GP_2_13_FN, FN_IP4_25_24,
+ GP_2_12_FN, FN_IP4_23_22,
+ GP_2_11_FN, FN_IP4_21,
+ GP_2_10_FN, FN_IP4_20,
+ GP_2_9_FN, FN_IP4_19,
+ GP_2_8_FN, FN_IP4_18_16,
+ GP_2_7_FN, FN_IP4_15_13,
+ GP_2_6_FN, FN_IP4_12_10,
+ GP_2_5_FN, FN_IP4_9_8,
+ GP_2_4_FN, FN_IP4_7_5,
+ GP_2_3_FN, FN_IP4_4_2,
+ GP_2_2_FN, FN_IP4_1_0,
+ GP_2_1_FN, FN_IP3_30_28,
+ GP_2_0_FN, FN_IP3_27_25 }
+ },
+ { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+ GP_3_31_FN, FN_IP9_18_17,
+ GP_3_30_FN, FN_IP9_16,
+ GP_3_29_FN, FN_IP9_15_13,
+ GP_3_28_FN, FN_IP9_12,
+ GP_3_27_FN, FN_IP9_11,
+ GP_3_26_FN, FN_IP9_10_8,
+ GP_3_25_FN, FN_IP9_7,
+ GP_3_24_FN, FN_IP9_6,
+ GP_3_23_FN, FN_IP9_5_3,
+ GP_3_22_FN, FN_IP9_2_0,
+ GP_3_21_FN, FN_IP8_30_28,
+ GP_3_20_FN, FN_IP8_27_26,
+ GP_3_19_FN, FN_IP8_25_24,
+ GP_3_18_FN, FN_IP8_23_21,
+ GP_3_17_FN, FN_IP8_20_18,
+ GP_3_16_FN, FN_IP8_17_15,
+ GP_3_15_FN, FN_IP8_14_12,
+ GP_3_14_FN, FN_IP8_11_9,
+ GP_3_13_FN, FN_IP8_8_6,
+ GP_3_12_FN, FN_IP8_5_3,
+ GP_3_11_FN, FN_IP8_2_0,
+ GP_3_10_FN, FN_IP7_29_27,
+ GP_3_9_FN, FN_IP7_26_24,
+ GP_3_8_FN, FN_IP7_23_21,
+ GP_3_7_FN, FN_IP7_20_19,
+ GP_3_6_FN, FN_IP7_18_17,
+ GP_3_5_FN, FN_IP7_16_15,
+ GP_3_4_FN, FN_IP7_14_13,
+ GP_3_3_FN, FN_IP7_12_11,
+ GP_3_2_FN, FN_IP7_10_9,
+ GP_3_1_FN, FN_IP7_8_6,
+ GP_3_0_FN, FN_IP7_5_3 }
+ },
+ { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+ GP_4_31_FN, FN_IP15_5_4,
+ GP_4_30_FN, FN_IP15_3_2,
+ GP_4_29_FN, FN_IP15_1_0,
+ GP_4_28_FN, FN_IP11_8_6,
+ GP_4_27_FN, FN_IP11_5_3,
+ GP_4_26_FN, FN_IP11_2_0,
+ GP_4_25_FN, FN_IP10_31_29,
+ GP_4_24_FN, FN_IP10_28_27,
+ GP_4_23_FN, FN_IP10_26_25,
+ GP_4_22_FN, FN_IP10_24_22,
+ GP_4_21_FN, FN_IP10_21_19,
+ GP_4_20_FN, FN_IP10_18_17,
+ GP_4_19_FN, FN_IP10_16_15,
+ GP_4_18_FN, FN_IP10_14_12,
+ GP_4_17_FN, FN_IP10_11_9,
+ GP_4_16_FN, FN_IP10_8_6,
+ GP_4_15_FN, FN_IP10_5_3,
+ GP_4_14_FN, FN_IP10_2_0,
+ GP_4_13_FN, FN_IP9_31_29,
+ GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
+ GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
+ GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
+ GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
+ GP_4_8_FN, FN_IP9_28_27,
+ GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
+ GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
+ GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
+ GP_4_4_FN, FN_IP9_26_25,
+ GP_4_3_FN, FN_IP9_24_23,
+ GP_4_2_FN, FN_IP9_22_21,
+ GP_4_1_FN, FN_IP9_20_19,
+ GP_4_0_FN, FN_VI0_CLK }
+ },
+ { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+ GP_5_31_FN, FN_IP3_24_22,
+ GP_5_30_FN, FN_IP13_9_7,
+ GP_5_29_FN, FN_IP13_6_5,
+ GP_5_28_FN, FN_IP13_4_3,
+ GP_5_27_FN, FN_IP13_2_0,
+ GP_5_26_FN, FN_IP12_29_27,
+ GP_5_25_FN, FN_IP12_26_24,
+ GP_5_24_FN, FN_IP12_23_22,
+ GP_5_23_FN, FN_IP12_21_20,
+ GP_5_22_FN, FN_IP12_19_18,
+ GP_5_21_FN, FN_IP12_17_16,
+ GP_5_20_FN, FN_IP12_15_13,
+ GP_5_19_FN, FN_IP12_12_10,
+ GP_5_18_FN, FN_IP12_9_7,
+ GP_5_17_FN, FN_IP12_6_4,
+ GP_5_16_FN, FN_IP12_3_2,
+ GP_5_15_FN, FN_IP12_1_0,
+ GP_5_14_FN, FN_IP11_31_30,
+ GP_5_13_FN, FN_IP11_29_28,
+ GP_5_12_FN, FN_IP11_27,
+ GP_5_11_FN, FN_IP11_26,
+ GP_5_10_FN, FN_IP11_25,
+ GP_5_9_FN, FN_IP11_24,
+ GP_5_8_FN, FN_IP11_23,
+ GP_5_7_FN, FN_IP11_22,
+ GP_5_6_FN, FN_IP11_21,
+ GP_5_5_FN, FN_IP11_20,
+ GP_5_4_FN, FN_IP11_19,
+ GP_5_3_FN, FN_IP11_18_17,
+ GP_5_2_FN, FN_IP11_16_15,
+ GP_5_1_FN, FN_IP11_14_12,
+ GP_5_0_FN, FN_IP11_11_9 }
+ },
+ { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
+ GP_6_31_FN, FN_DU0_DOTCLKIN,
+ GP_6_30_FN, FN_USB1_OVC,
+ GP_6_29_FN, FN_IP14_31_29,
+ GP_6_28_FN, FN_IP14_28_26,
+ GP_6_27_FN, FN_IP14_25_23,
+ GP_6_26_FN, FN_IP14_22_20,
+ GP_6_25_FN, FN_IP14_19_17,
+ GP_6_24_FN, FN_IP14_16_14,
+ GP_6_23_FN, FN_IP14_13_11,
+ GP_6_22_FN, FN_IP14_10_8,
+ GP_6_21_FN, FN_IP14_7,
+ GP_6_20_FN, FN_IP14_6,
+ GP_6_19_FN, FN_IP14_5,
+ GP_6_18_FN, FN_IP14_4,
+ GP_6_17_FN, FN_IP14_3,
+ GP_6_16_FN, FN_IP14_2,
+ GP_6_15_FN, FN_IP14_1_0,
+ GP_6_14_FN, FN_IP13_30_28,
+ GP_6_13_FN, FN_IP13_27,
+ GP_6_12_FN, FN_IP13_26,
+ GP_6_11_FN, FN_IP13_25,
+ GP_6_10_FN, FN_IP13_24_23,
+ GP_6_9_FN, FN_IP13_22,
+ 0, 0,
+ GP_6_7_FN, FN_IP13_21_19,
+ GP_6_6_FN, FN_IP13_18_16,
+ GP_6_5_FN, FN_IP13_15,
+ GP_6_4_FN, FN_IP13_14,
+ GP_6_3_FN, FN_IP13_13,
+ GP_6_2_FN, FN_IP13_12,
+ GP_6_1_FN, FN_IP13_11,
+ GP_6_0_FN, FN_IP13_10 }
+ },
+ { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_7_25_FN, FN_USB1_PWEN,
+ GP_7_24_FN, FN_USB0_OVC,
+ GP_7_23_FN, FN_USB0_PWEN,
+ GP_7_22_FN, FN_IP15_14_12,
+ GP_7_21_FN, FN_IP15_11_9,
+ GP_7_20_FN, FN_IP15_8_6,
+ GP_7_19_FN, FN_IP7_2_0,
+ GP_7_18_FN, FN_IP6_29_27,
+ GP_7_17_FN, FN_IP6_26_24,
+ GP_7_16_FN, FN_IP6_23_21,
+ GP_7_15_FN, FN_IP6_20_19,
+ GP_7_14_FN, FN_IP6_18_16,
+ GP_7_13_FN, FN_IP6_15_14,
+ GP_7_12_FN, FN_IP6_13_12,
+ GP_7_11_FN, FN_IP6_11_10,
+ GP_7_10_FN, FN_IP6_9_8,
+ GP_7_9_FN, FN_IP16_11_10,
+ GP_7_8_FN, FN_IP16_9_8,
+ GP_7_7_FN, FN_IP16_7_6,
+ GP_7_6_FN, FN_IP16_5_3,
+ GP_7_5_FN, FN_IP16_2_0,
+ GP_7_4_FN, FN_IP15_29_27,
+ GP_7_3_FN, FN_IP15_26_24,
+ GP_7_2_FN, FN_IP15_23_21,
+ GP_7_1_FN, FN_IP15_20_18,
+ GP_7_0_FN, FN_IP15_17_15 }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
+ 1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1) {
+ /* IP0_31 [1] */
+ 0, 0,
+ /* IP0_30_29 [2] */
+ FN_A6, FN_MSIOF1_SCK,
+ 0, 0,
+ /* IP0_28_27 [2] */
+ FN_A5, FN_MSIOF0_RXD_B,
+ 0, 0,
+ /* IP0_26_25 [2] */
+ FN_A4, FN_MSIOF0_TXD_B,
+ 0, 0,
+ /* IP0_24_23 [2] */
+ FN_A3, FN_MSIOF0_SS2_B,
+ 0, 0,
+ /* IP0_22_21 [2] */
+ FN_A2, FN_MSIOF0_SS1_B,
+ 0, 0,
+ /* IP0_20_19 [2] */
+ FN_A1, FN_MSIOF0_SYNC_B,
+ 0, 0,
+ /* IP0_18_16 [3] */
+ FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
+ 0, 0, 0,
+ /* IP0_15 [1] */
+ FN_D15, 0,
+ /* IP0_14 [1] */
+ FN_D14, 0,
+ /* IP0_13 [1] */
+ FN_D13, 0,
+ /* IP0_12 [1] */
+ FN_D12, 0,
+ /* IP0_11 [1] */
+ FN_D11, 0,
+ /* IP0_10 [1] */
+ FN_D10, 0,
+ /* IP0_9 [1] */
+ FN_D9, 0,
+ /* IP0_8 [1] */
+ FN_D8, 0,
+ /* IP0_7 [1] */
+ FN_D7, 0,
+ /* IP0_6 [1] */
+ FN_D6, 0,
+ /* IP0_5 [1] */
+ FN_D5, 0,
+ /* IP0_4 [1] */
+ FN_D4, 0,
+ /* IP0_3 [1] */
+ FN_D3, 0,
+ /* IP0_2 [1] */
+ FN_D2, 0,
+ /* IP0_1 [1] */
+ FN_D1, 0,
+ /* IP0_0 [1] */
+ FN_D0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
+ 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
+ /* IP1_31_29 [3] */
+ FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
+ 0, 0, 0,
+ /* IP1_28_26 [3] */
+ FN_A17, FN_DACK2_B, 0, FN_SDA0_C,
+ 0, 0, 0, 0,
+ /* IP1_25_23 [3] */
+ FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
+ 0, 0, 0,
+ /* IP1_22_20 [3] */
+ FN_A15, FN_BPFCLK_C,
+ 0, 0, 0, 0, 0, 0,
+ /* IP1_19_17 [3] */
+ FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
+ 0, 0, 0,
+ /* IP1_16_14 [3] */
+ FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
+ 0, 0, 0, 0,
+ /* IP1_13_11 [3] */
+ FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
+ 0, 0, 0, 0,
+ /* IP1_10_8 [3] */
+ FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
+ 0, 0, 0, 0,
+ /* IP1_7_6 [2] */
+ FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
+ /* IP1_5_4 [2] */
+ FN_A9, FN_MSIOF1_SS2, FN_SDA0, 0,
+ /* IP1_3_2 [2] */
+ FN_A8, FN_MSIOF1_SS1, FN_SCL0, 0,
+ /* IP1_1_0 [2] */
+ FN_A7, FN_MSIOF1_SYNC,
+ 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
+ 2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
+ /* IP2_31_20 [2] */
+ 0, 0, 0, 0,
+ /* IP2_29_27 [3] */
+ FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
+ FN_ATAG0_N, 0, FN_EX_WAIT1,
+ 0, 0,
+ /* IP2_26_25 [2] */
+ FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
+ /* IP2_24_23 [2] */
+ FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
+ /* IP2_22_21 [2] */
+ FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1, 0,
+ /* IP2_20_19 [2] */
+ FN_CS0_N, FN_ATAG0_N_B, FN_SCL1, 0,
+ /* IP2_18_16 [3] */
+ FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
+ 0, 0,
+ /* IP2_15_13 [3] */
+ FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
+ 0, 0, 0,
+ /* IP2_12_0 [3] */
+ FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
+ 0, 0, 0,
+ /* IP2_9_7 [3] */
+ FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
+ 0, 0, 0,
+ /* IP2_6_5 [2] */
+ FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
+ /* IP2_4_3 [2] */
+ FN_A20, FN_SPCLK, 0, 0,
+ /* IP2_2_0 [3] */
+ FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
+ FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
+ 1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
+ /* IP3_31 [1] */
+ 0, 0,
+ /* IP3_30_28 [3] */
+ FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
+ FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
+ 0, 0, 0,
+ /* IP3_27_25 [3] */
+ FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
+ FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
+ 0, 0, 0,
+ /* IP3_24_22 [3] */
+ FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
+ FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
+ /* IP3_21_20 [2] */
+ FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
+ /* IP3_19_18 [2] */
+ FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
+ /* IP3_17_16 [2] */
+ FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
+ /* IP3_15_14 [2] */
+ FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
+ /* IP3_13_12 [2] */
+ FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
+ /* IP3_11_9 [3] */
+ FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
+ 0, 0, 0,
+ /* IP3_8_6 [3] */
+ FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
+ FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
+ /* IP3_5_3 [3] */
+ FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
+ FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
+ /* IP3_2_0 [3] */
+ FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
+ 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
+ 1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
+ /* IP4_31 [1] */
+ 0, 0,
+ /* IP4_30_28 [3] */
+ FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
+ FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
+ 0, 0,
+ /* IP4_27_26 [2] */
+ FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
+ /* IP4_25_24 [2] */
+ FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
+ /* IP4_23_22 [2] */
+ FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
+ /* IP4_21 [1] */
+ FN_SSI_SDATA3, 0,
+ /* IP4_20 [1] */
+ FN_SSI_WS34, 0,
+ /* IP4_19 [1] */
+ FN_SSI_SCK34, 0,
+ /* IP4_18_16 [3] */
+ FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
+ 0, 0, 0, 0,
+ /* IP4_15_13 [3] */
+ FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
+ FN_GLO_Q1_D, FN_HCTS1_N_E,
+ 0, 0,
+ /* IP4_12_10 [3] */
+ FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
+ 0, 0, 0,
+ /* IP4_9_8 [2] */
+ FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
+ /* IP4_7_5 [3] */
+ FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
+ 0, 0, 0,
+ /* IP4_4_2 [3] */
+ FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B,
+ FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
+ 0, 0, 0,
+ /* IP4_1_0 [2] */
+ FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
+ 3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
+ /* IP5_31_29 [3] */
+ FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
+ 0, 0, 0, 0, 0,
+ /* IP5_28_26 [3] */
+ FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
+ 0, 0, 0, 0,
+ /* IP5_25_24 [2] */
+ FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
+ /* IP5_23_22 [2] */
+ FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
+ /* IP5_21_20 [2] */
+ FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
+ /* IP5_19_17 [3] */
+ FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
+ 0, 0, 0, 0,
+ /* IP5_16_15 [2] */
+ FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
+ /* IP5_14_12 [3] */
+ FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
+ 0, 0, 0, 0,
+ /* IP5_11_9 [3] */
+ FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
+ 0, 0, 0, 0,
+ /* IP5_8_6 [3] */
+ FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
+ FN_MSIOF2_RXD_D, FN_VI1_R5_B,
+ 0, 0,
+ /* IP5_5_3 [3] */
+ FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
+ FN_MSIOF2_SS1_D, FN_VI1_R4_B,
+ 0, 0,
+ /* IP5_2_0 [3] */
+ FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
+ FN_MSIOF2_TXD_D, FN_VI1_R3_B,
+ 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
+ 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
+ /* IP6_31_30 [2] */
+ 0, 0, 0, 0,
+ /* IP6_29_27 [3] */
+ FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
+ FN_GPS_SIGN_C, FN_GPS_SIGN_D,
+ 0, 0, 0,
+ /* IP6_26_24 [3] */
+ FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
+ FN_GPS_CLK_C, FN_GPS_CLK_D,
+ 0, 0, 0,
+ /* IP6_23_21 [3] */
+ FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
+ FN_SDA1_E, FN_MSIOF2_SYNC_E,
+ 0, 0, 0,
+ /* IP6_20_19 [2] */
+ FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
+ /* IP6_18_16 [3] */
+ FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
+ 0, 0, 0,
+ /* IP6_15_14 [2] */
+ FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
+ /* IP6_13_12 [2] */
+ FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
+ /* IP6_11_10 [2] */
+ FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
+ /* IP6_9_8 [2] */
+ FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
+ /* IP6_7_6 [2] */
+ FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
+ /* IP6_5_3 [3] */
+ FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
+ FN_SCIFA2_RXD, FN_FMIN_E,
+ 0, 0,
+ /* IP6_2_0 [3] */
+ FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
+ FN_SCIF_CLK, 0, FN_BPFCLK_E,
+ 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
+ 2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
+ /* IP7_31_30 [2] */
+ 0, 0, 0, 0,
+ /* IP7_29_27 [3] */
+ FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
+ FN_SCIFA1_SCK, FN_SSI_SCK78_B,
+ 0, 0,
+ /* IP7_26_24 [3] */
+ FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
+ FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
+ 0, 0,
+ /* IP7_23_21 [3] */
+ FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
+ FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
+ 0, 0,
+ /* IP7_20_19 [2] */
+ FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
+ /* IP7_18_17 [2] */
+ FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
+ /* IP7_16_15 [2] */
+ FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
+ /* IP7_14_13 [2] */
+ FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
+ /* IP7_12_11 [2] */
+ FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
+ /* IP7_10_9 [2] */
+ FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
+ /* IP7_8_6 [3] */
+ FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
+ FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
+ 0, 0,
+ /* IP7_5_3 [3] */
+ FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
+ FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
+ 0, 0,
+ /* IP7_2_0 [3] */
+ FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
+ FN_SCIF_CLK_B, FN_GPS_MAG_D,
+ 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
+ 1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
+ /* IP8_31 [1] */
+ 0, 0,
+ /* IP8_30_28 [3] */
+ FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
+ 0, 0, 0,
+ /* IP8_27_26 [2] */
+ FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
+ /* IP8_25_24 [2] */
+ FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
+ /* IP8_23_21 [3] */
+ FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
+ FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
+ 0, 0,
+ /* IP8_20_18 [3] */
+ FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
+ FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
+ 0, 0,
+ /* IP8_17_15 [3] */
+ FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
+ FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
+ 0, 0,
+ /* IP8_14_12 [3] */
+ FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
+ FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
+ 0, 0, 0,
+ /* IP8_11_9 [3] */
+ FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
+ FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
+ 0, 0, 0,
+ /* IP8_8_6 [3] */
+ FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
+ FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
+ 0, 0,
+ /* IP8_5_3 [3] */
+ FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
+ FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
+ 0, 0,
+ /* IP8_2_0 [3] */
+ FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
+ 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
+ 3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
+ /* IP9_31_29 [3] */
+ FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
+ FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
+ /* IP9_28_27 [2] */
+ FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
+ /* IP9_26_25 [2] */
+ FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
+ /* IP9_24_23 [2] */
+ FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
+ /* IP9_22_21 [2] */
+ FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
+ /* IP9_20_19 [2] */
+ FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
+ /* IP9_18_17 [2] */
+ FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
+ /* IP9_16 [1] */
+ FN_DU1_DISP, FN_QPOLA,
+ /* IP9_15_13 [3] */
+ FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
+ FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
+ 0, 0, 0,
+ /* IP9_12 [1] */
+ FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
+ /* IP9_11 [1] */
+ FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
+ /* IP9_10_8 [3] */
+ FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
+ FN_TX3_B, FN_SCL2_B, FN_PWM4,
+ 0, 0,
+ /* IP9_7 [1] */
+ FN_DU1_DOTCLKOUT0, FN_QCLK,
+ /* IP9_6 [1] */
+ FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
+ /* IP9_5_3 [3] */
+ FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C,
+ FN_SCIF3_SCK, FN_SCIFA3_SCK,
+ 0, 0, 0,
+ /* IP9_2_0 [3] */
+ FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
+ 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
+ 3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
+ /* IP10_31_29 [3] */
+ FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
+ 0, 0, 0,
+ /* IP10_28_27 [2] */
+ FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
+ /* IP10_26_25 [2] */
+ FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
+ /* IP10_24_22 [3] */
+ FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
+ 0, 0, 0,
+ /* IP10_21_29 [3] */
+ FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
+ FN_TS_SDATA0_C, FN_ATACS11_N,
+ 0, 0, 0,
+ /* IP10_18_17 [2] */
+ FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
+ /* IP10_16_15 [2] */
+ FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
+ /* IP10_14_12 [3] */
+ FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
+ FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
+ /* IP10_11_9 [3] */
+ FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
+ FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
+ 0, 0,
+ /* IP10_8_6 [3] */
+ FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
+ FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
+ /* IP10_5_3 [3] */
+ FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
+ FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
+ /* IP10_2_0 [3] */
+ FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
+ FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
+ 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
+ 3, 3, 3, 3, 3) {
+ /* IP11_31_30 [2] */
+ FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
+ /* IP11_29_28 [2] */
+ FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
+ /* IP11_27 [1] */
+ FN_VI1_DATA7, FN_AVB_MDC,
+ /* IP11_26 [1] */
+ FN_VI1_DATA6, FN_AVB_MAGIC,
+ /* IP11_25 [1] */
+ FN_VI1_DATA5, FN_AVB_RX_DV,
+ /* IP11_24 [1] */
+ FN_VI1_DATA4, FN_AVB_MDIO,
+ /* IP11_23 [1] */
+ FN_VI1_DATA3, FN_AVB_RX_ER,
+ /* IP11_22 [1] */
+ FN_VI1_DATA2, FN_AVB_RXD7,
+ /* IP11_21 [1] */
+ FN_VI1_DATA1, FN_AVB_RXD6,
+ /* IP11_20 [1] */
+ FN_VI1_DATA0, FN_AVB_RXD5,
+ /* IP11_19 [1] */
+ FN_VI1_CLK, FN_AVB_RXD4,
+ /* IP11_18_17 [2] */
+ FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
+ /* IP11_16_15 [2] */
+ FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
+ /* IP11_14_12 [3] */
+ FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
+ FN_RX4_B, FN_SCIFA4_RXD_B,
+ 0, 0, 0,
+ /* IP11_11_9 [3] */
+ FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
+ FN_TX4_B, FN_SCIFA4_TXD_B,
+ 0, 0, 0,
+ /* IP11_8_6 [3] */
+ FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
+ FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
+ /* IP11_5_3 [3] */
+ FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
+ 0, 0, 0,
+ /* IP11_2_0 [3] */
+ FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
+ 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
+ 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
+ /* IP12_31_30 [2] */
+ 0, 0, 0, 0,
+ /* IP12_29_27 [3] */
+ FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
+ FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
+ 0, 0, 0,
+ /* IP12_26_24 [3] */
+ FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
+ FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
+ 0, 0, 0,
+ /* IP12_23_22 [2] */
+ FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
+ /* IP12_21_20 [2] */
+ FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
+ /* IP12_19_18 [2] */
+ FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
+ /* IP12_17_16 [2] */
+ FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
+ /* IP12_15_13 [3] */
+ FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
+ FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
+ 0, 0, 0,
+ /* IP12_12_10 [3] */
+ FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
+ FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
+ 0, 0, 0,
+ /* IP12_9_7 [3] */
+ FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
+ FN_SDA2_D, FN_MSIOF1_SCK_E,
+ 0, 0, 0,
+ /* IP12_6_4 [3] */
+ FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
+ FN_SCL2_D, FN_MSIOF1_RXD_E,
+ 0, 0, 0,
+ /* IP12_3_2 [2] */
+ FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
+ /* IP12_1_0 [2] */
+ FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
+ 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
+ 3, 2, 2, 3) {
+ /* IP13_31 [1] */
+ 0, 0,
+ /* IP13_30_28 [3] */
+ FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
+ 0, 0, 0, 0,
+ /* IP13_27 [1] */
+ FN_SD1_DATA3, FN_IERX_B,
+ /* IP13_26 [1] */
+ FN_SD1_DATA2, FN_IECLK_B,
+ /* IP13_25 [1] */
+ FN_SD1_DATA1, FN_IETX_B,
+ /* IP13_24_23 [2] */
+ FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
+ /* IP13_22 [1] */
+ FN_SD1_CMD, FN_REMOCON_B,
+ /* IP13_21_19 [3] */
+ FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
+ FN_SCIFA5_RXD_B, FN_RX3_C,
+ 0, 0,
+ /* IP13_18_16 [3] */
+ FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
+ FN_SCIFA5_TXD_B, FN_TX3_C,
+ 0, 0,
+ /* IP13_15 [1] */
+ FN_SD0_DATA3, FN_SSL_B,
+ /* IP13_14 [1] */
+ FN_SD0_DATA2, FN_IO3_B,
+ /* IP13_13 [1] */
+ FN_SD0_DATA1, FN_IO2_B,
+ /* IP13_12 [1] */
+ FN_SD0_DATA0, FN_MISO_IO1_B,
+ /* IP13_11 [1] */
+ FN_SD0_CMD, FN_MOSI_IO0_B,
+ /* IP13_10 [1] */
+ FN_SD0_CLK, FN_SPCLK_B,
+ /* IP13_9_7 [3] */
+ FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
+ FN_ADICHS2_B, FN_MSIOF0_TXD_C,
+ 0, 0, 0,
+ /* IP13_6_5 [2] */
+ FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
+ /* IP13_4_3 [2] */
+ FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
+ /* IP13_2_0 [3] */
+ FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
+ FN_ADICLK_B, FN_MSIOF0_SS1_C,
+ 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
+ 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
+ /* IP14_31_29 [3] */
+ FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
+ FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0,
+ /* IP14_28_26 [3] */
+ FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
+ FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0,
+ /* IP14_25_23 [3] */
+ FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
+ 0, 0, 0,
+ /* IP14_22_20 [3] */
+ FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
+ 0, 0, 0,
+ /* IP14_19_17 [3] */
+ FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
+ FN_VI1_CLKENB_C, FN_VI1_G1_B,
+ 0, 0,
+ /* IP14_16_14 [3] */
+ FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
+ FN_VI1_CLK_C, FN_VI1_G0_B,
+ 0, 0,
+ /* IP14_13_11 [3] */
+ FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
+ 0, 0, 0,
+ /* IP14_10_8 [3] */
+ FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
+ 0, 0, 0,
+ /* IP14_7 [1] */
+ FN_SD2_DATA3, FN_MMC_D3,
+ /* IP14_6 [1] */
+ FN_SD2_DATA2, FN_MMC_D2,
+ /* IP14_5 [1] */
+ FN_SD2_DATA1, FN_MMC_D1,
+ /* IP14_4 [1] */
+ FN_SD2_DATA0, FN_MMC_D0,
+ /* IP14_3 [1] */
+ FN_SD2_CMD, FN_MMC_CMD,
+ /* IP14_2 [1] */
+ FN_SD2_CLK, FN_MMC_CLK,
+ /* IP14_1_0 [2] */
+ FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
+ 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
+ /* IP15_31_30 [2] */
+ 0, 0, 0, 0,
+ /* IP15_29_27 [3] */
+ FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
+ FN_CAN0_TX_B, FN_VI1_DATA5_C,
+ 0, 0,
+ /* IP15_26_24 [3] */
+ FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
+ FN_CAN0_RX_B, FN_VI1_DATA4_C,
+ 0, 0,
+ /* IP15_23_21 [3] */
+ FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
+ FN_TCLK2, FN_VI1_DATA3_C, 0,
+ /* IP15_20_18 [3] */
+ FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
+ 0, 0, 0,
+ /* IP15_17_15 [3] */
+ FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
+ FN_TCLK1, FN_VI1_DATA1_C,
+ 0, 0,
+ /* IP15_14_12 [3] */
+ FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
+ FN_VI1_G7_B, FN_SCIFA3_SCK_C,
+ 0, 0,
+ /* IP15_11_9 [3] */
+ FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
+ FN_VI1_G6_B, FN_SCIFA3_RXD_C,
+ 0, 0,
+ /* IP15_8_6 [3] */
+ FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
+ FN_PWM5_B, FN_SCIFA3_TXD_C,
+ 0, 0, 0,
+ /* IP15_5_4 [2] */
+ FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
+ /* IP15_3_2 [2] */
+ FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
+ /* IP15_1_0 [2] */
+ FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
+ 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
+ /* IP16_31_28 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP16_27_24 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP16_23_20 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP16_19_16 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP16_15_12 [4] */
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP16_11_10 [2] */
+ FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
+ /* IP16_9_8 [2] */
+ FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
+ /* IP16_7_6 [2] */
+ FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
+ /* IP16_5_3 [3] */
+ FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
+ FN_GLO_SS_C, FN_VI1_DATA7_C,
+ 0, 0, 0,
+ /* IP16_2_0 [3] */
+ FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
+ FN_GLO_SDATA_C, FN_VI1_DATA6_C,
+ 0, 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
+ 1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
+ 3, 2, 2, 2, 1, 2, 2, 2) {
+ /* RESEVED [1] */
+ 0, 0,
+ /* SEL_SCIF1 [2] */
+ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+ /* SEL_SCIFB [2] */
+ FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
+ /* SEL_SCIFB2 [2] */
+ FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
+ FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
+ /* SEL_SCIFB1 [3] */
+ FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
+ FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
+ 0, 0, 0, 0,
+ /* SEL_SCIFA1 [2] */
+ FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
+ /* SEL_SSI9 [1] */
+ FN_SEL_SSI9_0, FN_SEL_SSI9_1,
+ /* SEL_SCFA [1] */
+ FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+ /* SEL_QSP [1] */
+ FN_SEL_QSP_0, FN_SEL_QSP_1,
+ /* SEL_SSI7 [1] */
+ FN_SEL_SSI7_0, FN_SEL_SSI7_1,
+ /* SEL_HSCIF1 [3] */
+ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
+ FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
+ 0, 0, 0,
+ /* RESEVED [2] */
+ 0, 0, 0, 0,
+ /* SEL_VI1 [2] */
+ FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
+ /* RESEVED [2] */
+ 0, 0, 0, 0,
+ /* SEL_TMU [1] */
+ FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+ /* SEL_LBS [2] */
+ FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
+ /* SEL_TSIF0 [2] */
+ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+ /* SEL_SOF0 [2] */
+ FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
+ 3, 1, 1, 3, 2, 1, 1, 2, 2,
+ 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
+ /* SEL_SCIF0 [3] */
+ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
+ FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
+ 0, 0, 0,
+ /* RESEVED [1] */
+ 0, 0,
+ /* SEL_SCIF [1] */
+ FN_SEL_SCIF_0, FN_SEL_SCIF_1,
+ /* SEL_CAN0 [3] */
+ FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+ FN_SEL_CAN0_4, FN_SEL_CAN0_5,
+ 0, 0,
+ /* SEL_CAN1 [2] */
+ FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+ /* RESEVED [1] */
+ 0, 0,
+ /* SEL_SCIFA2 [1] */
+ FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
+ /* SEL_SCIF4 [2] */
+ FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
+ /* RESEVED [2] */
+ 0, 0, 0, 0,
+ /* SEL_ADG [1] */
+ FN_SEL_ADG_0, FN_SEL_ADG_1,
+ /* SEL_FM [3] */
+ FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
+ FN_SEL_FM_3, FN_SEL_FM_4,
+ 0, 0, 0,
+ /* SEL_SCIFA5 [2] */
+ FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
+ /* RESEVED [1] */
+ 0, 0,
+ /* SEL_GPS [2] */
+ FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
+ /* SEL_SCIFA4 [2] */
+ FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
+ /* SEL_SCIFA3 [2] */
+ FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
+ /* SEL_SIM [1] */
+ FN_SEL_SIM_0, FN_SEL_SIM_1,
+ /* RESEVED [1] */
+ 0, 0,
+ /* SEL_SSI8 [1] */
+ FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
+ 2, 2, 2, 2, 2, 2, 2, 2,
+ 1, 1, 2, 2, 3, 2, 2, 2, 1) {
+ /* SEL_HSCIF2 [2] */
+ FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
+ FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
+ /* SEL_CANCLK [2] */
+ FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+ FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
+ /* SEL_IIC8 [2] */
+ FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
+ /* SEL_IIC7 [2] */
+ FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
+ /* SEL_IIC4 [2] */
+ FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
+ /* SEL_IIC3 [2] */
+ FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
+ /* SEL_SCIF3 [2] */
+ FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
+ /* SEL_IEB [2] */
+ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+ /* SEL_MMC [1] */
+ FN_SEL_MMC_0, FN_SEL_MMC_1,
+ /* SEL_SCIF5 [1] */
+ FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
+ /* RESEVED [2] */
+ 0, 0, 0, 0,
+ /* SEL_IIC2 [2] */
+ FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+ /* SEL_IIC1 [3] */
+ FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
+ FN_SEL_IIC1_4,
+ 0, 0, 0,
+ /* SEL_IIC0 [2] */
+ FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
+ /* RESEVED [2] */
+ 0, 0, 0, 0,
+ /* RESEVED [2] */
+ 0, 0, 0, 0,
+ /* RESEVED [1] */
+ 0, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
+ 3, 2, 2, 1, 1, 1, 1, 3, 2,
+ 2, 3, 1, 1, 1, 2, 2, 2, 2) {
+ /* SEL_SOF1 [3] */
+ FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
+ FN_SEL_SOF1_4,
+ 0, 0, 0,
+ /* SEL_HSCIF0 [2] */
+ FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
+ /* SEL_DIS [2] */
+ FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
+ /* RESEVED [1] */
+ 0, 0,
+ /* SEL_RAD [1] */
+ FN_SEL_RAD_0, FN_SEL_RAD_1,
+ /* SEL_RCN [1] */
+ FN_SEL_RCN_0, FN_SEL_RCN_1,
+ /* SEL_RSP [1] */
+ FN_SEL_RSP_0, FN_SEL_RSP_1,
+ /* SEL_SCIF2 [3] */
+ FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
+ FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
+ 0, 0, 0,
+ /* RESEVED [2] */
+ 0, 0, 0, 0,
+ /* RESEVED [2] */
+ 0, 0, 0, 0,
+ /* SEL_SOF2 [3] */
+ FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
+ FN_SEL_SOF2_3, FN_SEL_SOF2_4,
+ 0, 0, 0,
+ /* RESEVED [1] */
+ 0, 0,
+ /* SEL_SSI1 [1] */
+ FN_SEL_SSI1_0, FN_SEL_SSI1_1,
+ /* SEL_SSI0 [1] */
+ FN_SEL_SSI0_0, FN_SEL_SSI0_1,
+ /* SEL_SSP [2] */
+ FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
+ /* RESEVED [2] */
+ 0, 0, 0, 0,
+ /* RESEVED [2] */
+ 0, 0, 0, 0,
+ /* RESEVED [2] */
+ 0, 0, 0, 0, }
+ },
+ { },
+};
+
+const struct sh_pfc_soc_info r8a7791_pinmux_info = {
+ .name = "r8a77910_pfc",
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+ .cfg_regs = pinmux_config_regs,
+
+ .gpio_data = pinmux_data,
+ .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
PINCTRL_PIN(100, "ac97_dout"),
PINCTRL_PIN(101, "ac97_din"),
PINCTRL_PIN(102, "x_rtc_io"),
+
+ PINCTRL_PIN(103, "x_usb1_dp"),
+ PINCTRL_PIN(104, "x_usb1_dn"),
};
static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
static const struct sirfsoc_padmux lcd_16bits_padmux = {
.muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
.muxmask = lcd_16bits_sirfsoc_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = 0,
};
static const struct sirfsoc_padmux lcd_18bits_padmux = {
.muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
.muxmask = lcd_18bits_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4) | BIT(15),
.funcval = 0,
};
static const struct sirfsoc_padmux lcd_24bits_padmux = {
.muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
.muxmask = lcd_24bits_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4) | BIT(15),
.funcval = 0,
};
static const struct sirfsoc_padmux lcdrom_padmux = {
.muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
.muxmask = lcdrom_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = BIT(4),
};
static const struct sirfsoc_padmux uart0_padmux = {
.muxmask_counts = ARRAY_SIZE(uart0_muxmask),
.muxmask = uart0_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(9),
.funcval = BIT(9),
};
static const struct sirfsoc_padmux uart2_padmux = {
.muxmask_counts = ARRAY_SIZE(uart2_muxmask),
.muxmask = uart2_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(10),
.funcval = BIT(10),
};
static const struct sirfsoc_padmux sdmmc3_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
.muxmask = sdmmc3_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(7),
.funcval = 0,
};
static const struct sirfsoc_padmux spi0_padmux = {
.muxmask_counts = ARRAY_SIZE(spi0_muxmask),
.muxmask = spi0_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(7),
.funcval = BIT(7),
};
static const struct sirfsoc_padmux cko1_padmux = {
.muxmask_counts = ARRAY_SIZE(cko1_muxmask),
.muxmask = cko1_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(3),
.funcval = 0,
};
static const struct sirfsoc_padmux i2s_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_muxmask),
.muxmask = i2s_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(3),
.funcval = BIT(3),
};
static const struct sirfsoc_padmux i2s_no_din_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
.muxmask = i2s_no_din_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(3),
.funcval = BIT(3),
};
static const struct sirfsoc_padmux i2s_6chn_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
.muxmask = i2s_6chn_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(3) | BIT(9),
.funcval = BIT(1) | BIT(3) | BIT(9),
};
static const struct sirfsoc_padmux spi1_padmux = {
.muxmask_counts = ARRAY_SIZE(spi1_muxmask),
.muxmask = spi1_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(16),
.funcval = 0,
};
static const struct sirfsoc_padmux sdmmc1_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
.muxmask = sdmmc1_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(5),
.funcval = BIT(5),
};
static const struct sirfsoc_padmux gps_padmux = {
.muxmask_counts = ARRAY_SIZE(gps_muxmask),
.muxmask = gps_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(13),
.funcval = 0,
};
static const struct sirfsoc_padmux sdmmc5_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
.muxmask = sdmmc5_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(13),
.funcval = BIT(13),
};
static const struct sirfsoc_padmux usp0_padmux = {
.muxmask_counts = ARRAY_SIZE(usp0_muxmask),
.muxmask = usp0_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(2) | BIT(9),
.funcval = 0,
};
static const struct sirfsoc_padmux usp1_padmux = {
.muxmask_counts = ARRAY_SIZE(usp1_muxmask),
.muxmask = usp1_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(16),
.funcval = BIT(16),
};
static const struct sirfsoc_padmux nand_padmux = {
.muxmask_counts = ARRAY_SIZE(nand_muxmask),
.muxmask = nand_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(5) | BIT(19),
.funcval = 0,
};
static const struct sirfsoc_padmux sdmmc0_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask),
.muxmask = sdmmc0_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(5) | BIT(19),
.funcval = BIT(19),
};
static const struct sirfsoc_padmux sdmmc2_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
.muxmask = sdmmc2_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(11),
.funcval = 0,
};
static const struct sirfsoc_padmux sdmmc2_nowp_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask),
.muxmask = sdmmc2_nowp_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(11),
.funcval = 0,
};
static const struct sirfsoc_padmux vip_padmux = {
.muxmask_counts = ARRAY_SIZE(vip_muxmask),
.muxmask = vip_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(18),
.funcval = BIT(18),
};
static const struct sirfsoc_padmux vip_noupli_padmux = {
.muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask),
.muxmask = vip_noupli_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(15),
.funcval = BIT(15),
};
static const struct sirfsoc_padmux i2c1_padmux = {
.muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
.muxmask = i2c1_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(16),
.funcval = 0,
};
static const struct sirfsoc_padmux pwm0_padmux = {
.muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
.muxmask = pwm0_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(12),
.funcval = 0,
};
static const struct sirfsoc_padmux warm_rst_padmux = {
.muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
.muxmask = warm_rst_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = 0,
};
static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = {
.muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask),
.muxmask = usb0_upli_drvbus_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(18),
.funcval = 0,
};
static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
.muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
.muxmask = usb1_utmi_drvbus_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(11),
.funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
};
static const unsigned usb1_utmi_drvbus_pins[] = { 28 };
+static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
+ .muxmask_counts = 0,
+ .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
+ .funcmask = BIT(2),
+ .funcval = BIT(2),
+};
+
+static const unsigned usb1_dp_dn_pins[] = { 103, 104 };
+
+static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
+ .muxmask_counts = 0,
+ .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
+ .funcmask = BIT(2),
+ .funcval = 0,
+};
+
+static const unsigned uart1_route_io_usb1_pins[] = { 103, 104 };
+
static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
{
.group = 0,
SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins),
SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
+ SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
+ SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" };
static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" };
static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
+static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
+static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
static const char * const pulse_countgrp[] = { "pulse_countgrp" };
static const char * const i2sgrp[] = { "i2sgrp" };
static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
+ SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
+ SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
PINCTRL_PIN(112, "x_ldd[13]"),
PINCTRL_PIN(113, "x_ldd[14]"),
PINCTRL_PIN(114, "x_ldd[15]"),
+
+ PINCTRL_PIN(115, "x_usb1_dp"),
+ PINCTRL_PIN(116, "x_usb1_dn"),
};
static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
static const struct sirfsoc_padmux lcd_16bits_padmux = {
.muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
.muxmask = lcd_16bits_sirfsoc_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = 0,
};
static const struct sirfsoc_padmux lcd_18bits_padmux = {
.muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
.muxmask = lcd_18bits_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = 0,
};
static const struct sirfsoc_padmux lcd_24bits_padmux = {
.muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
.muxmask = lcd_24bits_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = 0,
};
static const struct sirfsoc_padmux lcdrom_padmux = {
.muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
.muxmask = lcdrom_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(4),
.funcval = BIT(4),
};
static const struct sirfsoc_padmux uart0_padmux = {
.muxmask_counts = ARRAY_SIZE(uart0_muxmask),
.muxmask = uart0_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(9),
.funcval = BIT(9),
};
static const struct sirfsoc_padmux uart2_padmux = {
.muxmask_counts = ARRAY_SIZE(uart2_muxmask),
.muxmask = uart2_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(10),
.funcval = BIT(10),
};
static const struct sirfsoc_padmux sdmmc3_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
.muxmask = sdmmc3_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(7),
.funcval = 0,
};
static const struct sirfsoc_padmux spi0_padmux = {
.muxmask_counts = ARRAY_SIZE(spi0_muxmask),
.muxmask = spi0_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(7),
.funcval = BIT(7),
};
static const struct sirfsoc_padmux cko1_padmux = {
.muxmask_counts = ARRAY_SIZE(cko1_muxmask),
.muxmask = cko1_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(3),
.funcval = 0,
};
static const struct sirfsoc_padmux i2s_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_muxmask),
.muxmask = i2s_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(3) | BIT(9),
.funcval = BIT(3),
};
static const struct sirfsoc_padmux ac97_padmux = {
.muxmask_counts = ARRAY_SIZE(ac97_muxmask),
.muxmask = ac97_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(8),
.funcval = 0,
};
static const struct sirfsoc_padmux spi1_padmux = {
.muxmask_counts = ARRAY_SIZE(spi1_muxmask),
.muxmask = spi1_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(8),
.funcval = BIT(8),
};
static const struct sirfsoc_padmux gps_padmux = {
.muxmask_counts = ARRAY_SIZE(gps_muxmask),
.muxmask = gps_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(12) | BIT(13) | BIT(14),
.funcval = BIT(12),
};
static const struct sirfsoc_padmux sdmmc5_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
.muxmask = sdmmc5_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(13) | BIT(14),
.funcval = BIT(13) | BIT(14),
};
static const struct sirfsoc_padmux usp0_padmux = {
.muxmask_counts = ARRAY_SIZE(usp0_muxmask),
.muxmask = usp0_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9),
.funcval = 0,
};
static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
+static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
+ {
+ .group = 1,
+ .mask = BIT(20) | BIT(21),
+ },
+};
+
+static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
+ .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
+ .muxmask = usp0_uart_nostreamctrl_muxmask,
+};
+
+static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
+
static const struct sirfsoc_muxmask usp1_muxmask[] = {
{
.group = 1,
static const struct sirfsoc_padmux usp1_padmux = {
.muxmask_counts = ARRAY_SIZE(usp1_muxmask),
.muxmask = usp1_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11),
.funcval = 0,
};
static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 };
+static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
+ {
+ .group = 1,
+ .mask = BIT(25) | BIT(26),
+ },
+};
+
+static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
+ .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
+ .muxmask = usp1_uart_nostreamctrl_muxmask,
+};
+
+static const unsigned usp1_uart_nostreamctrl_pins[] = { 57, 58 };
+
static const struct sirfsoc_muxmask usp2_muxmask[] = {
{
.group = 1,
static const struct sirfsoc_padmux usp2_padmux = {
.muxmask_counts = ARRAY_SIZE(usp2_muxmask),
.muxmask = usp2_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(13) | BIT(14),
.funcval = 0,
};
static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 };
+static const struct sirfsoc_muxmask usp2_uart_nostreamctrl_muxmask[] = {
+ {
+ .group = 1,
+ .mask = BIT(30) | BIT(31),
+ },
+};
+
+static const struct sirfsoc_padmux usp2_uart_nostreamctrl_padmux = {
+ .muxmask_counts = ARRAY_SIZE(usp2_uart_nostreamctrl_muxmask),
+ .muxmask = usp2_uart_nostreamctrl_muxmask,
+};
+
+static const unsigned usp2_uart_nostreamctrl_pins[] = { 62, 63 };
+
static const struct sirfsoc_muxmask nand_muxmask[] = {
{
.group = 2,
static const struct sirfsoc_padmux nand_padmux = {
.muxmask_counts = ARRAY_SIZE(nand_muxmask),
.muxmask = nand_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(5),
.funcval = 0,
};
static const struct sirfsoc_padmux sdmmc0_padmux = {
.muxmask_counts = 0,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(5),
.funcval = 0,
};
static const struct sirfsoc_padmux sdmmc2_padmux = {
.muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
.muxmask = sdmmc2_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(5),
.funcval = BIT(5),
};
static const struct sirfsoc_padmux vip_padmux = {
.muxmask_counts = ARRAY_SIZE(vip_muxmask),
.muxmask = vip_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(0),
.funcval = 0,
};
static const struct sirfsoc_padmux viprom_padmux = {
.muxmask_counts = ARRAY_SIZE(viprom_muxmask),
.muxmask = viprom_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(0),
.funcval = BIT(0),
};
static const struct sirfsoc_padmux pwm0_padmux = {
.muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
.muxmask = pwm0_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(12),
.funcval = 0,
};
static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = {
.muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask),
.muxmask = usb0_utmi_drvbus_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(6),
.funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
};
static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
.muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
.muxmask = usb1_utmi_drvbus_muxmask,
+ .ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(11),
.funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
};
static const unsigned usb1_utmi_drvbus_pins[] = { 59 };
+static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
+ .muxmask_counts = 0,
+ .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
+ .funcmask = BIT(2),
+ .funcval = BIT(2),
+};
+
+static const unsigned usb1_dp_dn_pins[] = { 115, 116 };
+
+static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
+ .muxmask_counts = 0,
+ .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
+ .funcmask = BIT(2),
+ .funcval = 0,
+};
+
+static const unsigned uart1_route_io_usb1_pins[] = { 115, 116 };
+
static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
{
.group = 0,
SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
+ SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
+ SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
+ usp0_uart_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
+ SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
+ usp1_uart_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("usp2grp", usp2_pins),
+ SIRFSOC_PIN_GROUP("usp2_uart_nostreamctrl_grp",
+ usp2_uart_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins),
SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
+ SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
+ SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
static const char * const lcdromgrp[] = { "lcdromgrp" };
static const char * const uart0grp[] = { "uart0grp" };
+static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
static const char * const uart1grp[] = { "uart1grp" };
static const char * const uart2grp[] = { "uart2grp" };
static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
static const char * const usp0grp[] = { "usp0grp" };
+static const char * const usp0_uart_nostreamctrl_grp[] =
+ { "usp0_uart_nostreamctrl_grp" };
static const char * const usp1grp[] = { "usp1grp" };
+static const char * const usp1_uart_nostreamctrl_grp[] =
+ { "usp1_uart_nostreamctrl_grp" };
static const char * const usp2grp[] = { "usp2grp" };
+static const char * const usp2_uart_nostreamctrl_grp[] =
+ { "usp2_uart_nostreamctrl_grp" };
static const char * const i2c0grp[] = { "i2c0grp" };
static const char * const i2c1grp[] = { "i2c1grp" };
static const char * const pwm0grp[] = { "pwm0grp" };
static const char * const sdmmc5grp[] = { "sdmmc5grp" };
static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
+static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
+static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
static const char * const pulse_countgrp[] = { "pulse_countgrp" };
static const char * const i2sgrp[] = { "i2sgrp" };
static const char * const ac97grp[] = { "ac97grp" };
SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
+ SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
+ SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
+ usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
+ SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
+ usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux),
+ SIRFSOC_PMX_FUNCTION("usp2_uart_nostreamctrl",
+ usp2_uart_nostreamctrl_grp, usp2_uart_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
+ SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
+ SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
if (mux->funcmask && enable) {
u32 func_en_val;
+
func_en_val =
- readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
+ readl(spmx->rsc_virtbase + mux->ctrlreg);
func_en_val =
- (func_en_val & ~mux->funcmask) | (mux->
- funcval);
- writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
+ (func_en_val & ~mux->funcmask) | (mux->funcval);
+ writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg);
}
}
#ifndef __PINMUX_SIRF_H__
#define __PINMUX_SIRF_H__
-#define SIRFSOC_NUM_PADS 622
-#define SIRFSOC_RSC_PIN_MUX 0x4
+#define SIRFSOC_NUM_PADS 622
+#define SIRFSOC_RSC_USB_UART_SHARE 0
+#define SIRFSOC_RSC_PIN_MUX 0x4
#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
#define SIRFSOC_GPIO_PAD_EN_CLR(g) ((g)*0x100 + 0x90)
unsigned long muxmask_counts;
const struct sirfsoc_muxmask *muxmask;
/* RSC_PIN_MUX set */
+ unsigned long ctrlreg;
unsigned long funcmask;
unsigned long funcval;
};
.owner = THIS_MODULE,
.name = "spear-plgpio",
.pm = &plgpio_dev_pm_ops,
- .of_match_table = of_match_ptr(plgpio_of_match),
+ .of_match_table = plgpio_of_match,
},
};
int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
unsigned int gpio_offset, unsigned int pin_offset,
unsigned int npins);
+int gpiochip_add_pingroup_range(struct gpio_chip *chip,
+ struct pinctrl_dev *pctldev,
+ unsigned int gpio_offset, const char *pin_group);
void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
#else
{
return 0;
}
+static inline int
+gpiochip_add_pingroup_range(struct gpio_chip *chip,
+ struct pinctrl_dev *pctldev,
+ unsigned int gpio_offset, const char *pin_group)
+{
+ return 0;
+}
static inline void
gpiochip_remove_pin_ranges(struct gpio_chip *chip)
#define AT91_PINCTRL_PULL_DOWN (1 << 3)
#define AT91_PINCTRL_DIS_SCHMIT (1 << 4)
#define AT91_PINCTRL_DEBOUNCE (1 << 16)
-#define AT91_PINCTRL_DEBOUNCE_VA(x) (x << 17)
+#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17)
#define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH)
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/bug.h>
+#include <linux/pinctrl/pinctrl.h>
struct device;
struct gpio_chip;
return -EINVAL;
}
+static inline int
+gpiochip_add_pingroup_range(struct gpio_chip *chip,
+ struct pinctrl_dev *pctldev,
+ unsigned int gpio_offset, const char *pin_group)
+{
+ WARN_ON(1);
+ return -EINVAL;
+}
+
static inline void
gpiochip_remove_pin_ranges(struct gpio_chip *chip)
{
extern struct pinctrl_gpio_range *
pinctrl_find_gpio_range_from_pin(struct pinctrl_dev *pctldev,
unsigned int pin);
+extern int pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+ const char *pin_group, const unsigned **pins,
+ unsigned *num_pins);
#ifdef CONFIG_OF
extern struct pinctrl_dev *of_pinctrl_get(struct device_node *np);
--- /dev/null
+/*
+ * Pinctrl Driver for ADI GPIO2 controller
+ *
+ * Copyright 2007-2013 Analog Devices Inc.
+ *
+ * Licensed under the GPLv2 or later
+ */
+
+
+#ifndef PINCTRL_ADI2_H
+#define PINCTRL_ADI2_H
+
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+/**
+ * struct adi_pinctrl_gpio_platform_data - Pinctrl gpio platform data
+ * for ADI GPIO2 device.
+ *
+ * @port_gpio_base: Optional global GPIO index of the GPIO bank.
+ * 0 means driver decides.
+ * @port_pin_base: Pin index of the pin controller device.
+ * @port_width: PIN number of the GPIO bank device
+ * @pint_id: GPIO PINT device id that this GPIO bank should map to.
+ * @pint_assign: The 32-bit GPIO PINT registers can be divided into 2 parts. A
+ * GPIO bank can be mapped into either low 16 bits[0] or high 16
+ * bits[1] of each PINT register.
+ * @pint_map: GIOP bank mapping code in PINT device
+ */
+struct adi_pinctrl_gpio_platform_data {
+ unsigned int port_gpio_base;
+ unsigned int port_pin_base;
+ unsigned int port_width;
+ u8 pinctrl_id;
+ u8 pint_id;
+ bool pint_assign;
+ u8 pint_map;
+};
+
+#endif
projects / cascardo / linux.git / commitdiff