ath10k: remove 4-addr padding related hw_param configuration
authorVasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
Fri, 9 Sep 2016 14:25:36 +0000 (17:25 +0300)
committerKalle Valo <kvalo@qca.qualcomm.com>
Tue, 13 Sep 2016 12:31:06 +0000 (15:31 +0300)
hw_4addr_pad was added to handle different types of padding
in 4-address rx frame. But this padding is not very specific
to 4-address, it can happen even with three address + ethernet
decap mode. Since the  padding information can be obtained
through Rx desc for QCA99X0 and newer chips, this hw_param
is not needed any more.

Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
drivers/net/wireless/ath/ath10k/core.c
drivers/net/wireless/ath/ath10k/hw.h

index 2d405a6..3a8984b 100644 (file)
@@ -60,7 +60,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .otp_exe_param = 0,
                .channel_counters_freq_hz = 88000,
                .max_probe_resp_desc_thres = 0,
-               .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
                .cal_data_len = 2116,
                .fw = {
                        .dir = QCA988X_HW_2_0_FW_DIR,
@@ -80,7 +79,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .otp_exe_param = 0,
                .channel_counters_freq_hz = 88000,
                .max_probe_resp_desc_thres = 0,
-               .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
                .cal_data_len = 2116,
                .fw = {
                        .dir = QCA9887_HW_1_0_FW_DIR,
@@ -117,7 +115,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .otp_exe_param = 0,
                .channel_counters_freq_hz = 88000,
                .max_probe_resp_desc_thres = 0,
-               .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
                .cal_data_len = 8124,
                .fw = {
                        .dir = QCA6174_HW_2_1_FW_DIR,
@@ -136,7 +133,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .otp_exe_param = 0,
                .channel_counters_freq_hz = 88000,
                .max_probe_resp_desc_thres = 0,
-               .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
                .cal_data_len = 8124,
                .fw = {
                        .dir = QCA6174_HW_3_0_FW_DIR,
@@ -155,7 +151,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .otp_exe_param = 0,
                .channel_counters_freq_hz = 88000,
                .max_probe_resp_desc_thres = 0,
-               .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
                .cal_data_len = 8124,
                .fw = {
                        /* uses same binaries as hw3.0 */
@@ -177,7 +172,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .cck_rate_map_rev2 = true,
                .channel_counters_freq_hz = 150000,
                .max_probe_resp_desc_thres = 24,
-               .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
                .tx_chain_mask = 0xf,
                .rx_chain_mask = 0xf,
                .max_spatial_stream = 4,
@@ -202,7 +196,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .cck_rate_map_rev2 = true,
                .channel_counters_freq_hz = 150000,
                .max_probe_resp_desc_thres = 24,
-               .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
                .tx_chain_mask = 0xf,
                .rx_chain_mask = 0xf,
                .max_spatial_stream = 4,
@@ -226,7 +219,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .continuous_frag_desc = true,
                .channel_counters_freq_hz = 150000,
                .max_probe_resp_desc_thres = 24,
-               .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
                .tx_chain_mask = 3,
                .rx_chain_mask = 3,
                .max_spatial_stream = 2,
@@ -288,7 +280,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .cck_rate_map_rev2 = true,
                .channel_counters_freq_hz = 125000,
                .max_probe_resp_desc_thres = 24,
-               .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
                .tx_chain_mask = 0x3,
                .rx_chain_mask = 0x3,
                .max_spatial_stream = 2,
index 204f882..308e423 100644 (file)
@@ -338,11 +338,6 @@ enum ath10k_hw_rate_rev2_cck {
        ATH10K_HW_RATE_REV2_CCK_SP_11M,
 };
 
-enum ath10k_hw_4addr_pad {
-       ATH10K_HW_4ADDR_PAD_AFTER,
-       ATH10K_HW_4ADDR_PAD_BEFORE,
-};
-
 enum ath10k_hw_cc_wraparound_type {
        ATH10K_HW_CC_WRAP_DISABLED = 0,
 
@@ -395,9 +390,6 @@ struct ath10k_hw_params {
         */
        u32 max_probe_resp_desc_thres;
 
-       /* The padding bytes's location is different on various chips */
-       enum ath10k_hw_4addr_pad hw_4addr_pad;
-
        u32 tx_chain_mask;
        u32 rx_chain_mask;
        u32 max_spatial_stream;