ARM: dts: STi: STiH407: clock configuration to address 720p and 1080p
authorGabriel Fernandez <gabriel.fernandez@st.com>
Mon, 29 Aug 2016 12:27:00 +0000 (14:27 +0200)
committerPatrice Chotard <patrice.chotard@st.com>
Fri, 16 Sep 2016 07:42:12 +0000 (09:42 +0200)
It is necessary to properly configure these clocks in order
to address 720p and 1080p HDMI resolution.

Signed-off-by: Vincent Abriou <vincent.abriou@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
arch/arm/boot/dts/stih407.dtsi

index d60f0d8..291ffac 100644 (file)
                        #size-cells = <1>;
 
                        assigned-clocks = <&clk_s_d2_quadfs 0>,
-                                         <&clk_s_d2_quadfs 0>,
+                                         <&clk_s_d2_quadfs 1>,
+                                         <&clk_s_c0_pll1 0>,
+                                         <&clk_s_c0_flexgen CLK_COMPO_DVP>,
+                                         <&clk_s_c0_flexgen CLK_MAIN_DISP>,
                                          <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
                                          <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
                                          <&clk_s_d2_flexgen CLK_PIX_GDP1>,
 
                        assigned-clock-parents = <0>,
                                                 <0>,
+                                                <0>,
+                                                <&clk_s_c0_pll1 0>,
+                                                <&clk_s_c0_pll1 0>,
                                                 <&clk_s_d2_quadfs 0>,
-                                                <&clk_s_d2_quadfs 0>,
+                                                <&clk_s_d2_quadfs 1>,
                                                 <&clk_s_d2_quadfs 0>,
                                                 <&clk_s_d2_quadfs 0>,
                                                 <&clk_s_d2_quadfs 0>,
                                                 <&clk_s_d2_quadfs 0>;
 
-                       assigned-clock-rates = <297000000>, <297000000>;
+                       assigned-clock-rates = <297000000>,
+                                              <108000000>,
+                                              <0>,
+                                              <400000000>,
+                                              <400000000>;
 
                        ranges;