ARCH_INTEGRATOR || \
ARCH_IOP13XX || \
ARCH_KS8695 || \
- (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
+ ARCH_REALVIEW
default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
default 0x20000000 if ARCH_S5PV210
- default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
default 0xc0000000 if ARCH_SA1100
help
Please provide the physical address corresponding to the
select GENERIC_CLOCKEVENTS
select MIGHT_HAVE_PCI
select MULTI_IRQ_HANDLER
+ select PCI_DOMAINS if PCI
select SPARSE_IRQ
select USE_OF
CONFIG_ARCH_MULTI_V5=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_MXC=y
-CONFIG_MACH_SCB9328=y
-CONFIG_MACH_APF9328=y
CONFIG_MACH_MX21ADS=y
CONFIG_MACH_MX27ADS=y
CONFIG_MACH_MX27_3DS=y
CONFIG_MACH_IMX27_VISSTRIM_M10=y
CONFIG_MACH_PCA100=y
CONFIG_MACH_IMX27_DT=y
+CONFIG_SOC_IMX1=y
CONFIG_SOC_IMX25=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_INTEGRATOR_CM920T=y
CONFIG_INTEGRATOR_CM922T_XA10=y
CONFIG_ARCH_MXC=y
-CONFIG_MACH_SCB9328=y
-CONFIG_MACH_APF9328=y
-CONFIG_MACH_IMX1_DT=y
+CONFIG_SOC_IMX1=y
CONFIG_ARCH_NSPIRE=y
CONFIG_AEABI=y
# CONFIG_ATAGS is not set
select ATMEL_ST
select CPU_ARM920T
select HAVE_AT91_USB_CLK
- select MIGHT_HAVE_PCI
select PINCTRL_AT91
select SOC_SAM_V4_V5
select SRAM if PM
select ARM_TIMER_SP804
select HAVE_ARM_ARCH_TIMER
select MFD_SYSCON
- select MIGHT_HAVE_PCI
- select PCI_DOMAINS if PCI
select ZONE_DMA
help
This enables support for the LSI Axxia devices.
+++ /dev/null
-/*
- * linux/arch/arm/mach-clps711x/autcpu12.c
- *
- * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/ioport.h>
-#include <linux/interrupt.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/nand-gpio.h>
-#include <linux/platform_device.h>
-#include <linux/gpio/driver.h>
-
-#include <mach/hardware.h>
-#include <asm/sizes.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices.h"
-
-/* NOR flash */
-#define AUTCPU12_FLASH_BASE (CS0_PHYS_BASE)
-
-/* Board specific hardware definitions */
-#define AUTCPU12_CHAR_LCD_BASE (CS1_PHYS_BASE + 0x00000000)
-#define AUTCPU12_CSAUX1_BASE (CS1_PHYS_BASE + 0x04000000)
-#define AUTCPU12_CAN_BASE (CS1_PHYS_BASE + 0x08000000)
-#define AUTCPU12_TOUCH_BASE (CS1_PHYS_BASE + 0x0a000000)
-#define AUTCPU12_IO_BASE (CS1_PHYS_BASE + 0x0c000000)
-#define AUTCPU12_LPT_BASE (CS1_PHYS_BASE + 0x0e000000)
-
-/* NVRAM */
-#define AUTCPU12_NVRAM_BASE (CS1_PHYS_BASE + 0x02000000)
-
-/* SmartMedia flash */
-#define AUTCPU12_SMC_BASE (CS1_PHYS_BASE + 0x06000000)
-#define AUTCPU12_SMC_SEL_BASE (AUTCPU12_SMC_BASE + 0x10)
-
-/* Ethernet */
-#define AUTCPU12_CS8900_BASE (CS2_PHYS_BASE + 0x300)
-#define AUTCPU12_CS8900_IRQ (IRQ_EINT3)
-
-/* NAND flash */
-#define AUTCPU12_MMGPIO_BASE (CLPS711X_NR_GPIO)
-#define AUTCPU12_SMC_NCE (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
-#define AUTCPU12_SMC_RDY CLPS711X_GPIO(1, 2)
-#define AUTCPU12_SMC_ALE CLPS711X_GPIO(1, 3)
-#define AUTCPU12_SMC_CLE CLPS711X_GPIO(1, 4)
-
-/* LCD contrast digital potentiometer */
-#define AUTCPU12_DPOT_CS CLPS711X_GPIO(4, 0)
-#define AUTCPU12_DPOT_CLK CLPS711X_GPIO(4, 1)
-#define AUTCPU12_DPOT_UD CLPS711X_GPIO(4, 2)
-
-static struct resource autcpu12_cs8900_resource[] __initdata = {
- DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K),
- DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ),
-};
-
-static struct resource autcpu12_nand_resource[] __initdata = {
- DEFINE_RES_MEM(AUTCPU12_SMC_BASE, SZ_16),
-};
-
-static struct mtd_partition autcpu12_nand_parts[] __initdata = {
- {
- .name = "Flash partition 1",
- .offset = 0,
- .size = SZ_8M,
- },
- {
- .name = "Flash partition 2",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static void __init autcpu12_adjust_parts(struct gpio_nand_platdata *pdata,
- size_t sz)
-{
- switch (sz) {
- case SZ_16M:
- case SZ_32M:
- break;
- case SZ_64M:
- case SZ_128M:
- pdata->parts[0].size = SZ_16M;
- break;
- default:
- pr_warn("Unsupported SmartMedia device size %u\n", sz);
- break;
- }
-}
-
-static struct gpio_nand_platdata autcpu12_nand_pdata __initdata = {
- .gpio_rdy = AUTCPU12_SMC_RDY,
- .gpio_nce = AUTCPU12_SMC_NCE,
- .gpio_ale = AUTCPU12_SMC_ALE,
- .gpio_cle = AUTCPU12_SMC_CLE,
- .gpio_nwp = -1,
- .chip_delay = 20,
- .parts = autcpu12_nand_parts,
- .num_parts = ARRAY_SIZE(autcpu12_nand_parts),
- .adjust_parts = autcpu12_adjust_parts,
-};
-
-static struct platform_device autcpu12_nand_pdev __initdata = {
- .name = "gpio-nand",
- .id = -1,
- .resource = autcpu12_nand_resource,
- .num_resources = ARRAY_SIZE(autcpu12_nand_resource),
- .dev = {
- .platform_data = &autcpu12_nand_pdata,
- },
-};
-
-static struct resource autcpu12_mmgpio_resource[] __initdata = {
- DEFINE_RES_MEM_NAMED(AUTCPU12_SMC_SEL_BASE, SZ_1, "dat"),
-};
-
-static struct bgpio_pdata autcpu12_mmgpio_pdata __initdata = {
- .base = AUTCPU12_MMGPIO_BASE,
- .ngpio = 8,
-};
-
-static struct platform_device autcpu12_mmgpio_pdev __initdata = {
- .name = "basic-mmio-gpio",
- .id = -1,
- .resource = autcpu12_mmgpio_resource,
- .num_resources = ARRAY_SIZE(autcpu12_mmgpio_resource),
- .dev = {
- .platform_data = &autcpu12_mmgpio_pdata,
- },
-};
-
-static const struct gpio const autcpu12_gpios[] __initconst = {
- { AUTCPU12_DPOT_CS, GPIOF_OUT_INIT_HIGH, "DPOT CS" },
- { AUTCPU12_DPOT_CLK, GPIOF_OUT_INIT_LOW, "DPOT CLK" },
- { AUTCPU12_DPOT_UD, GPIOF_OUT_INIT_LOW, "DPOT UD" },
-};
-
-static struct mtd_partition autcpu12_flash_partitions[] = {
- {
- .name = "NOR.0",
- .offset = 0,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct physmap_flash_data autcpu12_flash_pdata = {
- .width = 4,
- .parts = autcpu12_flash_partitions,
- .nr_parts = ARRAY_SIZE(autcpu12_flash_partitions),
-};
-
-static struct resource autcpu12_flash_resources[] __initdata = {
- DEFINE_RES_MEM(AUTCPU12_FLASH_BASE, SZ_8M),
-};
-
-static struct platform_device autcpu12_flash_pdev __initdata = {
- .name = "physmap-flash",
- .id = 0,
- .resource = autcpu12_flash_resources,
- .num_resources = ARRAY_SIZE(autcpu12_flash_resources),
- .dev = {
- .platform_data = &autcpu12_flash_pdata,
- },
-};
-
-static struct resource autcpu12_nvram_resource[] __initdata = {
- DEFINE_RES_MEM(AUTCPU12_NVRAM_BASE, 0),
-};
-
-static struct platdata_mtd_ram autcpu12_nvram_pdata = {
- .bankwidth = 4,
-};
-
-static struct platform_device autcpu12_nvram_pdev __initdata = {
- .name = "mtd-ram",
- .id = 0,
- .resource = autcpu12_nvram_resource,
- .num_resources = ARRAY_SIZE(autcpu12_nvram_resource),
- .dev = {
- .platform_data = &autcpu12_nvram_pdata,
- },
-};
-
-static void __init autcpu12_nvram_init(void)
-{
- void __iomem *nvram;
- unsigned int save[2];
- resource_size_t nvram_size = SZ_128K;
-
- /*
- * Check for 32K/128K
- * Read ofs 0K
- * Read ofs 64K
- * Write complement to ofs 64K
- * Read and check result on ofs 0K
- * Restore contents
- */
- nvram = ioremap(autcpu12_nvram_resource[0].start, SZ_128K);
- if (nvram) {
- save[0] = readl(nvram + 0);
- save[1] = readl(nvram + SZ_64K);
- writel(~save[0], nvram + SZ_64K);
- if (readl(nvram + 0) != save[0]) {
- writel(save[0], nvram + 0);
- nvram_size = SZ_32K;
- } else
- writel(save[1], nvram + SZ_64K);
- iounmap(nvram);
-
- autcpu12_nvram_resource[0].end =
- autcpu12_nvram_resource[0].start + nvram_size - 1;
- platform_device_register(&autcpu12_nvram_pdev);
- } else
- pr_err("Failed to remap NVRAM resource\n");
-}
-
-static void __init autcpu12_init(void)
-{
- clps711x_devices_init();
- platform_device_register(&autcpu12_flash_pdev);
- platform_device_register_simple("video-clps711x", 0, NULL, 0);
- platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource,
- ARRAY_SIZE(autcpu12_cs8900_resource));
- platform_device_register(&autcpu12_mmgpio_pdev);
- autcpu12_nvram_init();
-}
-
-static void __init autcpu12_init_late(void)
-{
- gpio_request_array(autcpu12_gpios, ARRAY_SIZE(autcpu12_gpios));
- platform_device_register(&autcpu12_nand_pdev);
-}
-
-MACHINE_START(AUTCPU12, "autronix autcpu12")
- /* Maintainer: Thomas Gleixner */
- .atag_offset = 0x20000,
- .map_io = clps711x_map_io,
- .init_irq = clps711x_init_irq,
- .init_time = clps711x_timer_init,
- .init_machine = autcpu12_init,
- .init_late = autcpu12_init_late,
- .restart = clps711x_restart,
-MACHINE_END
-
+++ /dev/null
-/*
- * linux/arch/arm/mach-clps711x/cdb89712.c
- *
- * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/mtd/partitions.h>
-
-#include <mach/hardware.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices.h"
-
-#define CDB89712_CS8900_BASE (CS2_PHYS_BASE + 0x300)
-#define CDB89712_CS8900_IRQ (IRQ_EINT3)
-
-static struct resource cdb89712_cs8900_resource[] __initdata = {
- DEFINE_RES_MEM(CDB89712_CS8900_BASE, SZ_1K),
- DEFINE_RES_IRQ(CDB89712_CS8900_IRQ),
-};
-
-static struct mtd_partition cdb89712_flash_partitions[] __initdata = {
- {
- .name = "Flash",
- .offset = 0,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct physmap_flash_data cdb89712_flash_pdata __initdata = {
- .width = 4,
- .probe_type = "map_rom",
- .parts = cdb89712_flash_partitions,
- .nr_parts = ARRAY_SIZE(cdb89712_flash_partitions),
-};
-
-static struct resource cdb89712_flash_resources[] __initdata = {
- DEFINE_RES_MEM(CS0_PHYS_BASE, SZ_8M),
-};
-
-static struct platform_device cdb89712_flash_pdev __initdata = {
- .name = "physmap-flash",
- .id = 0,
- .resource = cdb89712_flash_resources,
- .num_resources = ARRAY_SIZE(cdb89712_flash_resources),
- .dev = {
- .platform_data = &cdb89712_flash_pdata,
- },
-};
-
-static struct mtd_partition cdb89712_bootrom_partitions[] __initdata = {
- {
- .name = "BootROM",
- .offset = 0,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct physmap_flash_data cdb89712_bootrom_pdata __initdata = {
- .width = 4,
- .probe_type = "map_rom",
- .parts = cdb89712_bootrom_partitions,
- .nr_parts = ARRAY_SIZE(cdb89712_bootrom_partitions),
-};
-
-static struct resource cdb89712_bootrom_resources[] __initdata = {
- DEFINE_RES_NAMED(CS7_PHYS_BASE, SZ_128, "BOOTROM", IORESOURCE_MEM |
- IORESOURCE_READONLY),
-};
-
-static struct platform_device cdb89712_bootrom_pdev __initdata = {
- .name = "physmap-flash",
- .id = 1,
- .resource = cdb89712_bootrom_resources,
- .num_resources = ARRAY_SIZE(cdb89712_bootrom_resources),
- .dev = {
- .platform_data = &cdb89712_bootrom_pdata,
- },
-};
-
-static struct platdata_mtd_ram cdb89712_sram_pdata __initdata = {
- .bankwidth = 4,
-};
-
-static struct resource cdb89712_sram_resources[] __initdata = {
- DEFINE_RES_MEM(CLPS711X_SRAM_BASE, CLPS711X_SRAM_SIZE),
-};
-
-static struct platform_device cdb89712_sram_pdev __initdata = {
- .name = "mtd-ram",
- .id = 0,
- .resource = cdb89712_sram_resources,
- .num_resources = ARRAY_SIZE(cdb89712_sram_resources),
- .dev = {
- .platform_data = &cdb89712_sram_pdata,
- },
-};
-
-static void __init cdb89712_init(void)
-{
- clps711x_devices_init();
- platform_device_register(&cdb89712_flash_pdev);
- platform_device_register(&cdb89712_bootrom_pdev);
- platform_device_register(&cdb89712_sram_pdev);
- platform_device_register_simple("cs89x0", 0, cdb89712_cs8900_resource,
- ARRAY_SIZE(cdb89712_cs8900_resource));
-}
-
-MACHINE_START(CDB89712, "Cirrus-CDB89712")
- /* Maintainer: Ray Lehtiniemi */
- .atag_offset = 0x100,
- .map_io = clps711x_map_io,
- .init_irq = clps711x_init_irq,
- .init_time = clps711x_timer_init,
- .init_machine = cdb89712_init,
- .restart = clps711x_restart,
-MACHINE_END
+++ /dev/null
-/*
- * linux/arch/arm/mach-clps711x/clep7312.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/memblock.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "common.h"
-#include "devices.h"
-
-static void __init
-fixup_clep7312(struct tag *tags, char **cmdline)
-{
- memblock_add(0xc0000000, 0x01000000);
-}
-
-MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
- /* Maintainer: Nobody */
- .atag_offset = 0x0100,
- .fixup = fixup_clep7312,
- .map_io = clps711x_map_io,
- .init_irq = clps711x_init_irq,
- .init_time = clps711x_timer_init,
- .init_machine = clps711x_devices_init,
- .restart = clps711x_restart,
-MACHINE_END
+++ /dev/null
-/*
- * Copyright (C) 2000, 2001 Blue Mug, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/memblock.h>
-#include <linux/types.h>
-#include <linux/i2c-gpio.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/memblock.h>
-
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/partitions.h>
-
-#include <asm/setup.h>
-#include <asm/mach/map.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <video/platform_lcd.h>
-
-#include <mach/hardware.h>
-
-#include "common.h"
-#include "devices.h"
-
-#define VIDEORAM_SIZE SZ_128K
-
-#define EDB7211_LCD_DC_DC_EN CLPS711X_GPIO(3, 1)
-#define EDB7211_LCDEN CLPS711X_GPIO(3, 2)
-#define EDB7211_LCDBL CLPS711X_GPIO(3, 3)
-
-#define EDB7211_I2C_SDA CLPS711X_GPIO(3, 4)
-#define EDB7211_I2C_SCL CLPS711X_GPIO(3, 5)
-
-#define EDB7211_FLASH0_BASE (CS0_PHYS_BASE)
-#define EDB7211_FLASH1_BASE (CS1_PHYS_BASE)
-
-#define EDB7211_CS8900_BASE (CS2_PHYS_BASE + 0x300)
-#define EDB7211_CS8900_IRQ (IRQ_EINT3)
-
-/* The extra 8 lines of the keyboard matrix */
-#define EDB7211_EXTKBD_BASE (CS3_PHYS_BASE)
-
-static struct i2c_gpio_platform_data edb7211_i2c_pdata __initdata = {
- .sda_pin = EDB7211_I2C_SDA,
- .scl_pin = EDB7211_I2C_SCL,
- .scl_is_output_only = 1,
-};
-
-static struct resource edb7211_cs8900_resource[] __initdata = {
- DEFINE_RES_MEM(EDB7211_CS8900_BASE, SZ_1K),
- DEFINE_RES_IRQ(EDB7211_CS8900_IRQ),
-};
-
-static struct mtd_partition edb7211_flash_partitions[] __initdata = {
- {
- .name = "Flash",
- .offset = 0,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct physmap_flash_data edb7211_flash_pdata __initdata = {
- .width = 4,
- .parts = edb7211_flash_partitions,
- .nr_parts = ARRAY_SIZE(edb7211_flash_partitions),
-};
-
-static struct resource edb7211_flash_resources[] __initdata = {
- DEFINE_RES_MEM(EDB7211_FLASH0_BASE, SZ_8M),
- DEFINE_RES_MEM(EDB7211_FLASH1_BASE, SZ_8M),
-};
-
-static struct platform_device edb7211_flash_pdev __initdata = {
- .name = "physmap-flash",
- .id = 0,
- .resource = edb7211_flash_resources,
- .num_resources = ARRAY_SIZE(edb7211_flash_resources),
- .dev = {
- .platform_data = &edb7211_flash_pdata,
- },
-};
-
-static void edb7211_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
-{
- if (power) {
- gpio_set_value(EDB7211_LCDEN, 1);
- udelay(100);
- gpio_set_value(EDB7211_LCD_DC_DC_EN, 1);
- } else {
- gpio_set_value(EDB7211_LCD_DC_DC_EN, 0);
- udelay(100);
- gpio_set_value(EDB7211_LCDEN, 0);
- }
-}
-
-static struct plat_lcd_data edb7211_lcd_power_pdata = {
- .set_power = edb7211_lcd_power_set,
-};
-
-static struct pwm_lookup edb7211_pwm_lookup[] = {
- PWM_LOOKUP("clps711x-pwm", 0, "pwm-backlight.0", NULL,
- 0, PWM_POLARITY_NORMAL),
-};
-
-static struct platform_pwm_backlight_data pwm_bl_pdata = {
- .dft_brightness = 0x01,
- .max_brightness = 0x0f,
- .enable_gpio = EDB7211_LCDBL,
-};
-
-static struct resource clps711x_pwm_res =
- DEFINE_RES_MEM(CLPS711X_PHYS_BASE + PMPCON, SZ_4);
-
-static struct gpio edb7211_gpios[] __initconst = {
- { EDB7211_LCD_DC_DC_EN, GPIOF_OUT_INIT_LOW, "LCD DC-DC" },
- { EDB7211_LCDEN, GPIOF_OUT_INIT_LOW, "LCD POWER" },
-};
-
-/* Reserve screen memory region at the start of main system memory. */
-static void __init edb7211_reserve(void)
-{
- memblock_reserve(PHYS_OFFSET, VIDEORAM_SIZE);
-}
-
-static void __init
-fixup_edb7211(struct tag *tags, char **cmdline)
-{
- /*
- * Bank start addresses are not present in the information
- * passed in from the boot loader. We could potentially
- * detect them, but instead we hard-code them.
- *
- * Banks sizes _are_ present in the param block, but we're
- * not using that information yet.
- */
- memblock_add(0xc0000000, SZ_8M);
- memblock_add(0xc1000000, SZ_8M);
-}
-
-static void __init edb7211_init_late(void)
-{
- gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios));
-
- platform_device_register(&edb7211_flash_pdev);
-
- platform_device_register_data(NULL, "platform-lcd", 0,
- &edb7211_lcd_power_pdata,
- sizeof(edb7211_lcd_power_pdata));
-
- platform_device_register_simple("clps711x-pwm", PLATFORM_DEVID_NONE,
- &clps711x_pwm_res, 1);
- pwm_add_table(edb7211_pwm_lookup, ARRAY_SIZE(edb7211_pwm_lookup));
-
- platform_device_register_data(&platform_bus, "pwm-backlight", 0,
- &pwm_bl_pdata, sizeof(pwm_bl_pdata));
-
- platform_device_register_simple("video-clps711x", 0, NULL, 0);
- platform_device_register_simple("cs89x0", 0, edb7211_cs8900_resource,
- ARRAY_SIZE(edb7211_cs8900_resource));
- platform_device_register_data(NULL, "i2c-gpio", 0,
- &edb7211_i2c_pdata,
- sizeof(edb7211_i2c_pdata));
-}
-
-MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
- /* Maintainer: Jon McClintock */
- .atag_offset = VIDEORAM_SIZE + 0x100,
- .fixup = fixup_edb7211,
- .reserve = edb7211_reserve,
- .map_io = clps711x_map_io,
- .init_irq = clps711x_init_irq,
- .init_time = clps711x_timer_init,
- .init_machine = clps711x_devices_init,
- .init_late = edb7211_init_late,
- .restart = clps711x_restart,
-MACHINE_END
+++ /dev/null
-/*
- * linux/arch/arm/mach-clps711x/p720t.c
- *
- * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/slab.h>
-#include <linux/leds.h>
-#include <linux/sizes.h>
-#include <linux/backlight.h>
-#include <linux/gpio/driver.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/nand-gpio.h>
-
-#include <mach/hardware.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <video/platform_lcd.h>
-
-#include "common.h"
-#include "devices.h"
-
-#define P720T_USERLED CLPS711X_GPIO(3, 0)
-#define P720T_NAND_CLE CLPS711X_GPIO(4, 0)
-#define P720T_NAND_ALE CLPS711X_GPIO(4, 1)
-#define P720T_NAND_NCE CLPS711X_GPIO(4, 2)
-
-#define P720T_NAND_BASE (CLPS711X_SDRAM1_BASE)
-
-#define P720T_MMGPIO_BASE (CLPS711X_NR_GPIO)
-
-#define SYSPLD_PHYS_BASE IOMEM(CS1_PHYS_BASE)
-
-#define PLD_INT (SYSPLD_PHYS_BASE + 0x000000)
-#define PLD_INT_MMGPIO_BASE (P720T_MMGPIO_BASE + 0)
-#define PLD_INT_PENIRQ (PLD_INT_MMGPIO_BASE + 5)
-#define PLD_INT_UCB_IRQ (PLD_INT_MMGPIO_BASE + 1)
-#define PLD_INT_KBD_ATN (PLD_INT_MMGPIO_BASE + 0) /* EINT1 */
-
-#define PLD_PWR (SYSPLD_PHYS_BASE + 0x000004)
-#define PLD_PWR_MMGPIO_BASE (P720T_MMGPIO_BASE + 8)
-#define PLD_PWR_EXT (PLD_PWR_MMGPIO_BASE + 5)
-#define PLD_PWR_MODE (PLD_PWR_MMGPIO_BASE + 4) /* 1 = PWM, 0 = PFM */
-#define PLD_S4_ON (PLD_PWR_MMGPIO_BASE + 3) /* LCD bias voltage enable */
-#define PLD_S3_ON (PLD_PWR_MMGPIO_BASE + 2) /* LCD backlight enable */
-#define PLD_S2_ON (PLD_PWR_MMGPIO_BASE + 1) /* LCD 3V3 supply enable */
-#define PLD_S1_ON (PLD_PWR_MMGPIO_BASE + 0) /* LCD 3V supply enable */
-
-#define PLD_KBD (SYSPLD_PHYS_BASE + 0x000008)
-#define PLD_KBD_MMGPIO_BASE (P720T_MMGPIO_BASE + 16)
-#define PLD_KBD_WAKE (PLD_KBD_MMGPIO_BASE + 1)
-#define PLD_KBD_EN (PLD_KBD_MMGPIO_BASE + 0)
-
-#define PLD_SPI (SYSPLD_PHYS_BASE + 0x00000c)
-#define PLD_SPI_MMGPIO_BASE (P720T_MMGPIO_BASE + 24)
-#define PLD_SPI_EN (PLD_SPI_MMGPIO_BASE + 0)
-
-#define PLD_IO (SYSPLD_PHYS_BASE + 0x000010)
-#define PLD_IO_MMGPIO_BASE (P720T_MMGPIO_BASE + 32)
-#define PLD_IO_BOOTSEL (PLD_IO_MMGPIO_BASE + 6) /* Boot sel switch */
-#define PLD_IO_USER (PLD_IO_MMGPIO_BASE + 5) /* User defined switch */
-#define PLD_IO_LED3 (PLD_IO_MMGPIO_BASE + 4)
-#define PLD_IO_LED2 (PLD_IO_MMGPIO_BASE + 3)
-#define PLD_IO_LED1 (PLD_IO_MMGPIO_BASE + 2)
-#define PLD_IO_LED0 (PLD_IO_MMGPIO_BASE + 1)
-#define PLD_IO_LEDEN (PLD_IO_MMGPIO_BASE + 0)
-
-#define PLD_IRDA (SYSPLD_PHYS_BASE + 0x000014)
-#define PLD_IRDA_MMGPIO_BASE (P720T_MMGPIO_BASE + 40)
-#define PLD_IRDA_EN (PLD_IRDA_MMGPIO_BASE + 0)
-
-#define PLD_COM2 (SYSPLD_PHYS_BASE + 0x000018)
-#define PLD_COM2_MMGPIO_BASE (P720T_MMGPIO_BASE + 48)
-#define PLD_COM2_EN (PLD_COM2_MMGPIO_BASE + 0)
-
-#define PLD_COM1 (SYSPLD_PHYS_BASE + 0x00001c)
-#define PLD_COM1_MMGPIO_BASE (P720T_MMGPIO_BASE + 56)
-#define PLD_COM1_EN (PLD_COM1_MMGPIO_BASE + 0)
-
-#define PLD_AUD (SYSPLD_PHYS_BASE + 0x000020)
-#define PLD_AUD_MMGPIO_BASE (P720T_MMGPIO_BASE + 64)
-#define PLD_AUD_DIV1 (PLD_AUD_MMGPIO_BASE + 6)
-#define PLD_AUD_DIV0 (PLD_AUD_MMGPIO_BASE + 5)
-#define PLD_AUD_CLK_SEL1 (PLD_AUD_MMGPIO_BASE + 4)
-#define PLD_AUD_CLK_SEL0 (PLD_AUD_MMGPIO_BASE + 3)
-#define PLD_AUD_MIC_PWR (PLD_AUD_MMGPIO_BASE + 2)
-#define PLD_AUD_MIC_GAIN (PLD_AUD_MMGPIO_BASE + 1)
-#define PLD_AUD_CODEC_EN (PLD_AUD_MMGPIO_BASE + 0)
-
-#define PLD_CF (SYSPLD_PHYS_BASE + 0x000024)
-#define PLD_CF_MMGPIO_BASE (P720T_MMGPIO_BASE + 72)
-#define PLD_CF2_SLEEP (PLD_CF_MMGPIO_BASE + 5)
-#define PLD_CF1_SLEEP (PLD_CF_MMGPIO_BASE + 4)
-#define PLD_CF2_nPDREQ (PLD_CF_MMGPIO_BASE + 3)
-#define PLD_CF1_nPDREQ (PLD_CF_MMGPIO_BASE + 2)
-#define PLD_CF2_nIRQ (PLD_CF_MMGPIO_BASE + 1)
-#define PLD_CF1_nIRQ (PLD_CF_MMGPIO_BASE + 0)
-
-#define PLD_SDC (SYSPLD_PHYS_BASE + 0x000028)
-#define PLD_SDC_MMGPIO_BASE (P720T_MMGPIO_BASE + 80)
-#define PLD_SDC_INT_EN (PLD_SDC_MMGPIO_BASE + 2)
-#define PLD_SDC_WP (PLD_SDC_MMGPIO_BASE + 1)
-#define PLD_SDC_CD (PLD_SDC_MMGPIO_BASE + 0)
-
-#define PLD_CODEC (SYSPLD_PHYS_BASE + 0x400000)
-#define PLD_CODEC_MMGPIO_BASE (P720T_MMGPIO_BASE + 88)
-#define PLD_CODEC_IRQ3 (PLD_CODEC_MMGPIO_BASE + 4)
-#define PLD_CODEC_IRQ2 (PLD_CODEC_MMGPIO_BASE + 3)
-#define PLD_CODEC_IRQ1 (PLD_CODEC_MMGPIO_BASE + 2)
-#define PLD_CODEC_EN (PLD_CODEC_MMGPIO_BASE + 0)
-
-#define PLD_BRITE (SYSPLD_PHYS_BASE + 0x400004)
-#define PLD_BRITE_MMGPIO_BASE (P720T_MMGPIO_BASE + 96)
-#define PLD_BRITE_UP (PLD_BRITE_MMGPIO_BASE + 1)
-#define PLD_BRITE_DN (PLD_BRITE_MMGPIO_BASE + 0)
-
-#define PLD_LCDEN (SYSPLD_PHYS_BASE + 0x400008)
-#define PLD_LCDEN_MMGPIO_BASE (P720T_MMGPIO_BASE + 104)
-#define PLD_LCDEN_EN (PLD_LCDEN_MMGPIO_BASE + 0)
-
-#define PLD_TCH (SYSPLD_PHYS_BASE + 0x400010)
-#define PLD_TCH_MMGPIO_BASE (P720T_MMGPIO_BASE + 112)
-#define PLD_TCH_PENIRQ (PLD_TCH_MMGPIO_BASE + 1)
-#define PLD_TCH_EN (PLD_TCH_MMGPIO_BASE + 0)
-
-#define PLD_GPIO (SYSPLD_PHYS_BASE + 0x400014)
-#define PLD_GPIO_MMGPIO_BASE (P720T_MMGPIO_BASE + 120)
-#define PLD_GPIO2 (PLD_GPIO_MMGPIO_BASE + 2)
-#define PLD_GPIO1 (PLD_GPIO_MMGPIO_BASE + 1)
-#define PLD_GPIO0 (PLD_GPIO_MMGPIO_BASE + 0)
-
-static struct gpio p720t_gpios[] __initconst = {
- { PLD_S1_ON, GPIOF_OUT_INIT_LOW, "PLD_S1_ON" },
- { PLD_S2_ON, GPIOF_OUT_INIT_LOW, "PLD_S2_ON" },
- { PLD_S3_ON, GPIOF_OUT_INIT_LOW, "PLD_S3_ON" },
- { PLD_S4_ON, GPIOF_OUT_INIT_LOW, "PLD_S4_ON" },
- { PLD_KBD_EN, GPIOF_OUT_INIT_LOW, "PLD_KBD_EN" },
- { PLD_SPI_EN, GPIOF_OUT_INIT_LOW, "PLD_SPI_EN" },
- { PLD_IO_USER, GPIOF_OUT_INIT_LOW, "PLD_IO_USER" },
- { PLD_IO_LED0, GPIOF_OUT_INIT_LOW, "PLD_IO_LED0" },
- { PLD_IO_LED1, GPIOF_OUT_INIT_LOW, "PLD_IO_LED1" },
- { PLD_IO_LED2, GPIOF_OUT_INIT_LOW, "PLD_IO_LED2" },
- { PLD_IO_LED3, GPIOF_OUT_INIT_LOW, "PLD_IO_LED3" },
- { PLD_IO_LEDEN, GPIOF_OUT_INIT_LOW, "PLD_IO_LEDEN" },
- { PLD_IRDA_EN, GPIOF_OUT_INIT_LOW, "PLD_IRDA_EN" },
- { PLD_COM1_EN, GPIOF_OUT_INIT_HIGH, "PLD_COM1_EN" },
- { PLD_COM2_EN, GPIOF_OUT_INIT_HIGH, "PLD_COM2_EN" },
- { PLD_CODEC_EN, GPIOF_OUT_INIT_LOW, "PLD_CODEC_EN" },
- { PLD_LCDEN_EN, GPIOF_OUT_INIT_LOW, "PLD_LCDEN_EN" },
- { PLD_TCH_EN, GPIOF_OUT_INIT_LOW, "PLD_TCH_EN" },
- { P720T_USERLED,GPIOF_OUT_INIT_LOW, "USER_LED" },
-};
-
-static struct resource p720t_mmgpio_resource[] __initdata = {
- DEFINE_RES_MEM_NAMED(0, 4, "dat"),
-};
-
-static struct bgpio_pdata p720t_mmgpio_pdata = {
- .ngpio = 8,
-};
-
-static struct platform_device p720t_mmgpio __initdata = {
- .name = "basic-mmio-gpio",
- .id = -1,
- .resource = p720t_mmgpio_resource,
- .num_resources = ARRAY_SIZE(p720t_mmgpio_resource),
- .dev = {
- .platform_data = &p720t_mmgpio_pdata,
- },
-};
-
-static void __init p720t_mmgpio_init(void __iomem *addrbase, int gpiobase)
-{
- p720t_mmgpio_resource[0].start = (unsigned long)addrbase;
- p720t_mmgpio_pdata.base = gpiobase;
-
- platform_device_register(&p720t_mmgpio);
-}
-
-static struct {
- void __iomem *addrbase;
- int gpiobase;
-} mmgpios[] __initconst = {
- { PLD_INT, PLD_INT_MMGPIO_BASE },
- { PLD_PWR, PLD_PWR_MMGPIO_BASE },
- { PLD_KBD, PLD_KBD_MMGPIO_BASE },
- { PLD_SPI, PLD_SPI_MMGPIO_BASE },
- { PLD_IO, PLD_IO_MMGPIO_BASE },
- { PLD_IRDA, PLD_IRDA_MMGPIO_BASE },
- { PLD_COM2, PLD_COM2_MMGPIO_BASE },
- { PLD_COM1, PLD_COM1_MMGPIO_BASE },
- { PLD_AUD, PLD_AUD_MMGPIO_BASE },
- { PLD_CF, PLD_CF_MMGPIO_BASE },
- { PLD_SDC, PLD_SDC_MMGPIO_BASE },
- { PLD_CODEC, PLD_CODEC_MMGPIO_BASE },
- { PLD_BRITE, PLD_BRITE_MMGPIO_BASE },
- { PLD_LCDEN, PLD_LCDEN_MMGPIO_BASE },
- { PLD_TCH, PLD_TCH_MMGPIO_BASE },
- { PLD_GPIO, PLD_GPIO_MMGPIO_BASE },
-};
-
-static struct resource p720t_nand_resource[] __initdata = {
- DEFINE_RES_MEM(P720T_NAND_BASE, SZ_4),
-};
-
-static struct mtd_partition p720t_nand_parts[] __initdata = {
- {
- .name = "Flash partition 1",
- .offset = 0,
- .size = SZ_2M,
- },
- {
- .name = "Flash partition 2",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct gpio_nand_platdata p720t_nand_pdata __initdata = {
- .gpio_rdy = -1,
- .gpio_nce = P720T_NAND_NCE,
- .gpio_ale = P720T_NAND_ALE,
- .gpio_cle = P720T_NAND_CLE,
- .gpio_nwp = -1,
- .chip_delay = 15,
- .parts = p720t_nand_parts,
- .num_parts = ARRAY_SIZE(p720t_nand_parts),
-};
-
-static struct platform_device p720t_nand_pdev __initdata = {
- .name = "gpio-nand",
- .id = -1,
- .resource = p720t_nand_resource,
- .num_resources = ARRAY_SIZE(p720t_nand_resource),
- .dev = {
- .platform_data = &p720t_nand_pdata,
- },
-};
-
-static void p720t_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
-{
- if (power) {
- gpio_set_value(PLD_LCDEN_EN, 1);
- gpio_set_value(PLD_S1_ON, 1);
- gpio_set_value(PLD_S2_ON, 1);
- gpio_set_value(PLD_S4_ON, 1);
- } else {
- gpio_set_value(PLD_S1_ON, 0);
- gpio_set_value(PLD_S2_ON, 0);
- gpio_set_value(PLD_S4_ON, 0);
- gpio_set_value(PLD_LCDEN_EN, 0);
- }
-}
-
-static struct plat_lcd_data p720t_lcd_power_pdata = {
- .set_power = p720t_lcd_power_set,
-};
-
-static void p720t_lcd_backlight_set_intensity(int intensity)
-{
- gpio_set_value(PLD_S3_ON, intensity);
-}
-
-static struct generic_bl_info p720t_lcd_backlight_pdata = {
- .name = "lcd-backlight.0",
- .default_intensity = 0x01,
- .max_intensity = 0x01,
- .set_bl_intensity = p720t_lcd_backlight_set_intensity,
-};
-
-static void __init
-fixup_p720t(struct tag *tag, char **cmdline)
-{
- /*
- * Our bootloader doesn't setup any tags (yet).
- */
- if (tag->hdr.tag != ATAG_CORE) {
- tag->hdr.tag = ATAG_CORE;
- tag->hdr.size = tag_size(tag_core);
- tag->u.core.flags = 0;
- tag->u.core.pagesize = PAGE_SIZE;
- tag->u.core.rootdev = 0x0100;
-
- tag = tag_next(tag);
- tag->hdr.tag = ATAG_MEM;
- tag->hdr.size = tag_size(tag_mem32);
- tag->u.mem.size = 4096;
- tag->u.mem.start = PHYS_OFFSET;
-
- tag = tag_next(tag);
- tag->hdr.tag = ATAG_NONE;
- tag->hdr.size = 0;
- }
-}
-
-static struct gpio_led p720t_gpio_leds[] = {
- {
- .name = "User LED",
- .default_trigger = "heartbeat",
- .gpio = P720T_USERLED,
- },
-};
-
-static struct gpio_led_platform_data p720t_gpio_led_pdata __initdata = {
- .leds = p720t_gpio_leds,
- .num_leds = ARRAY_SIZE(p720t_gpio_leds),
-};
-
-static void __init p720t_init(void)
-{
- int i;
-
- clps711x_devices_init();
-
- for (i = 0; i < ARRAY_SIZE(mmgpios); i++)
- p720t_mmgpio_init(mmgpios[i].addrbase, mmgpios[i].gpiobase);
-
- platform_device_register(&p720t_nand_pdev);
-}
-
-static void __init p720t_init_late(void)
-{
- WARN_ON(gpio_request_array(p720t_gpios, ARRAY_SIZE(p720t_gpios)));
-
- platform_device_register_data(NULL, "platform-lcd", 0,
- &p720t_lcd_power_pdata,
- sizeof(p720t_lcd_power_pdata));
- platform_device_register_data(NULL, "generic-bl", 0,
- &p720t_lcd_backlight_pdata,
- sizeof(p720t_lcd_backlight_pdata));
- platform_device_register_simple("video-clps711x", 0, NULL, 0);
- platform_device_register_data(NULL, "leds-gpio", 0,
- &p720t_gpio_led_pdata,
- sizeof(p720t_gpio_led_pdata));
-}
-
-MACHINE_START(P720T, "ARM-Prospector720T")
- /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
- .atag_offset = 0x100,
- .fixup = fixup_p720t,
- .map_io = clps711x_map_io,
- .init_irq = clps711x_init_irq,
- .init_time = clps711x_timer_init,
- .init_machine = p720t_init,
- .init_late = p720t_init_late,
- .restart = clps711x_restart,
-MACHINE_END
+++ /dev/null
-/*
- * linux/arch/arm/mach-clps711x/core.c
- *
- * Core support for the CLPS711x-based machines.
- *
- * Copyright (C) 2001,2011 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include <linux/init.h>
-#include <linux/sizes.h>
-
-#include <asm/mach/map.h>
-#include <asm/system_misc.h>
-
-#include <mach/hardware.h>
-
-#include "common.h"
-
-/*
- * This maps the generic CLPS711x registers
- */
-static struct map_desc clps711x_io_desc[] __initdata = {
- {
- .virtual = (unsigned long)CLPS711X_VIRT_BASE,
- .pfn = __phys_to_pfn(CLPS711X_PHYS_BASE),
- .length = 48 * SZ_1K,
- .type = MT_DEVICE,
- }
-};
-
-void __init clps711x_map_io(void)
-{
- iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
-}
-
-void __init clps711x_init_irq(void)
-{
- clps711x_intc_init(CLPS711X_PHYS_BASE, SZ_16K);
-}
-
-void __init clps711x_timer_init(void)
-{
- clps711x_clk_init(CLPS711X_VIRT_BASE);
- clps711x_clksrc_init(CLPS711X_VIRT_BASE + TC1D,
- CLPS711X_VIRT_BASE + TC2D, IRQ_TC2OI);
-}
-
-void clps711x_restart(enum reboot_mode mode, const char *cmd)
-{
- soft_restart(0);
-}
+++ /dev/null
-/*
- * linux/arch/arm/mach-clps711x/common.h
- *
- * Common bits.
- */
-
-#include <linux/reboot.h>
-
-#define CLPS711X_NR_GPIO (4 * 8 + 3)
-#define CLPS711X_GPIO(prt, bit) ((prt) * 8 + (bit))
-
-extern void clps711x_map_io(void);
-extern void clps711x_init_irq(void);
-extern void clps711x_timer_init(void);
-extern void clps711x_restart(enum reboot_mode mode, const char *cmd);
-
-/* drivers/irqchip/irq-clps711x.c */
-void clps711x_intc_init(phys_addr_t, resource_size_t);
-/* drivers/clk/clk-clps711x.c */
-void clps711x_clk_init(void __iomem *base);
-/* drivers/clocksource/clps711x-timer.c */
-void clps711x_clksrc_init(void __iomem *tc1_base, void __iomem *tc2_base,
- unsigned int irq);
+++ /dev/null
-/*
- * CLPS711X common devices definitions
- *
- * Author: Alexander Shiyan <shc_work@mail.ru>, 2013-2014
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/io.h>
-#include <linux/of_fdt.h>
-#include <linux/platform_device.h>
-#include <linux/random.h>
-#include <linux/sizes.h>
-#include <linux/slab.h>
-#include <linux/sys_soc.h>
-
-#include <asm/system_info.h>
-
-#include <mach/hardware.h>
-
-static const struct resource clps711x_cpuidle_res __initconst =
- DEFINE_RES_MEM(CLPS711X_PHYS_BASE + HALT, SZ_128);
-
-static void __init clps711x_add_cpuidle(void)
-{
- platform_device_register_simple("clps711x-cpuidle", PLATFORM_DEVID_NONE,
- &clps711x_cpuidle_res, 1);
-}
-
-static const phys_addr_t clps711x_gpios[][2] __initconst = {
- { PADR, PADDR },
- { PBDR, PBDDR },
- { PCDR, PCDDR },
- { PDDR, PDDDR },
- { PEDR, PEDDR },
-};
-
-static void __init clps711x_add_gpio(void)
-{
- unsigned i;
- struct resource gpio_res[2];
-
- memset(gpio_res, 0, sizeof(gpio_res));
-
- gpio_res[0].flags = IORESOURCE_MEM;
- gpio_res[1].flags = IORESOURCE_MEM;
-
- for (i = 0; i < ARRAY_SIZE(clps711x_gpios); i++) {
- gpio_res[0].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][0];
- gpio_res[0].end = gpio_res[0].start;
- gpio_res[1].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][1];
- gpio_res[1].end = gpio_res[1].start;
-
- platform_device_register_simple("clps711x-gpio", i,
- gpio_res, ARRAY_SIZE(gpio_res));
- }
-}
-
-const struct resource clps711x_syscon_res[] __initconst = {
- /* SYSCON1, SYSFLG1 */
- DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON1, SZ_128),
- /* SYSCON2, SYSFLG2 */
- DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON2, SZ_128),
- /* SYSCON3 */
- DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON3, SZ_64),
-};
-
-static void __init clps711x_add_syscon(void)
-{
- unsigned i;
-
- for (i = 0; i < ARRAY_SIZE(clps711x_syscon_res); i++)
- platform_device_register_simple("syscon", i + 1,
- &clps711x_syscon_res[i], 1);
-}
-
-static const struct resource clps711x_uart1_res[] __initconst = {
- DEFINE_RES_MEM(CLPS711X_PHYS_BASE + UARTDR1, SZ_128),
- DEFINE_RES_IRQ(IRQ_UTXINT1),
- DEFINE_RES_IRQ(IRQ_URXINT1),
-};
-
-static const struct resource clps711x_uart2_res[] __initconst = {
- DEFINE_RES_MEM(CLPS711X_PHYS_BASE + UARTDR2, SZ_128),
- DEFINE_RES_IRQ(IRQ_UTXINT2),
- DEFINE_RES_IRQ(IRQ_URXINT2),
-};
-
-static void __init clps711x_add_uart(void)
-{
- platform_device_register_simple("clps711x-uart", 0, clps711x_uart1_res,
- ARRAY_SIZE(clps711x_uart1_res));
- platform_device_register_simple("clps711x-uart", 1, clps711x_uart2_res,
- ARRAY_SIZE(clps711x_uart2_res));
-};
-
-static void __init clps711x_soc_init(void)
-{
- struct soc_device_attribute *soc_dev_attr;
- struct soc_device *soc_dev;
- void __iomem *base;
- u32 id[5];
-
- base = ioremap(CLPS711X_PHYS_BASE, SZ_32K);
- if (!base)
- return;
-
- id[0] = readl(base + UNIQID);
- id[1] = readl(base + RANDID0);
- id[2] = readl(base + RANDID1);
- id[3] = readl(base + RANDID2);
- id[4] = readl(base + RANDID3);
- system_rev = SYSFLG1_VERID(readl(base + SYSFLG1));
-
- add_device_randomness(id, sizeof(id));
-
- system_serial_low = id[0];
-
- soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
- if (!soc_dev_attr)
- goto out_unmap;
-
- soc_dev_attr->machine = of_flat_dt_get_machine_name();
- soc_dev_attr->family = "Cirrus Logic CLPS711X";
- soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u", system_rev);
- soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%08x", id[0]);
-
- soc_dev = soc_device_register(soc_dev_attr);
- if (IS_ERR(soc_dev)) {
- kfree(soc_dev_attr->revision);
- kfree(soc_dev_attr->soc_id);
- kfree(soc_dev_attr);
- }
-
-out_unmap:
- iounmap(base);
-}
-
-void __init clps711x_devices_init(void)
-{
- clps711x_add_cpuidle();
- clps711x_add_gpio();
- clps711x_add_syscon();
- clps711x_add_uart();
- clps711x_soc_init();
-}
+++ /dev/null
-/*
- * CLPS711X common devices definitions
- *
- * Copyright (C) 2013 Alexander Shiyan <shc_work@mail.ru>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-void clps711x_devices_init(void);
bool "Cavium Networks CNS3XXX family"
depends on ARCH_MULTI_V6
select ARM_GIC
- select PCI_DOMAINS if PCI
help
Support for Cavium Networks CNS3XXX platform.
select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
select HAVE_ARM_ARCH_TIMER
select AUTO_ZRELADDR
- select MIGHT_HAVE_PCI
- select PCI_DOMAINS if PCI
select PINCTRL_EXYNOS5440
select PM_OPP
help
config ARCH_MXC_IOMUX_V3
bool
-config SOC_IMX1
- bool
- select CPU_ARM920T
- select IMX_HAVE_IOMUX_V1
- select MXC_AVIC
- select PINCTRL_IMX1
-
config SOC_IMX21
bool
select CPU_ARM926T
bool
select CPU_V6
select MXC_AVIC
- select SMP_ON_UP if SMP
config SOC_IMX35
bool
select HAVE_EPIT
select MXC_AVIC
select PINCTRL_IMX35
- select SMP_ON_UP if SMP
-
-if ARCH_MULTI_V4T
-
-comment "MX1 platforms:"
-
-config MACH_SCB9328
- bool "Synertronixx scb9328"
- select IMX_HAVE_PLATFORM_IMX_UART
- select SOC_IMX1
- help
- Say Y here if you are using a Synertronixx scb9328 board
-
-config MACH_APF9328
- bool "APF9328"
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_UART
- select SOC_IMX1
- help
- Say Yes here if you are using the Armadeus APF9328 development board
-
-config MACH_IMX1_DT
- bool "Support i.MX1 platforms from device tree"
- select SOC_IMX1
- help
- Include support for Freescale i.MX1 based platforms
- using the device tree for discovery.
-
-endif
if ARCH_MULTI_V5
comment "Device tree only"
+if ARCH_MULTI_V4T
+
+config SOC_IMX1
+ bool "i.MX1 support"
+ select CPU_ARM920T
+ select MXC_AVIC
+ select PINCTRL_IMX1
+ help
+ This enables support for Freescale i.MX1 processor
+
+endif
+
if ARCH_MULTI_V5
config SOC_IMX25
select ARM_ERRATA_764369 if SMP
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD
- select PCI_DOMAINS if PCI
select PINCTRL_IMX6Q
select SOC_IMX6
bool "Freescale LS1021A support"
select ARM_GIC
select HAVE_ARM_ARCH_TIMER
- select PCI_DOMAINS if PCI
select ZONE_DMA if ARM_LPAE
help
This enables support for Freescale LS1021A processor.
select ARM_GIC if ARCH_MULTI_V7
select PINCTRL_VF610
select PL310_ERRATA_769419 if CACHE_L2X0
- select SMP_ON_UP if SMP
help
This enables support for Freescale Vybrid VF610 processor.
obj-y := cpu.o system.o irq-common.o
-obj-$(CONFIG_SOC_IMX1) += mm-imx1.o
obj-$(CONFIG_SOC_IMX21) += mm-imx21.o
obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o
obj-y += ssi-fiq-ksym.o
endif
-# i.MX1 based machines
-obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
-obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o
-obj-$(CONFIG_MACH_IMX1_DT) += imx1-dt.o
-
# i.MX21 based machines
obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
endif
obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
+obj-$(CONFIG_SOC_IMX1) += mach-imx1.o
obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
obj-$(CONFIG_SOC_IMX51) += mach-imx51.o
obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
enum mxc_cpu_pwr_mode;
struct of_device_id;
-void mx1_map_io(void);
void mx21_map_io(void);
void mx27_map_io(void);
void mx31_map_io(void);
void mx35_map_io(void);
-void imx1_init_early(void);
void imx21_init_early(void);
void imx27_init_early(void);
void imx31_init_early(void);
void imx35_init_early(void);
void mxc_init_irq(void __iomem *);
-void mx1_init_irq(void);
void mx21_init_irq(void);
void mx27_init_irq(void);
void mx31_init_irq(void);
void mx35_init_irq(void);
-void imx1_soc_init(void);
void imx21_soc_init(void);
void imx27_soc_init(void);
void imx31_soc_init(void);
void imx35_soc_init(void);
void epit_timer_init(void __iomem *base, int irq);
-int mx1_clocks_init(unsigned long fref);
int mx21_clocks_init(unsigned long lref, unsigned long fref);
int mx27_clocks_init(unsigned long fref);
int mx31_clocks_init(unsigned long fref);
+++ /dev/null
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "devices/devices-common.h"
-
-extern const struct imx_imx_fb_data imx1_imx_fb_data;
-#define imx1_add_imx_fb(pdata) \
- imx_add_imx_fb(&imx1_imx_fb_data, pdata)
-
-extern const struct imx_imx_i2c_data imx1_imx_i2c_data;
-#define imx1_add_imx_i2c(pdata) \
- imx_add_imx_i2c(&imx1_imx_i2c_data, pdata)
-
-extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[];
-#define imx1_add_imx_uart(id, pdata) \
- imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata)
-#define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata)
-#define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata)
-
-extern const struct imx_spi_imx_data imx1_cspi_data[];
-#define imx1_add_cspi(id, pdata) \
- imx_add_spi_imx(&imx1_cspi_data[id], pdata)
-
-#define imx1_add_spi_imx0(pdata) imx1_add_cspi(0, pdata)
-#define imx1_add_spi_imx1(pdata) imx1_add_cspi(1, pdata)
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
const struct imx_ssi_platform_data *pdata);
#include <linux/platform_data/serial-imx.h>
-struct imx_imx_uart_3irq_data {
- int id;
- resource_size_t iobase;
- resource_size_t iosize;
- resource_size_t irqrx;
- resource_size_t irqtx;
- resource_size_t irqrts;
-};
-struct platform_device *__init imx_add_imx_uart_3irq(
- const struct imx_imx_uart_3irq_data *data,
- const struct imxuart_platform_data *pdata);
-
struct imx_imx_uart_1irq_data {
int id;
resource_size_t iobase;
.irq = soc ## _INT_LCDC, \
}
-#ifdef CONFIG_SOC_IMX1
-const struct imx_imx_fb_data imx1_imx_fb_data __initconst =
- imx_imx_fb_data_entry_single(MX1, "imx1-fb", SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX1 */
-
#ifdef CONFIG_SOC_IMX21
const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K);
#define imx_imx_i2c_data_entry(soc, _devid, _id, _hwid, _size) \
[_id] = imx_imx_i2c_data_entry_single(soc, _devid, _id, _hwid, _size)
-#ifdef CONFIG_SOC_IMX1
-const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst =
- imx_imx_i2c_data_entry_single(MX1, "imx1-i2c", 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX1 */
-
#ifdef CONFIG_SOC_IMX21
const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst =
imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K);
.irq = soc ## _INT_UART ## _hwid, \
}
-#ifdef CONFIG_SOC_IMX1
-const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst = {
-#define imx1_imx_uart_data_entry(_id, _hwid) \
- imx_imx_uart_3irq_data_entry(MX1, _id, _hwid, 0xd0)
- imx1_imx_uart_data_entry(0, 1),
- imx1_imx_uart_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX1 */
-
#ifdef CONFIG_SOC_IMX21
const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = {
#define imx21_imx_uart_data_entry(_id, _hwid) \
};
#endif /* ifdef CONFIG_SOC_IMX35 */
-struct platform_device *__init imx_add_imx_uart_3irq(
- const struct imx_imx_uart_3irq_data *data,
- const struct imxuart_platform_data *pdata)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + data->iosize - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irqrx,
- .end = data->irqrx,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = data->irqtx,
- .end = data->irqtx,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = data->irqrts,
- .end = data->irqrx,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- return imx_add_platform_device("imx1-uart", data->id, res,
- ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
-
struct platform_device *__init imx_add_imx_uart_1irq(
const struct imx_imx_uart_1irq_data *data,
const struct imxuart_platform_data *pdata)
#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size) \
[id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size)
-#ifdef CONFIG_SOC_IMX1
-const struct imx_spi_imx_data imx1_cspi_data[] __initconst = {
-#define imx1_cspi_data_entry(_id, _hwid) \
- imx_spi_imx_data_entry(MX1, CSPI, "imx1-cspi", _id, _hwid, SZ_4K)
- imx1_cspi_data_entry(0, 1),
- imx1_cspi_data_entry(1, 2),
-};
-#endif
-
#ifdef CONFIG_SOC_IMX21
const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
#define imx21_cspi_data_entry(_id, _hwid) \
#include "mx2x.h"
#include "mx21.h"
#include "mx27.h"
-#include "mx1.h"
#define imx_map_entry(soc, name, _type) { \
.virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
.type = _type, \
}
-/* There's a off-by-one betweem the gpio bank number and the gpiochip */
+/* There's an off-by-one between the gpio bank number and the gpiochip */
/* range e.g. GPIO_1_5 is gpio 5 under linux */
#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
+++ /dev/null
-/*
- * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/of_platform.h>
-#include <asm/mach/arch.h>
-
-#include "common.h"
-
-static const char * const imx1_dt_board_compat[] __initconst = {
- "fsl,imx1",
- NULL
-};
-
-DT_MACHINE_START(IMX1_DT, "Freescale i.MX1 (Device Tree Support)")
- .map_io = mx1_map_io,
- .init_early = imx1_init_early,
- .init_irq = mx1_init_irq,
- .dt_compat = imx1_dt_board_compat,
- .restart = mxc_restart,
-MACHINE_END
+++ /dev/null
-/*
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#ifndef __MACH_IOMUX_MX1_H__
-#define __MACH_IOMUX_MX1_H__
-
-#include "iomux-v1.h"
-
-#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
-#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0)
-#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1)
-#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1)
-#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2)
-#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3)
-#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4)
-#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5)
-#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6)
-#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7)
-#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8)
-#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9)
-#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10)
-#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11)
-#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12)
-#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13)
-#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14)
-#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
-#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
-#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
-#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
-#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
-#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
-#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
-#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21)
-#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22)
-#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23)
-#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24)
-#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
-#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25)
-#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
-#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26)
-#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
-#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27)
-#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
-#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28)
-#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
-#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29)
-#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
-#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30)
-#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
-#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31)
-#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31)
-#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
-#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8)
-#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9)
-#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9)
-#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10)
-#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10)
-#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11)
-#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11)
-#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12)
-#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12)
-#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
-#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13)
-#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14)
-#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15)
-#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_AF | GPIO_IN | 16)
-#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17)
-#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18)
-#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19)
-#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20)
-#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21)
-#define PB22_PF_USBD_RCV (GPIO_PORTB | GPIO_PF | 22)
-#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23)
-#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24)
-#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25)
-#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26)
-#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27)
-#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28)
-#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_PF | GPIO_IN | 29)
-#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30)
-#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_PF | GPIO_IN | 31)
-#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3)
-#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4)
-#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
-#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6)
-#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7)
-#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8)
-#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
-#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_PF | GPIO_IN | 10)
-#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
-#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 12)
-#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
-#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14)
-#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15)
-#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16)
-#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17)
-#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24)
-#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25)
-#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26)
-#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27)
-#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28)
-#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29)
-#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30)
-#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31)
-#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6)
-#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7)
-#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_AF | GPIO_IN | 7)
-#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7)
-#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8)
-#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8)
-#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8)
-#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9)
-#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9)
-#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9)
-#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10)
-#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10)
-#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10)
-#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11)
-#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12)
-#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13)
-#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14)
-#define PD15_PF_LD0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15)
-#define PD16_PF_LD1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16)
-#define PD17_PF_LD2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
-#define PD18_PF_LD3 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
-#define PD19_PF_LD4 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19)
-#define PD20_PF_LD5 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20)
-#define PD21_PF_LD6 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21)
-#define PD22_PF_LD7 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22)
-#define PD23_PF_LD8 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23)
-#define PD24_PF_LD9 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24)
-#define PD25_PF_LD10 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
-#define PD26_PF_LD11 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
-#define PD27_PF_LD12 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
-#define PD28_PF_LD13 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
-#define PD29_PF_LD14 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
-#define PD30_PF_LD15 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30)
-#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31)
-#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31)
-
-#endif /* ifndef __MACH_IOMUX_MX1_H__ */
#define MX31_PIN_CONTRAST__CONTRAST IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC)
#define MX31_PIN_D3_SPL__D3_SPL IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC)
#define MX31_PIN_D3_CLS__D3_CLS IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LCS0__GPI03_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO)
#define MX31_PIN_GPIO1_1__GPIO IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_I2C_CLK__SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_I2C_DAT__SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2)
#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2)
#define MX31_PIN_CSPI2_SS2__I2C3_SDA IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_ALT1)
#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_ATA_CS0__GPIO3_26 IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_ATA_CS1__GPIO3_27 IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_PC_PWRON__SD2_DATA3 IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_VS1__SD2_DATA2 IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_READY__SD2_DATA1 IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_WAIT_B__SD2_DATA0 IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_CD2_B__SD2_CLK IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_CD1_B__SD2_CMD IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_ATA_DIOR__GPIO3_28 IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_ATA_DIOW__GPIO3_29 IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_CSI_D4__CSI_D4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D5__CSI_D5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D6__CSI_D6 IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D7__CSI_D7 IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D8__CSI_D8 IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D9__CSI_D9 IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D10__CSI_D10 IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D11__CSI_D11 IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D12__CSI_D12 IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D13__CSI_D13 IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D14__CSI_D14 IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D15__CSI_D15 IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_HSYNC__CSI_HSYNC IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_MCLK__CSI_MCLK IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_VSYNC__CSI_VSYNC IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
#define MX31_PIN_GPIO1_0__GPIO1_0 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO)
#define MX31_PIN_SVEN0__GPIO2_0 IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO)
#define MX31_PIN_STX0__GPIO2_1 IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO)
+++ /dev/null
-/*
- * linux/arch/arm/mach-imx/mach-apf9328.c
- *
- * Copyright (c) 2005-2011 ARMadeus systems <support@armadeus.com>
- *
- * This work is based on mach-scb9328.c which is:
- * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de>
- * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/dm9000.h>
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-#include "devices-imx1.h"
-#include "hardware.h"
-#include "iomux-mx1.h"
-
-static const int apf9328_pins[] __initconst = {
- /* UART1 */
- PC9_PF_UART1_CTS,
- PC10_PF_UART1_RTS,
- PC11_PF_UART1_TXD,
- PC12_PF_UART1_RXD,
- /* UART2 */
- PB28_PF_UART2_CTS,
- PB29_PF_UART2_RTS,
- PB30_PF_UART2_TXD,
- PB31_PF_UART2_RXD,
- /* I2C */
- PA15_PF_I2C_SDA,
- PA16_PF_I2C_SCL,
-};
-
-/*
- * The APF9328 can have up to 32MB NOR Flash
- */
-static struct resource flash_resource = {
- .start = MX1_CS0_PHYS,
- .end = MX1_CS0_PHYS + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct physmap_flash_data apf9328_flash_data = {
- .width = 2,
-};
-
-static struct platform_device apf9328_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &apf9328_flash_data,
- },
- .resource = &flash_resource,
- .num_resources = 1,
-};
-
-/*
- * APF9328 has a DM9000 Ethernet controller
- */
-static struct dm9000_plat_data dm9000_setup = {
- .flags = DM9000_PLATF_16BITONLY
-};
-
-static struct resource dm9000_resources[] = {
- {
- .start = MX1_CS4_PHYS + 0x00C00000,
- .end = MX1_CS4_PHYS + 0x00C00001,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MX1_CS4_PHYS + 0x00C00002,
- .end = MX1_CS4_PHYS + 0x00C00003,
- .flags = IORESOURCE_MEM,
- }, {
- /* irq number is run-time assigned */
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct platform_device dm9000x_device = {
- .name = "dm9000",
- .id = 0,
- .num_resources = ARRAY_SIZE(dm9000_resources),
- .resource = dm9000_resources,
- .dev = {
- .platform_data = &dm9000_setup,
- }
-};
-
-static const struct imxuart_platform_data uart1_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct imxi2c_platform_data apf9328_i2c_data __initconst = {
- .bitrate = 100000,
-};
-
-static struct platform_device *devices[] __initdata = {
- &apf9328_flash_device,
- &dm9000x_device,
-};
-
-static void __init apf9328_init(void)
-{
- imx1_soc_init();
-
- mxc_gpio_setup_multiple_pins(apf9328_pins,
- ARRAY_SIZE(apf9328_pins),
- "APF9328");
-
- imx1_add_imx_uart0(NULL);
- imx1_add_imx_uart1(&uart1_pdata);
-
- imx1_add_imx_i2c(&apf9328_i2c_data);
-
- dm9000_resources[2].start = gpio_to_irq(IMX_GPIO_NR(2, 14));
- dm9000_resources[2].end = gpio_to_irq(IMX_GPIO_NR(2, 14));
- platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-static void __init apf9328_timer_init(void)
-{
- mx1_clocks_init(32768);
-}
-
-MACHINE_START(APF9328, "Armadeus APF9328")
- /* Maintainer: Gwenhael Goavec-Merou, ARMadeus Systems */
- .map_io = mx1_map_io,
- .init_early = imx1_init_early,
- .init_irq = mx1_init_irq,
- .init_time = apf9328_timer_init,
- .init_machine = apf9328_init,
- .restart = mxc_restart,
-MACHINE_END
--- /dev/null
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include "common.h"
+#include "hardware.h"
+
+#define MX1_AVIC_ADDR 0x00223000
+
+static void __init imx1_init_early(void)
+{
+ mxc_set_cpu_type(MXC_CPU_MX1);
+}
+
+static void __init imx1_init_irq(void)
+{
+ void __iomem *avic_addr;
+
+ avic_addr = ioremap(MX1_AVIC_ADDR, SZ_4K);
+ WARN_ON(!avic_addr);
+
+ mxc_init_irq(avic_addr);
+}
+
+static const char * const imx1_dt_board_compat[] __initconst = {
+ "fsl,imx1",
+ NULL
+};
+
+DT_MACHINE_START(IMX1_DT, "Freescale i.MX1 (Device Tree Support)")
+ .map_io = debug_ll_io_init,
+ .init_early = imx1_init_early,
+ .init_irq = imx1_init_irq,
+ .dt_compat = imx1_dt_board_compat,
+ .restart = mxc_restart,
+MACHINE_END
*/
#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_8250)
/*
* KZM-ARM11-01 has an external UART on FPGA
*/
/*
* SMSC LAN9118
*/
-#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+#if IS_ENABLED(CONFIG_SMSC911X)
static struct smsc911x_platform_config kzm_smsc9118_config = {
.phy_interface = PHY_INTERFACE_MODE_MII,
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
}
#endif
-#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_IMX)
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
MX31_PIN_CONTRAST__CONTRAST,
MX31_PIN_D3_SPL__D3_SPL,
MX31_PIN_D3_CLS__D3_CLS,
- MX31_PIN_LCS0__GPI03_23,
+ MX31_PIN_LCS0__GPIO3_23,
/* CSI */
IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO),
MX31_PIN_CSI_D6__CSI_D6,
+++ /dev/null
-/*
- * linux/arch/arm/mach-mx1/mach-scb9328.c
- *
- * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de>
- * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/interrupt.h>
-#include <linux/dm9000.h>
-#include <linux/gpio.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-#include "devices-imx1.h"
-#include "hardware.h"
-#include "iomux-mx1.h"
-
-/*
- * This scb9328 has a 32MiB flash
- */
-static struct resource flash_resource = {
- .start = MX1_CS0_PHYS,
- .end = MX1_CS0_PHYS + (32 * 1024 * 1024) - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct physmap_flash_data scb_flash_data = {
- .width = 2,
-};
-
-static struct platform_device scb_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &scb_flash_data,
- },
- .resource = &flash_resource,
- .num_resources = 1,
-};
-
-/*
- * scb9328 has a DM9000 network controller
- * connected to CS5, with 16 bit data path
- * and interrupt connected to GPIO 3
- */
-
-/*
- * internal datapath is fixed 16 bit
- */
-static struct dm9000_plat_data dm9000_platdata = {
- .flags = DM9000_PLATF_16BITONLY,
-};
-
-/*
- * the DM9000 drivers wants two defined address spaces
- * to gain access to address latch registers and the data path.
- */
-static struct resource dm9000x_resources[] = {
- {
- .name = "address area",
- .start = MX1_CS5_PHYS,
- .end = MX1_CS5_PHYS + 1,
- .flags = IORESOURCE_MEM, /* address access */
- }, {
- .name = "data area",
- .start = MX1_CS5_PHYS + 4,
- .end = MX1_CS5_PHYS + 5,
- .flags = IORESOURCE_MEM, /* data access */
- }, {
- /* irq number is run-time assigned */
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct platform_device dm9000x_device = {
- .name = "dm9000",
- .id = 0,
- .num_resources = ARRAY_SIZE(dm9000x_resources),
- .resource = dm9000x_resources,
- .dev = {
- .platform_data = &dm9000_platdata,
- }
-};
-
-static const int mxc_uart1_pins[] = {
- PC9_PF_UART1_CTS,
- PC10_PF_UART1_RTS,
- PC11_PF_UART1_TXD,
- PC12_PF_UART1_RXD,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct platform_device *devices[] __initdata = {
- &scb_flash_device,
- &dm9000x_device,
-};
-
-/*
- * scb9328_init - Init the CPU card itself
- */
-static void __init scb9328_init(void)
-{
- imx1_soc_init();
-
- mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
- ARRAY_SIZE(mxc_uart1_pins), "UART1");
-
- imx1_add_imx_uart0(&uart_pdata);
-
- printk(KERN_INFO"Scb9328: Adding devices\n");
- dm9000x_resources[2].start = gpio_to_irq(IMX_GPIO_NR(3, 3));
- dm9000x_resources[2].end = gpio_to_irq(IMX_GPIO_NR(3, 3));
- platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-static void __init scb9328_timer_init(void)
-{
- mx1_clocks_init(32000);
-}
-
-MACHINE_START(SCB9328, "Synertronixx scb9328")
- /* Sascha Hauer */
- .atag_offset = 100,
- .map_io = mx1_map_io,
- .init_early = imx1_init_early,
- .init_irq = mx1_init_irq,
- .init_time = scb9328_timer_init,
- .init_machine = scb9328_init,
- .restart = mxc_restart,
-MACHINE_END
+++ /dev/null
-/*
- * author: Sascha Hauer
- * Created: april 20th, 2004
- * Copyright: Synertronixx GmbH
- *
- * Common code for i.MX1 machines
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/pinctrl/machine.h>
-
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices/devices-common.h"
-#include "hardware.h"
-#include "iomux-v1.h"
-
-static struct map_desc imx_io_desc[] __initdata = {
- imx_map_entry(MX1, IO, MT_DEVICE),
-};
-
-void __init mx1_map_io(void)
-{
- iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
-}
-
-void __init imx1_init_early(void)
-{
- mxc_set_cpu_type(MXC_CPU_MX1);
- imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
- MX1_NUM_GPIO_PORT);
-}
-
-void __init mx1_init_irq(void)
-{
- mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
-}
-
-void __init imx1_soc_init(void)
-{
- imx1_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
- mxc_device_init();
-
- mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256,
- MX1_GPIO_INT_PORTA, 0);
- mxc_register_gpio("imx1-gpio", 1, MX1_GPIO2_BASE_ADDR, SZ_256,
- MX1_GPIO_INT_PORTB, 0);
- mxc_register_gpio("imx1-gpio", 2, MX1_GPIO3_BASE_ADDR, SZ_256,
- MX1_GPIO_INT_PORTC, 0);
- mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256,
- MX1_GPIO_INT_PORTD, 0);
- imx_add_imx_dma("imx1-dma", MX1_DMA_BASE_ADDR,
- MX1_DMA_INT, MX1_DMA_ERR);
- pinctrl_provide_dummies();
-}
+++ /dev/null
-/*
- * Copyright (C) 1997,1998 Russell King
- * Copyright (C) 1999 ARM Limited
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_MX1_H__
-#define __MACH_MX1_H__
-
-/*
- * Memory map
- */
-#define MX1_IO_BASE_ADDR 0x00200000
-#define MX1_IO_SIZE SZ_1M
-
-#define MX1_CS0_PHYS 0x10000000
-#define MX1_CS0_SIZE 0x02000000
-
-#define MX1_CS1_PHYS 0x12000000
-#define MX1_CS1_SIZE 0x01000000
-
-#define MX1_CS2_PHYS 0x13000000
-#define MX1_CS2_SIZE 0x01000000
-
-#define MX1_CS3_PHYS 0x14000000
-#define MX1_CS3_SIZE 0x01000000
-
-#define MX1_CS4_PHYS 0x15000000
-#define MX1_CS4_SIZE 0x01000000
-
-#define MX1_CS5_PHYS 0x16000000
-#define MX1_CS5_SIZE 0x01000000
-
-/*
- * Register BASEs, based on OFFSETs
- */
-#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR)
-#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR)
-#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR)
-#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR)
-#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR)
-#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR)
-#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR)
-#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR)
-#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR)
-#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR)
-#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR)
-#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR)
-#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR)
-#define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR)
-#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR)
-#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR)
-#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR)
-#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR)
-#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR)
-#define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR)
-#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR)
-#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
-#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR)
-#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR)
-#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR)
-#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR)
-#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR)
-#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
-
-/* macro to get at IO space when running virtually */
-#define MX1_IO_P2V(x) IMX_IO_P2V(x)
-#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
-
-/* fixed interrput numbers */
-#include <asm/irq.h>
-#define MX1_INT_SOFTINT (NR_IRQS_LEGACY + 0)
-#define MX1_INT_CSI (NR_IRQS_LEGACY + 6)
-#define MX1_DSPA_MAC_INT (NR_IRQS_LEGACY + 7)
-#define MX1_DSPA_INT (NR_IRQS_LEGACY + 8)
-#define MX1_COMP_INT (NR_IRQS_LEGACY + 9)
-#define MX1_MSHC_XINT (NR_IRQS_LEGACY + 10)
-#define MX1_GPIO_INT_PORTA (NR_IRQS_LEGACY + 11)
-#define MX1_GPIO_INT_PORTB (NR_IRQS_LEGACY + 12)
-#define MX1_GPIO_INT_PORTC (NR_IRQS_LEGACY + 13)
-#define MX1_INT_LCDC (NR_IRQS_LEGACY + 14)
-#define MX1_SIM_INT (NR_IRQS_LEGACY + 15)
-#define MX1_SIM_DATA_INT (NR_IRQS_LEGACY + 16)
-#define MX1_RTC_INT (NR_IRQS_LEGACY + 17)
-#define MX1_RTC_SAMINT (NR_IRQS_LEGACY + 18)
-#define MX1_INT_UART2PFERR (NR_IRQS_LEGACY + 19)
-#define MX1_INT_UART2RTS (NR_IRQS_LEGACY + 20)
-#define MX1_INT_UART2DTR (NR_IRQS_LEGACY + 21)
-#define MX1_INT_UART2UARTC (NR_IRQS_LEGACY + 22)
-#define MX1_INT_UART2TX (NR_IRQS_LEGACY + 23)
-#define MX1_INT_UART2RX (NR_IRQS_LEGACY + 24)
-#define MX1_INT_UART1PFERR (NR_IRQS_LEGACY + 25)
-#define MX1_INT_UART1RTS (NR_IRQS_LEGACY + 26)
-#define MX1_INT_UART1DTR (NR_IRQS_LEGACY + 27)
-#define MX1_INT_UART1UARTC (NR_IRQS_LEGACY + 28)
-#define MX1_INT_UART1TX (NR_IRQS_LEGACY + 29)
-#define MX1_INT_UART1RX (NR_IRQS_LEGACY + 30)
-#define MX1_VOICE_DAC_INT (NR_IRQS_LEGACY + 31)
-#define MX1_VOICE_ADC_INT (NR_IRQS_LEGACY + 32)
-#define MX1_PEN_DATA_INT (NR_IRQS_LEGACY + 33)
-#define MX1_PWM_INT (NR_IRQS_LEGACY + 34)
-#define MX1_SDHC_INT (NR_IRQS_LEGACY + 35)
-#define MX1_INT_I2C (NR_IRQS_LEGACY + 39)
-#define MX1_INT_CSPI2 (NR_IRQS_LEGACY + 40)
-#define MX1_INT_CSPI1 (NR_IRQS_LEGACY + 41)
-#define MX1_SSI_TX_INT (NR_IRQS_LEGACY + 42)
-#define MX1_SSI_TX_ERR_INT (NR_IRQS_LEGACY + 43)
-#define MX1_SSI_RX_INT (NR_IRQS_LEGACY + 44)
-#define MX1_SSI_RX_ERR_INT (NR_IRQS_LEGACY + 45)
-#define MX1_TOUCH_INT (NR_IRQS_LEGACY + 46)
-#define MX1_INT_USBD0 (NR_IRQS_LEGACY + 47)
-#define MX1_INT_USBD1 (NR_IRQS_LEGACY + 48)
-#define MX1_INT_USBD2 (NR_IRQS_LEGACY + 49)
-#define MX1_INT_USBD3 (NR_IRQS_LEGACY + 50)
-#define MX1_INT_USBD4 (NR_IRQS_LEGACY + 51)
-#define MX1_INT_USBD5 (NR_IRQS_LEGACY + 52)
-#define MX1_INT_USBD6 (NR_IRQS_LEGACY + 53)
-#define MX1_BTSYS_INT (NR_IRQS_LEGACY + 55)
-#define MX1_BTTIM_INT (NR_IRQS_LEGACY + 56)
-#define MX1_BTWUI_INT (NR_IRQS_LEGACY + 57)
-#define MX1_TIM2_INT (NR_IRQS_LEGACY + 58)
-#define MX1_TIM1_INT (NR_IRQS_LEGACY + 59)
-#define MX1_DMA_ERR (NR_IRQS_LEGACY + 60)
-#define MX1_DMA_INT (NR_IRQS_LEGACY + 61)
-#define MX1_GPIO_INT_PORTD (NR_IRQS_LEGACY + 62)
-#define MX1_WDT_INT (NR_IRQS_LEGACY + 63)
-
-/* DMA */
-#define MX1_DMA_REQ_UART3_T 2
-#define MX1_DMA_REQ_UART3_R 3
-#define MX1_DMA_REQ_SSI2_T 4
-#define MX1_DMA_REQ_SSI2_R 5
-#define MX1_DMA_REQ_CSI_STAT 6
-#define MX1_DMA_REQ_CSI_R 7
-#define MX1_DMA_REQ_MSHC 8
-#define MX1_DMA_REQ_DSPA_DCT_DOUT 9
-#define MX1_DMA_REQ_DSPA_DCT_DIN 10
-#define MX1_DMA_REQ_DSPA_MAC 11
-#define MX1_DMA_REQ_EXT 12
-#define MX1_DMA_REQ_SDHC 13
-#define MX1_DMA_REQ_SPI1_R 14
-#define MX1_DMA_REQ_SPI1_T 15
-#define MX1_DMA_REQ_SSI_T 16
-#define MX1_DMA_REQ_SSI_R 17
-#define MX1_DMA_REQ_ASP_DAC 18
-#define MX1_DMA_REQ_ASP_ADC 19
-#define MX1_DMA_REQ_USP_EP(x) (20 + (x))
-#define MX1_DMA_REQ_SPI2_R 26
-#define MX1_DMA_REQ_SPI2_T 27
-#define MX1_DMA_REQ_UART2_T 28
-#define MX1_DMA_REQ_UART2_R 29
-#define MX1_DMA_REQ_UART1_T 30
-#define MX1_DMA_REQ_UART1_R 31
-
-/*
- * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS
- * to not break drivers/usb/gadget/imx_udc. Should go
- * away after this driver uses the new name.
- */
-#define USBD_INT0 MX1_INT_USBD0
-
-#endif /* ifndef __MACH_MX1_H__ */
config ARCH_INTEGRATOR_AP
bool "Support Integrator/AP and Integrator/PP2 platforms"
select INTEGRATOR_AP_TIMER
- select MIGHT_HAVE_PCI
select SERIAL_AMBA_PL010 if TTY
select SERIAL_AMBA_PL010_CONSOLE if TTY
select SOC_BUS
select COMMON_CLK_KEYSTONE
select ARCH_SUPPORTS_BIG_ENDIAN
select ZONE_DMA if ARM_LPAE
- select MIGHT_HAVE_PCI
- select PCI_DOMAINS if PCI
select PINCTRL
help
Support for boards based on the Texas Instruments Keystone family of
apx4devkit_phy_fixup);
}
-#define ENET0_MDC__GPIO_4_0 MXS_GPIO_NR(4, 0)
-#define ENET0_MDIO__GPIO_4_1 MXS_GPIO_NR(4, 1)
-#define ENET0_RX_EN__GPIO_4_2 MXS_GPIO_NR(4, 2)
-#define ENET0_RXD0__GPIO_4_3 MXS_GPIO_NR(4, 3)
-#define ENET0_RXD1__GPIO_4_4 MXS_GPIO_NR(4, 4)
-#define ENET0_TX_EN__GPIO_4_6 MXS_GPIO_NR(4, 6)
-#define ENET0_TXD0__GPIO_4_7 MXS_GPIO_NR(4, 7)
-#define ENET0_TXD1__GPIO_4_8 MXS_GPIO_NR(4, 8)
-#define ENET_CLK__GPIO_4_16 MXS_GPIO_NR(4, 16)
-
-#define TX28_FEC_PHY_POWER MXS_GPIO_NR(3, 29)
-#define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13)
-#define TX28_FEC_nINT MXS_GPIO_NR(4, 5)
-
-static const struct gpio const tx28_gpios[] __initconst = {
- { ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" },
- { ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" },
- { ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" },
- { ENET0_RXD0__GPIO_4_3, GPIOF_OUT_INIT_LOW, "GPIO_4_3" },
- { ENET0_RXD1__GPIO_4_4, GPIOF_OUT_INIT_LOW, "GPIO_4_4" },
- { ENET0_TX_EN__GPIO_4_6, GPIOF_OUT_INIT_LOW, "GPIO_4_6" },
- { ENET0_TXD0__GPIO_4_7, GPIOF_OUT_INIT_LOW, "GPIO_4_7" },
- { ENET0_TXD1__GPIO_4_8, GPIOF_OUT_INIT_LOW, "GPIO_4_8" },
- { ENET_CLK__GPIO_4_16, GPIOF_OUT_INIT_LOW, "GPIO_4_16" },
- { TX28_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" },
- { TX28_FEC_PHY_RESET, GPIOF_OUT_INIT_LOW, "fec-phy-reset" },
- { TX28_FEC_nINT, GPIOF_DIR_IN, "fec-int" },
-};
-
-static void __init tx28_post_init(void)
-{
- struct device_node *np;
- struct platform_device *pdev;
- struct pinctrl *pctl;
- int ret;
-
- enable_clk_enet_out();
-
- np = of_find_compatible_node(NULL, NULL, "fsl,imx28-fec");
- pdev = of_find_device_by_node(np);
- if (!pdev) {
- pr_err("%s: failed to find fec device\n", __func__);
- return;
- }
-
- pctl = pinctrl_get_select(&pdev->dev, "gpio_mode");
- if (IS_ERR(pctl)) {
- pr_err("%s: failed to get pinctrl state\n", __func__);
- return;
- }
-
- ret = gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
- if (ret) {
- pr_err("%s: failed to request gpios: %d\n", __func__, ret);
- return;
- }
-
- /* Power up fec phy */
- gpio_set_value(TX28_FEC_PHY_POWER, 1);
- msleep(26); /* 25ms according to data sheet */
-
- /* Mode strap pins */
- gpio_set_value(ENET0_RX_EN__GPIO_4_2, 1);
- gpio_set_value(ENET0_RXD0__GPIO_4_3, 1);
- gpio_set_value(ENET0_RXD1__GPIO_4_4, 1);
-
- udelay(100); /* minimum assertion time for nRST */
-
- /* Deasserting FEC PHY RESET */
- gpio_set_value(TX28_FEC_PHY_RESET, 1);
-
- pinctrl_put(pctl);
-}
-
static void __init crystalfontz_init(void)
{
update_fec_mac_prop(OUI_CRYSTALFONTZ);
of_platform_default_populate(NULL, NULL, parent);
mxs_restart_init();
-
- if (of_machine_is_compatible("karo,tx28"))
- tx28_post_init();
}
#define MXS_CLKCTRL_RESET_CHIP (1 << 1)
#include "board-h2.h"
#include "mmc.h"
-#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+#if IS_ENABLED(CONFIG_MMC_OMAP)
static int mmc_set_power(struct device *dev, int slot, int power_on,
int vdd)
#if IS_ENABLED(CONFIG_USB_OMAP)
.hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */
/* .hmc_mode = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */
-#elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+#elif IS_ENABLED(CONFIG_USB_OHCI_HCD)
/* needs OTG cable, or NONSTANDARD (B-to-MiniB) */
.hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */
#endif
#include "board-h3.h"
#include "mmc.h"
-#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+#if IS_ENABLED(CONFIG_MMC_OMAP)
static int mmc_set_power(struct device *dev, int slot, int power_on,
int vdd)
#if IS_ENABLED(CONFIG_USB_OMAP)
.hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */
-#elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+#elif IS_ENABLED(CONFIG_USB_OHCI_HCD)
/* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */
.hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */
#endif
};
/* MMC Card */
-#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+#if IS_ENABLED(CONFIG_MMC_OMAP)
static struct omap_mmc_platform_data htc_mmc1_data = {
.nr_slots = 1,
.switch_slot = NULL,
omap_register_i2c_bus(1, 100, NULL, 0);
-#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+#if IS_ENABLED(CONFIG_MMC_OMAP)
htc_mmc_data[0] = &htc_mmc1_data;
omap1_init_mmc(htc_mmc_data, 1);
#endif
#if IS_ENABLED(CONFIG_USB_OMAP)
.hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */
/* .hmc_mode = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */
-#elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+#elif IS_ENABLED(CONFIG_USB_OHCI_HCD)
/* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */
.hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */
#endif
};
#endif
-#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+#if IS_ENABLED(CONFIG_MMC_OMAP)
static int mmc_set_power(struct device *dev, int slot, int power_on,
int vdd)
.extcon = "tahvo-usb",
};
-#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+#if IS_ENABLED(CONFIG_MMC_OMAP)
#define NOKIA770_GPIO_MMC_POWER 41
#define NOKIA770_GPIO_MMC_SWITCH 23
}
#endif
-#if defined(CONFIG_I2C_CBUS_GPIO) || defined(CONFIG_I2C_CBUS_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_I2C_CBUS_GPIO)
static struct i2c_cbus_platform_data nokia770_cbus_data = {
.clk_gpio = OMAP_MPUIO(9),
.dat_gpio = OMAP_MPUIO(10),
#include "mmc.h"
-#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+#if IS_ENABLED(CONFIG_MMC_OMAP)
static int mmc_set_power(struct device *dev, int slot, int power_on,
int vdd)
#include "mmc.h"
#include "sram.h"
-#if defined(CONFIG_RTC_DRV_OMAP) || defined(CONFIG_RTC_DRV_OMAP_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_OMAP)
#define OMAP_RTC_BASE 0xfffb4800
/*-------------------------------------------------------------------------*/
-#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+#if IS_ENABLED(CONFIG_MMC_OMAP)
static inline void omap1_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
int controller_nr)
/*-------------------------------------------------------------------------*/
/* OMAP7xx SPI support */
-#if defined(CONFIG_SPI_OMAP_100K) || defined(CONFIG_SPI_OMAP_100K_MODULE)
+#if IS_ENABLED(CONFIG_SPI_OMAP_100K)
struct platform_device omap_spi1 = {
.name = "omap1_spi100k",
* mcbsp1..3 = 5..7
*/
-#if defined(CONFIG_SPI_OMAP_UWIRE) || defined(CONFIG_SPI_OMAP_UWIRE_MODULE)
+#if IS_ENABLED(CONFIG_SPI_OMAP_UWIRE)
#define OMAP_UWIRE_BASE 0xfffb3000
}
arch_initcall(omap1_init_devices);
-#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
+#if IS_ENABLED(CONFIG_OMAP_WATCHDOG)
static struct resource wdt_resources[] = {
{
#include <asm/mach/map.h>
-#if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
+#if IS_ENABLED(CONFIG_FB_OMAP)
static bool omapfb_lcd_configured;
static struct omapfb_platform_data omapfb_config;
void omap_otg_init(struct omap_usb_config *config);
-#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
+#if IS_ENABLED(CONFIG_USB)
void omap1_usb_init(struct omap_usb_config *pdata);
#else
static inline void omap1_usb_init(struct omap_usb_config *pdata)
#define OMAP1_MMC1_BASE 0xfffb7800
#define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */
-#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+#if IS_ENABLED(CONFIG_MMC_OMAP)
void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
int nr_controllers);
#else
}
#endif
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
if (config->otg || config->register_host) {
struct platform_device *ohci_device = config->ohci_device;
int status;
#endif
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
/* The dmamask must be set for OHCI to work */
static u64 ohci_dmamask = ~(u32)0;
}
#endif
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
if (config->register_host) {
int status;
depends on ARCH_OMAP2 && SOC_OMAP2420
default y if MACH_NOKIA_N8X0
-config MACH_OMAP_LDP
- bool "OMAP3 LDP board"
- depends on ARCH_OMAP3
- default y
- select OMAP_PACKAGE_CBB
-
config MACH_OMAP3517EVM
bool "OMAP3517/ AM3517 EVM board"
depends on ARCH_OMAP3
select MACH_NOKIA_N810
select MACH_NOKIA_N810_WIMAX
-config MACH_NOKIA_RX51
- bool "Nokia N900 (RX-51) phone"
- depends on ARCH_OMAP3
- default y
- select OMAP_PACKAGE_CBB
-
config OMAP3_SDRC_AC_TIMING
bool "Enable SDRC AC timing register changes"
depends on ARCH_OMAP3
# Specific board support
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o
-obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o
obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
-obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o sdram-nokia.o
-obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-peripherals.o
-obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-video.o
# Platform specific device init code
pr_err("Unable to register NOR device\n");
}
-#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
- defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
static struct omap_onenand_platform_data board_onenand_data = {
.dma_channel = -1, /* disable DMA in OMAP OneNAND driver */
};
gpmc_onenand_init(&board_onenand_data);
}
-#endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */
+#endif /* IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2) */
-#if defined(CONFIG_MTD_NAND_OMAP2) || \
- defined(CONFIG_MTD_NAND_OMAP2_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
/* Note that all values in this struct are in nanoseconds */
struct gpmc_timings nand_default_timings[1] = {
board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_SW;
gpmc_nand_init(&board_nand_data, gpmc_t);
}
-#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
+#endif /* IS_ENABLED(CONFIG_MTD_NAND_OMAP2) */
/**
* get_gpmc0_type - Reads the FPGA DIP_SWITCH_INPUT_REGISTER2 to get
int nr_parts;
};
-#if defined(CONFIG_MTD_NAND_OMAP2) || \
- defined(CONFIG_MTD_NAND_OMAP2_MODULE) || \
- defined(CONFIG_MTD_ONENAND_OMAP2) || \
- defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2) || IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
extern void board_flash_init(struct flash_partitions [],
char chip_sel[][GPMC_CS_NUM], int nand_type);
#else
}
#endif
-#if defined(CONFIG_MTD_NAND_OMAP2) || \
- defined(CONFIG_MTD_NAND_OMAP2_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
extern void board_nand_init(struct mtd_partition *nand_parts,
u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t);
extern struct gpmc_timings nand_default_timings[];
#define nand_default_timings NULL
#endif
-#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
- defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
extern void board_onenand_init(struct mtd_partition *nand_parts,
u8 nr_parts, u8 cs);
#else
+++ /dev/null
-/*
- * linux/arch/arm/mach-omap2/board-ldp.c
- *
- * Copyright (C) 2008 Texas Instruments Inc.
- * Nishant Kamat <nskamat@ti.com>
- *
- * Modified from mach-omap2/board-3430sdp.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/input.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/gpio_keys.h>
-#include <linux/workqueue.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/spi/spi.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-#include <linux/i2c/twl.h>
-#include <linux/io.h>
-#include <linux/smsc911x.h>
-#include <linux/mmc/host.h>
-#include <linux/usb/phy.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "gpmc.h"
-#include "gpmc-smsc911x.h"
-
-#include <linux/platform_data/omapdss.h>
-#include <video/omap-panel-data.h>
-
-#include "board-flash.h"
-#include "mux.h"
-#include "hsmmc.h"
-#include "control.h"
-#include "common-board-devices.h"
-#include "display.h"
-
-#define LDP_SMSC911X_CS 1
-#define LDP_SMSC911X_GPIO 152
-#define DEBUG_BASE 0x08000000
-#define LDP_ETHR_START DEBUG_BASE
-
-static uint32_t board_keymap[] = {
- KEY(0, 0, KEY_1),
- KEY(1, 0, KEY_2),
- KEY(2, 0, KEY_3),
- KEY(0, 1, KEY_4),
- KEY(1, 1, KEY_5),
- KEY(2, 1, KEY_6),
- KEY(3, 1, KEY_F5),
- KEY(0, 2, KEY_7),
- KEY(1, 2, KEY_8),
- KEY(2, 2, KEY_9),
- KEY(3, 2, KEY_F6),
- KEY(0, 3, KEY_F7),
- KEY(1, 3, KEY_0),
- KEY(2, 3, KEY_F8),
- PERSISTENT_KEY(4, 5),
- KEY(4, 4, KEY_VOLUMEUP),
- KEY(5, 5, KEY_VOLUMEDOWN),
- 0
-};
-
-static struct matrix_keymap_data board_map_data = {
- .keymap = board_keymap,
- .keymap_size = ARRAY_SIZE(board_keymap),
-};
-
-static struct twl4030_keypad_data ldp_kp_twl4030_data = {
- .keymap_data = &board_map_data,
- .rows = 6,
- .cols = 6,
- .rep = 1,
-};
-
-static struct gpio_keys_button ldp_gpio_keys_buttons[] = {
- [0] = {
- .code = KEY_ENTER,
- .gpio = 101,
- .desc = "enter sw",
- .active_low = 1,
- .debounce_interval = 30,
- },
- [1] = {
- .code = KEY_F1,
- .gpio = 102,
- .desc = "func 1",
- .active_low = 1,
- .debounce_interval = 30,
- },
- [2] = {
- .code = KEY_F2,
- .gpio = 103,
- .desc = "func 2",
- .active_low = 1,
- .debounce_interval = 30,
- },
- [3] = {
- .code = KEY_F3,
- .gpio = 104,
- .desc = "func 3",
- .active_low = 1,
- .debounce_interval = 30,
- },
- [4] = {
- .code = KEY_F4,
- .gpio = 105,
- .desc = "func 4",
- .active_low = 1,
- .debounce_interval = 30,
- },
- [5] = {
- .code = KEY_LEFT,
- .gpio = 106,
- .desc = "left sw",
- .active_low = 1,
- .debounce_interval = 30,
- },
- [6] = {
- .code = KEY_RIGHT,
- .gpio = 107,
- .desc = "right sw",
- .active_low = 1,
- .debounce_interval = 30,
- },
- [7] = {
- .code = KEY_UP,
- .gpio = 108,
- .desc = "up sw",
- .active_low = 1,
- .debounce_interval = 30,
- },
- [8] = {
- .code = KEY_DOWN,
- .gpio = 109,
- .desc = "down sw",
- .active_low = 1,
- .debounce_interval = 30,
- },
-};
-
-static struct gpio_keys_platform_data ldp_gpio_keys = {
- .buttons = ldp_gpio_keys_buttons,
- .nbuttons = ARRAY_SIZE(ldp_gpio_keys_buttons),
- .rep = 1,
-};
-
-static struct platform_device ldp_gpio_keys_device = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &ldp_gpio_keys,
- },
-};
-
-static struct omap_smsc911x_platform_data smsc911x_cfg = {
- .cs = LDP_SMSC911X_CS,
- .gpio_irq = LDP_SMSC911X_GPIO,
- .gpio_reset = -EINVAL,
- .flags = SMSC911X_USE_32BIT,
-};
-
-static inline void __init ldp_init_smsc911x(void)
-{
- gpmc_smsc911x_init(&smsc911x_cfg);
-}
-
-/* LCD */
-
-#define LCD_PANEL_RESET_GPIO 55
-#define LCD_PANEL_QVGA_GPIO 56
-
-static const struct display_timing ldp_lcd_videomode = {
- .pixelclock = { 0, 5400000, 0 },
-
- .hactive = { 0, 240, 0 },
- .hfront_porch = { 0, 3, 0 },
- .hback_porch = { 0, 39, 0 },
- .hsync_len = { 0, 3, 0 },
-
- .vactive = { 0, 320, 0 },
- .vfront_porch = { 0, 2, 0 },
- .vback_porch = { 0, 7, 0 },
- .vsync_len = { 0, 1, 0 },
-
- .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
- DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
-};
-
-static struct panel_dpi_platform_data ldp_lcd_pdata = {
- .name = "lcd",
- .source = "dpi.0",
-
- .data_lines = 18,
-
- .display_timing = &ldp_lcd_videomode,
-
- .enable_gpio = -1, /* filled in code */
- .backlight_gpio = -1, /* filled in code */
-};
-
-static struct platform_device ldp_lcd_device = {
- .name = "panel-dpi",
- .id = 0,
- .dev.platform_data = &ldp_lcd_pdata,
-};
-
-static struct omap_dss_board_info ldp_dss_data = {
- .default_display_name = "lcd",
-};
-
-static void __init ldp_display_init(void)
-{
- int r;
-
- static struct gpio gpios[] __initdata = {
- {LCD_PANEL_RESET_GPIO, GPIOF_OUT_INIT_HIGH, "LCD RESET"},
- {LCD_PANEL_QVGA_GPIO, GPIOF_OUT_INIT_HIGH, "LCD QVGA"},
- };
-
- r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
- if (r) {
- pr_err("Cannot request LCD GPIOs, error %d\n", r);
- return;
- }
-
- omap_display_init(&ldp_dss_data);
-}
-
-static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio)
-{
- int res;
-
- /* LCD enable GPIO */
- ldp_lcd_pdata.enable_gpio = gpio + 7;
-
- /* Backlight enable GPIO */
- ldp_lcd_pdata.backlight_gpio = gpio + 15;
-
- res = platform_device_register(&ldp_lcd_device);
- if (res)
- pr_err("Unable to register LCD: %d\n", res);
-
- return 0;
-}
-
-static struct twl4030_gpio_platform_data ldp_gpio_data = {
- .setup = ldp_twl_gpio_setup,
-};
-
-static struct regulator_consumer_supply ldp_vmmc1_supply[] = {
- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
-};
-
-/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
-static struct regulator_init_data ldp_vmmc1 = {
- .constraints = {
- .min_uV = 1850000,
- .max_uV = 3150000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
- | REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldp_vmmc1_supply),
- .consumer_supplies = ldp_vmmc1_supply,
-};
-
-/* ads7846 on SPI */
-static struct regulator_consumer_supply ldp_vaux1_supplies[] = {
- REGULATOR_SUPPLY("vcc", "spi1.0"),
-};
-
-/* VAUX1 */
-static struct regulator_init_data ldp_vaux1 = {
- .constraints = {
- .min_uV = 3000000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldp_vaux1_supplies),
- .consumer_supplies = ldp_vaux1_supplies,
-};
-
-static struct regulator_consumer_supply ldp_vpll2_supplies[] = {
- REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
- REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
- REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
-};
-
-static struct regulator_init_data ldp_vpll2 = {
- .constraints = {
- .name = "VDVI",
- .min_uV = 1800000,
- .max_uV = 1800000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldp_vpll2_supplies),
- .consumer_supplies = ldp_vpll2_supplies,
-};
-
-static struct twl4030_platform_data ldp_twldata = {
- /* platform_data for children goes here */
- .vmmc1 = &ldp_vmmc1,
- .vaux1 = &ldp_vaux1,
- .vpll2 = &ldp_vpll2,
- .gpio = &ldp_gpio_data,
- .keypad = &ldp_kp_twl4030_data,
-};
-
-static int __init omap_i2c_init(void)
-{
- omap3_pmic_get_config(&ldp_twldata,
- TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC, 0);
- omap3_pmic_init("twl4030", &ldp_twldata);
- omap_register_i2c_bus(2, 400, NULL, 0);
- omap_register_i2c_bus(3, 400, NULL, 0);
- return 0;
-}
-
-static struct omap2_hsmmc_info mmc[] __initdata = {
- {
- .mmc = 1,
- .caps = MMC_CAP_4_BIT_DATA,
- .gpio_cd = -EINVAL,
- .gpio_wp = -EINVAL,
- },
- {} /* Terminator */
-};
-
-static struct platform_device *ldp_devices[] __initdata = {
- &ldp_gpio_keys_device,
-};
-
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
- { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#endif
-
-static struct mtd_partition ldp_nand_partitions[] = {
- /* All the partition sizes are listed in terms of NAND block size */
- {
- .name = "X-Loader-NAND",
- .offset = 0,
- .size = 4 * (64 * 2048), /* 512KB, 0x80000 */
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- {
- .name = "U-Boot-NAND",
- .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
- .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
- {
- .name = "Boot Env-NAND",
- .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */
- .size = 2 * (64 * 2048), /* 256KB, 0x40000 */
- },
- {
- .name = "Kernel-NAND",
- .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/
- .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */
- },
- {
- .name = "File System - NAND",
- .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */
- .size = MTDPART_SIZ_FULL, /* 96MB, 0x6000000 */
- },
-
-};
-
-static struct regulator_consumer_supply dummy_supplies[] = {
- REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
- REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
-};
-
-static void __init omap_ldp_init(void)
-{
- regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
- omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
- ldp_init_smsc911x();
- omap_i2c_init();
- platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
- omap_ads7846_init(1, 54, 310, NULL);
- omap_serial_init();
- omap_sdrc_init(NULL, NULL);
- usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
- usb_musb_init(NULL);
- board_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions),
- 0, 0, nand_default_timings);
-
- omap_hsmmc_init(mmc);
- ldp_display_init();
-}
-
-MACHINE_START(OMAP_LDP, "OMAP LDP board")
- .atag_offset = 0x100,
- .reserve = omap_reserve,
- .map_io = omap3_map_io,
- .init_early = omap3430_init_early,
- .init_irq = omap3_init_irq,
- .init_machine = omap_ldp_init,
- .init_late = omap3430_init_late,
- .init_time = omap_init_time,
- .restart = omap3xxx_restart,
-MACHINE_END
pr_err("Unknown board\n");
}
-#if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
+#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
/*
* Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and
* 1.5 V voltage regulators of PM companion chip. Companion chip will then
},
};
-#if defined(CONFIG_MENELAUS) && \
- (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE))
+#if defined(CONFIG_MENELAUS) && IS_ENABLED(CONFIG_MMC_OMAP)
/*
* On both N800 and N810, only the first of the two MMC controllers is in use.
+++ /dev/null
-/*
- * linux/arch/arm/mach-omap2/board-rx51-peripherals.c
- *
- * Copyright (C) 2008-2009 Nokia
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/spi/spi.h>
-#include <linux/wl12xx.h>
-#include <linux/spi/tsc2005.h>
-#include <linux/i2c.h>
-#include <linux/i2c/twl.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/regulator/machine.h>
-#include <linux/gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio/machine.h>
-#include <linux/omap-gpmc.h>
-#include <linux/mmc/host.h>
-#include <linux/power/isp1704_charger.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <linux/platform_data/mtd-onenand-omap2.h>
-#include <linux/module.h>
-
-#include <plat/dmtimer.h>
-
-#include <asm/system_info.h>
-
-#include "common.h"
-#include <linux/omap-dma.h>
-
-#include "board-rx51.h"
-
-#include <sound/tlv320aic3x.h>
-#include <sound/tpa6130a2-plat.h>
-#include <linux/platform_data/media/si4713.h>
-#include <linux/platform_data/leds-lp55xx.h>
-
-#include <linux/platform_data/tsl2563.h>
-#include <linux/lis3lv02d.h>
-
-#include <video/omap-panel-data.h>
-
-#include <linux/platform_data/pwm_omap_dmtimer.h>
-#include <linux/platform_data/media/ir-rx51.h>
-
-#include "mux.h"
-#include "omap-pm.h"
-#include "hsmmc.h"
-#include "common-board-devices.h"
-#include "soc.h"
-#include "omap-secure.h"
-
-#define SYSTEM_REV_B_USES_VAUX3 0x1699
-#define SYSTEM_REV_S_USES_VAUX3 0x8
-
-#define RX51_WL1251_POWER_GPIO 87
-#define RX51_WL1251_IRQ_GPIO 42
-#define RX51_FMTX_RESET_GPIO 163
-#define RX51_FMTX_IRQ 53
-#define RX51_LP5523_CHIP_EN_GPIO 41
-
-#define RX51_USB_TRANSCEIVER_RST_GPIO 67
-
-#define RX51_TSC2005_RESET_GPIO 104
-#define RX51_TSC2005_IRQ_GPIO 100
-
-#define LIS302_IRQ1_GPIO 181
-#define LIS302_IRQ2_GPIO 180 /* Not yet in use */
-
-/* List all SPI devices here. Note that the list/probe order seems to matter! */
-enum {
- RX51_SPI_WL1251,
- RX51_SPI_TSC2005, /* Touch Controller */
- RX51_SPI_MIPID, /* LCD panel */
-};
-
-static struct wl1251_platform_data wl1251_pdata;
-static struct tsc2005_platform_data tsc2005_pdata;
-
-#if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
-static int lis302_setup(void)
-{
- int err;
- int irq1 = LIS302_IRQ1_GPIO;
- int irq2 = LIS302_IRQ2_GPIO;
-
- /* gpio for interrupt pin 1 */
- err = gpio_request(irq1, "lis3lv02dl_irq1");
- if (err) {
- printk(KERN_ERR "lis3lv02dl: gpio request failed\n");
- goto out;
- }
-
- /* gpio for interrupt pin 2 */
- err = gpio_request(irq2, "lis3lv02dl_irq2");
- if (err) {
- gpio_free(irq1);
- printk(KERN_ERR "lis3lv02dl: gpio request failed\n");
- goto out;
- }
-
- gpio_direction_input(irq1);
- gpio_direction_input(irq2);
-
-out:
- return err;
-}
-
-static int lis302_release(void)
-{
- gpio_free(LIS302_IRQ1_GPIO);
- gpio_free(LIS302_IRQ2_GPIO);
-
- return 0;
-}
-
-static struct lis3lv02d_platform_data rx51_lis3lv02d_data = {
- .click_flags = LIS3_CLICK_SINGLE_X | LIS3_CLICK_SINGLE_Y |
- LIS3_CLICK_SINGLE_Z,
- /* Limits are 0.5g * value */
- .click_thresh_x = 8,
- .click_thresh_y = 8,
- .click_thresh_z = 10,
- /* Click must be longer than time limit */
- .click_time_limit = 9,
- /* Kind of debounce filter */
- .click_latency = 50,
-
- /* Limits for all axis. millig-value / 18 to get HW values */
- .wakeup_flags = LIS3_WAKEUP_X_HI | LIS3_WAKEUP_Y_HI,
- .wakeup_thresh = 800 / 18,
- .wakeup_flags2 = LIS3_WAKEUP_Z_HI ,
- .wakeup_thresh2 = 900 / 18,
-
- .hipass_ctrl = LIS3_HIPASS1_DISABLE | LIS3_HIPASS2_DISABLE,
-
- /* Interrupt line 2 for click detection, line 1 for thresholds */
- .irq_cfg = LIS3_IRQ2_CLICK | LIS3_IRQ1_FF_WU_12,
-
- .axis_x = LIS3_DEV_X,
- .axis_y = LIS3_INV_DEV_Y,
- .axis_z = LIS3_INV_DEV_Z,
- .setup_resources = lis302_setup,
- .release_resources = lis302_release,
- .st_min_limits = {-32, 3, 3},
- .st_max_limits = {-3, 32, 32},
-};
-#endif
-
-#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
-static struct tsl2563_platform_data rx51_tsl2563_platform_data = {
- .cover_comp_gain = 16,
-};
-#endif
-
-#if defined(CONFIG_LEDS_LP5523) || defined(CONFIG_LEDS_LP5523_MODULE)
-static struct lp55xx_led_config rx51_lp5523_led_config[] = {
- {
- .name = "lp5523:kb1",
- .chan_nr = 0,
- .led_current = 50,
- .max_current = 100,
- }, {
- .name = "lp5523:kb2",
- .chan_nr = 1,
- .led_current = 50,
- .max_current = 100,
- }, {
- .name = "lp5523:kb3",
- .chan_nr = 2,
- .led_current = 50,
- .max_current = 100,
- }, {
- .name = "lp5523:kb4",
- .chan_nr = 3,
- .led_current = 50,
- .max_current = 100,
- }, {
- .name = "lp5523:b",
- .chan_nr = 4,
- .led_current = 50,
- .max_current = 100,
- }, {
- .name = "lp5523:g",
- .chan_nr = 5,
- .led_current = 50,
- .max_current = 100,
- }, {
- .name = "lp5523:r",
- .chan_nr = 6,
- .led_current = 50,
- .max_current = 100,
- }, {
- .name = "lp5523:kb5",
- .chan_nr = 7,
- .led_current = 50,
- .max_current = 100,
- }, {
- .name = "lp5523:kb6",
- .chan_nr = 8,
- .led_current = 50,
- .max_current = 100,
- }
-};
-
-static struct lp55xx_platform_data rx51_lp5523_platform_data = {
- .led_config = rx51_lp5523_led_config,
- .num_channels = ARRAY_SIZE(rx51_lp5523_led_config),
- .clock_mode = LP55XX_CLOCK_AUTO,
- .enable_gpio = RX51_LP5523_CHIP_EN_GPIO,
-};
-#endif
-
-#define RX51_LCD_RESET_GPIO 90
-
-static struct panel_acx565akm_platform_data acx_pdata = {
- .name = "lcd",
- .source = "sdi.0",
- .reset_gpio = RX51_LCD_RESET_GPIO,
- .datapairs = 2,
-};
-
-static struct omap2_mcspi_device_config wl1251_mcspi_config = {
- .turbo_mode = 0,
-};
-
-static struct omap2_mcspi_device_config mipid_mcspi_config = {
- .turbo_mode = 0,
-};
-
-static struct omap2_mcspi_device_config tsc2005_mcspi_config = {
- .turbo_mode = 0,
-};
-
-static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
- [RX51_SPI_WL1251] = {
- .modalias = "wl1251",
- .bus_num = 4,
- .chip_select = 0,
- .max_speed_hz = 48000000,
- .mode = SPI_MODE_3,
- .controller_data = &wl1251_mcspi_config,
- .platform_data = &wl1251_pdata,
- },
- [RX51_SPI_MIPID] = {
- .modalias = "acx565akm",
- .bus_num = 1,
- .chip_select = 2,
- .max_speed_hz = 6000000,
- .controller_data = &mipid_mcspi_config,
- .platform_data = &acx_pdata,
- },
- [RX51_SPI_TSC2005] = {
- .modalias = "tsc2005",
- .bus_num = 1,
- .chip_select = 0,
- .max_speed_hz = 6000000,
- .controller_data = &tsc2005_mcspi_config,
- .platform_data = &tsc2005_pdata,
- },
-};
-
-static struct platform_device rx51_battery_device = {
- .name = "rx51-battery",
- .id = -1,
-};
-
-static void rx51_charger_set_power(bool on)
-{
- gpio_set_value(RX51_USB_TRANSCEIVER_RST_GPIO, on);
-}
-
-static struct isp1704_charger_data rx51_charger_data = {
- .set_power = rx51_charger_set_power,
-};
-
-static struct platform_device rx51_charger_device = {
- .name = "isp1704_charger",
- .dev = {
- .platform_data = &rx51_charger_data,
- },
-};
-
-static void __init rx51_charger_init(void)
-{
- WARN_ON(gpio_request_one(RX51_USB_TRANSCEIVER_RST_GPIO,
- GPIOF_OUT_INIT_HIGH, "isp1704_reset"));
-
- platform_device_register(&rx51_battery_device);
- platform_device_register(&rx51_charger_device);
-}
-
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-
-#define RX51_GPIO_CAMERA_LENS_COVER 110
-#define RX51_GPIO_CAMERA_FOCUS 68
-#define RX51_GPIO_CAMERA_CAPTURE 69
-#define RX51_GPIO_KEYPAD_SLIDE 71
-#define RX51_GPIO_LOCK_BUTTON 113
-#define RX51_GPIO_PROXIMITY 89
-
-#define RX51_GPIO_DEBOUNCE_TIMEOUT 10
-
-static struct gpio_keys_button rx51_gpio_keys[] = {
- {
- .desc = "Camera Lens Cover",
- .type = EV_SW,
- .code = SW_CAMERA_LENS_COVER,
- .gpio = RX51_GPIO_CAMERA_LENS_COVER,
- .active_low = 1,
- .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
- }, {
- .desc = "Camera Focus",
- .type = EV_KEY,
- .code = KEY_CAMERA_FOCUS,
- .gpio = RX51_GPIO_CAMERA_FOCUS,
- .active_low = 1,
- .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
- }, {
- .desc = "Camera Capture",
- .type = EV_KEY,
- .code = KEY_CAMERA,
- .gpio = RX51_GPIO_CAMERA_CAPTURE,
- .active_low = 1,
- .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
- }, {
- .desc = "Lock Button",
- .type = EV_KEY,
- .code = KEY_SCREENLOCK,
- .gpio = RX51_GPIO_LOCK_BUTTON,
- .active_low = 1,
- .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
- }, {
- .desc = "Keypad Slide",
- .type = EV_SW,
- .code = SW_KEYPAD_SLIDE,
- .gpio = RX51_GPIO_KEYPAD_SLIDE,
- .active_low = 1,
- .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
- }, {
- .desc = "Proximity Sensor",
- .type = EV_SW,
- .code = SW_FRONT_PROXIMITY,
- .gpio = RX51_GPIO_PROXIMITY,
- .active_low = 0,
- .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
- }
-};
-
-static struct gpio_keys_platform_data rx51_gpio_keys_data = {
- .buttons = rx51_gpio_keys,
- .nbuttons = ARRAY_SIZE(rx51_gpio_keys),
-};
-
-static struct platform_device rx51_gpio_keys_device = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &rx51_gpio_keys_data,
- },
-};
-
-static void __init rx51_add_gpio_keys(void)
-{
- platform_device_register(&rx51_gpio_keys_device);
-}
-#else
-static void __init rx51_add_gpio_keys(void)
-{
-}
-#endif /* CONFIG_KEYBOARD_GPIO || CONFIG_KEYBOARD_GPIO_MODULE */
-
-static uint32_t board_keymap[] = {
- /*
- * Note that KEY(x, 8, KEY_XXX) entries represent "entrire row
- * connected to the ground" matrix state.
- */
- KEY(0, 0, KEY_Q),
- KEY(0, 1, KEY_O),
- KEY(0, 2, KEY_P),
- KEY(0, 3, KEY_COMMA),
- KEY(0, 4, KEY_BACKSPACE),
- KEY(0, 6, KEY_A),
- KEY(0, 7, KEY_S),
-
- KEY(1, 0, KEY_W),
- KEY(1, 1, KEY_D),
- KEY(1, 2, KEY_F),
- KEY(1, 3, KEY_G),
- KEY(1, 4, KEY_H),
- KEY(1, 5, KEY_J),
- KEY(1, 6, KEY_K),
- KEY(1, 7, KEY_L),
-
- KEY(2, 0, KEY_E),
- KEY(2, 1, KEY_DOT),
- KEY(2, 2, KEY_UP),
- KEY(2, 3, KEY_ENTER),
- KEY(2, 5, KEY_Z),
- KEY(2, 6, KEY_X),
- KEY(2, 7, KEY_C),
- KEY(2, 8, KEY_F9),
-
- KEY(3, 0, KEY_R),
- KEY(3, 1, KEY_V),
- KEY(3, 2, KEY_B),
- KEY(3, 3, KEY_N),
- KEY(3, 4, KEY_M),
- KEY(3, 5, KEY_SPACE),
- KEY(3, 6, KEY_SPACE),
- KEY(3, 7, KEY_LEFT),
-
- KEY(4, 0, KEY_T),
- KEY(4, 1, KEY_DOWN),
- KEY(4, 2, KEY_RIGHT),
- KEY(4, 4, KEY_LEFTCTRL),
- KEY(4, 5, KEY_RIGHTALT),
- KEY(4, 6, KEY_LEFTSHIFT),
- KEY(4, 8, KEY_F10),
-
- KEY(5, 0, KEY_Y),
- KEY(5, 8, KEY_F11),
-
- KEY(6, 0, KEY_U),
-
- KEY(7, 0, KEY_I),
- KEY(7, 1, KEY_F7),
- KEY(7, 2, KEY_F8),
-};
-
-static struct matrix_keymap_data board_map_data = {
- .keymap = board_keymap,
- .keymap_size = ARRAY_SIZE(board_keymap),
-};
-
-static struct twl4030_keypad_data rx51_kp_data = {
- .keymap_data = &board_map_data,
- .rows = 8,
- .cols = 8,
- .rep = 1,
-};
-
-/* Enable input logic and pull all lines up when eMMC is on. */
-static struct omap_board_mux rx51_mmc2_on_mux[] = {
- OMAP3_MUX(SDMMC2_CMD, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
- OMAP3_MUX(SDMMC2_DAT0, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
- OMAP3_MUX(SDMMC2_DAT1, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
- OMAP3_MUX(SDMMC2_DAT2, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
- OMAP3_MUX(SDMMC2_DAT3, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
- OMAP3_MUX(SDMMC2_DAT4, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
- OMAP3_MUX(SDMMC2_DAT5, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
- OMAP3_MUX(SDMMC2_DAT6, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
- OMAP3_MUX(SDMMC2_DAT7, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
- { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-
-/* Disable input logic and pull all lines down when eMMC is off. */
-static struct omap_board_mux rx51_mmc2_off_mux[] = {
- OMAP3_MUX(SDMMC2_CMD, OMAP_PULL_ENA | OMAP_MUX_MODE0),
- OMAP3_MUX(SDMMC2_DAT0, OMAP_PULL_ENA | OMAP_MUX_MODE0),
- OMAP3_MUX(SDMMC2_DAT1, OMAP_PULL_ENA | OMAP_MUX_MODE0),
- OMAP3_MUX(SDMMC2_DAT2, OMAP_PULL_ENA | OMAP_MUX_MODE0),
- OMAP3_MUX(SDMMC2_DAT3, OMAP_PULL_ENA | OMAP_MUX_MODE0),
- OMAP3_MUX(SDMMC2_DAT4, OMAP_PULL_ENA | OMAP_MUX_MODE0),
- OMAP3_MUX(SDMMC2_DAT5, OMAP_PULL_ENA | OMAP_MUX_MODE0),
- OMAP3_MUX(SDMMC2_DAT6, OMAP_PULL_ENA | OMAP_MUX_MODE0),
- OMAP3_MUX(SDMMC2_DAT7, OMAP_PULL_ENA | OMAP_MUX_MODE0),
- { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-
-static struct omap_mux_partition *partition;
-
-/*
- * Current flows to eMMC when eMMC is off and the data lines are pulled up,
- * so pull them down. N.B. we pull 8 lines because we are using 8 lines.
- */
-static void rx51_mmc2_remux(struct device *dev, int power_on)
-{
- if (power_on)
- omap_mux_write_array(partition, rx51_mmc2_on_mux);
- else
- omap_mux_write_array(partition, rx51_mmc2_off_mux);
-}
-
-static struct omap2_hsmmc_info mmc[] __initdata = {
- {
- .name = "external",
- .mmc = 1,
- .caps = MMC_CAP_4_BIT_DATA,
- .cover_only = true,
- .gpio_cd = 160,
- .gpio_wp = -EINVAL,
- },
- {
- .name = "internal",
- .mmc = 2,
- .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
- /* See also rx51_mmc2_remux */
- .gpio_cd = -EINVAL,
- .gpio_wp = -EINVAL,
- .nonremovable = true,
- .remux = rx51_mmc2_remux,
- },
- {} /* Terminator */
-};
-
-static struct regulator_consumer_supply rx51_vmmc1_supply[] = {
- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
-};
-
-static struct regulator_consumer_supply rx51_vaux2_supply[] = {
- REGULATOR_SUPPLY("vdds_csib", "omap3isp"),
-};
-
-static struct regulator_consumer_supply rx51_vaux3_supply[] = {
- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
-};
-
-static struct regulator_consumer_supply rx51_vsim_supply[] = {
- REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"),
-};
-
-static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
- /* tlv320aic3x analog supplies */
- REGULATOR_SUPPLY("AVDD", "2-0018"),
- REGULATOR_SUPPLY("DRVDD", "2-0018"),
- REGULATOR_SUPPLY("AVDD", "2-0019"),
- REGULATOR_SUPPLY("DRVDD", "2-0019"),
- /* tpa6130a2 */
- REGULATOR_SUPPLY("Vdd", "2-0060"),
- /* Keep vmmc as last item. It is not iterated for newer boards */
- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
-};
-
-static struct regulator_consumer_supply rx51_vio_supplies[] = {
- /* tlv320aic3x digital supplies */
- REGULATOR_SUPPLY("IOVDD", "2-0018"),
- REGULATOR_SUPPLY("DVDD", "2-0018"),
- REGULATOR_SUPPLY("IOVDD", "2-0019"),
- REGULATOR_SUPPLY("DVDD", "2-0019"),
- /* Si4713 IO supply */
- REGULATOR_SUPPLY("vio", "2-0063"),
- /* lis3lv02d */
- REGULATOR_SUPPLY("Vdd_IO", "3-001d"),
-};
-
-static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
- REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
- REGULATOR_SUPPLY("vdds_sdi", "omapdss_sdi.0"),
- /* Si4713 supply */
- REGULATOR_SUPPLY("vdd", "2-0063"),
- /* lis3lv02d */
- REGULATOR_SUPPLY("Vdd", "3-001d"),
-};
-
-static struct regulator_init_data rx51_vaux1 = {
- .constraints = {
- .name = "V28",
- .min_uV = 2800000,
- .max_uV = 2800000,
- .always_on = true, /* due battery cover sensor */
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(rx51_vaux1_consumers),
- .consumer_supplies = rx51_vaux1_consumers,
-};
-
-static struct regulator_init_data rx51_vaux2 = {
- .constraints = {
- .name = "VCSI",
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(rx51_vaux2_supply),
- .consumer_supplies = rx51_vaux2_supply,
-};
-
-/* VAUX3 - adds more power to VIO_18 rail */
-static struct regulator_init_data rx51_vaux3_cam = {
- .constraints = {
- .name = "VCAM_DIG_18",
- .min_uV = 1800000,
- .max_uV = 1800000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct regulator_init_data rx51_vaux3_mmc = {
- .constraints = {
- .name = "VMMC2_30",
- .min_uV = 2800000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
- | REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(rx51_vaux3_supply),
- .consumer_supplies = rx51_vaux3_supply,
-};
-
-static struct regulator_init_data rx51_vaux4 = {
- .constraints = {
- .name = "VCAM_ANA_28",
- .min_uV = 2800000,
- .max_uV = 2800000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct regulator_init_data rx51_vmmc1 = {
- .constraints = {
- .min_uV = 1850000,
- .max_uV = 3150000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
- | REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(rx51_vmmc1_supply),
- .consumer_supplies = rx51_vmmc1_supply,
-};
-
-static struct regulator_init_data rx51_vmmc2 = {
- .constraints = {
- .name = "V28_A",
- .min_uV = 2800000,
- .max_uV = 3000000,
- .always_on = true, /* due VIO leak to AIC34 VDDs */
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
- | REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(rx51_vmmc2_supplies),
- .consumer_supplies = rx51_vmmc2_supplies,
-};
-
-static struct regulator_init_data rx51_vpll1 = {
- .constraints = {
- .name = "VPLL",
- .min_uV = 1800000,
- .max_uV = 1800000,
- .apply_uV = true,
- .always_on = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE,
- },
-};
-
-static struct regulator_init_data rx51_vpll2 = {
- .constraints = {
- .name = "VSDI_CSI",
- .min_uV = 1800000,
- .max_uV = 1800000,
- .apply_uV = true,
- .always_on = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE,
- },
-};
-
-static struct regulator_init_data rx51_vsim = {
- .constraints = {
- .name = "VMMC2_IO_18",
- .min_uV = 1800000,
- .max_uV = 1800000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(rx51_vsim_supply),
- .consumer_supplies = rx51_vsim_supply,
-};
-
-static struct regulator_init_data rx51_vio = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
- | REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(rx51_vio_supplies),
- .consumer_supplies = rx51_vio_supplies,
-};
-
-static struct regulator_init_data rx51_vintana1 = {
- .constraints = {
- .name = "VINTANA1",
- .min_uV = 1500000,
- .max_uV = 1500000,
- .always_on = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE,
- },
-};
-
-static struct regulator_init_data rx51_vintana2 = {
- .constraints = {
- .name = "VINTANA2",
- .min_uV = 2750000,
- .max_uV = 2750000,
- .apply_uV = true,
- .always_on = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE,
- },
-};
-
-static struct regulator_init_data rx51_vintdig = {
- .constraints = {
- .name = "VINTDIG",
- .min_uV = 1500000,
- .max_uV = 1500000,
- .always_on = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE,
- },
-};
-
-static struct gpiod_lookup_table rx51_fmtx_gpios_table = {
- .dev_id = "2-0063",
- .table = {
- GPIO_LOOKUP("gpio.6", 3, "reset", GPIO_ACTIVE_HIGH), /* 163 */
- { },
- },
-};
-
-static __init void rx51_gpio_init(void)
-{
- gpiod_add_lookup_table(&rx51_fmtx_gpios_table);
-}
-
-static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n)
-{
- /* FIXME this gpio setup is just a placeholder for now */
- gpio_request_one(gpio + 6, GPIOF_OUT_INIT_LOW, "backlight_pwm");
- gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "speaker_en");
-
- return 0;
-}
-
-static struct twl4030_gpio_platform_data rx51_gpio_data = {
- .pulldowns = BIT(0) | BIT(1) | BIT(2) | BIT(3)
- | BIT(4) | BIT(5)
- | BIT(8) | BIT(9) | BIT(10) | BIT(11)
- | BIT(12) | BIT(13) | BIT(14) | BIT(15)
- | BIT(16) | BIT(17) ,
- .setup = rx51_twlgpio_setup,
-};
-
-static struct twl4030_ins sleep_on_seq[] __initdata = {
-/*
- * Turn off everything
- */
- {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_SLEEP), 2},
-};
-
-static struct twl4030_script sleep_on_script __initdata = {
- .script = sleep_on_seq,
- .size = ARRAY_SIZE(sleep_on_seq),
- .flags = TWL4030_SLEEP_SCRIPT,
-};
-
-static struct twl4030_ins wakeup_seq[] __initdata = {
-/*
- * Reenable everything
- */
- {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_ACTIVE), 2},
-};
-
-static struct twl4030_script wakeup_script __initdata = {
- .script = wakeup_seq,
- .size = ARRAY_SIZE(wakeup_seq),
- .flags = TWL4030_WAKEUP12_SCRIPT,
-};
-
-static struct twl4030_ins wakeup_p3_seq[] __initdata = {
-/*
- * Reenable everything
- */
- {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_ACTIVE), 2},
-};
-
-static struct twl4030_script wakeup_p3_script __initdata = {
- .script = wakeup_p3_seq,
- .size = ARRAY_SIZE(wakeup_p3_seq),
- .flags = TWL4030_WAKEUP3_SCRIPT,
-};
-
-static struct twl4030_ins wrst_seq[] __initdata = {
-/*
- * Reset twl4030.
- * Reset VDD1 regulator.
- * Reset VDD2 regulator.
- * Reset VPLL1 regulator.
- * Enable sysclk output.
- * Reenable twl4030.
- */
- {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_OFF), 2},
- {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 0, 1, RES_STATE_ACTIVE),
- 0x13},
- {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP, 0, 3, RES_STATE_OFF), 0x13},
- {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD1, RES_STATE_WRST), 0x13},
- {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD2, RES_STATE_WRST), 0x13},
- {MSG_SINGULAR(DEV_GRP_NULL, RES_VPLL1, RES_STATE_WRST), 0x35},
- {MSG_SINGULAR(DEV_GRP_P3, RES_HFCLKOUT, RES_STATE_ACTIVE), 2},
- {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_ACTIVE), 2},
-};
-
-static struct twl4030_script wrst_script __initdata = {
- .script = wrst_seq,
- .size = ARRAY_SIZE(wrst_seq),
- .flags = TWL4030_WRST_SCRIPT,
-};
-
-static struct twl4030_script *twl4030_scripts[] __initdata = {
- /* wakeup12 script should be loaded before sleep script, otherwise a
- board might hit retention before loading of wakeup script is
- completed. This can cause boot failures depending on timing issues.
- */
- &wakeup_script,
- &sleep_on_script,
- &wakeup_p3_script,
- &wrst_script,
-};
-
-static struct twl4030_resconfig twl4030_rconfig[] __initdata = {
- { .resource = RES_VDD1, .devgroup = -1,
- .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF,
- .remap_sleep = RES_STATE_OFF
- },
- { .resource = RES_VDD2, .devgroup = -1,
- .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF,
- .remap_sleep = RES_STATE_OFF
- },
- { .resource = RES_VPLL1, .devgroup = -1,
- .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF,
- .remap_sleep = RES_STATE_OFF
- },
- { .resource = RES_VPLL2, .devgroup = -1,
- .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VAUX1, .devgroup = -1,
- .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VAUX2, .devgroup = -1,
- .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VAUX3, .devgroup = -1,
- .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VAUX4, .devgroup = -1,
- .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VMMC1, .devgroup = -1,
- .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VMMC2, .devgroup = -1,
- .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VDAC, .devgroup = -1,
- .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VSIM, .devgroup = -1,
- .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VINTANA1, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
- .type = -1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VINTANA2, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
- .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VINTDIG, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
- .type = -1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_VIO, .devgroup = DEV_GRP_P3,
- .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_CLKEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
- .type = 1, .type2 = -1 , .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_REGEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
- .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_NRES_PWRON, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
- .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_SYSEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
- .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_HFCLKOUT, .devgroup = DEV_GRP_P3,
- .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_32KCLKOUT, .devgroup = -1,
- .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_RESET, .devgroup = -1,
- .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { .resource = RES_MAIN_REF, .devgroup = -1,
- .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
- },
- { 0, 0},
-};
-
-static struct twl4030_power_data rx51_t2scripts_data __initdata = {
- .scripts = twl4030_scripts,
- .num = ARRAY_SIZE(twl4030_scripts),
- .resource_config = twl4030_rconfig,
-};
-
-static struct twl4030_vibra_data rx51_vibra_data __initdata = {
- .coexist = 0,
-};
-
-static struct twl4030_audio_data rx51_audio_data __initdata = {
- .audio_mclk = 26000000,
- .vibra = &rx51_vibra_data,
-};
-
-static struct twl4030_platform_data rx51_twldata __initdata = {
- /* platform_data for children goes here */
- .gpio = &rx51_gpio_data,
- .keypad = &rx51_kp_data,
- .power = &rx51_t2scripts_data,
- .audio = &rx51_audio_data,
-
- .vaux1 = &rx51_vaux1,
- .vaux2 = &rx51_vaux2,
- .vaux4 = &rx51_vaux4,
- .vmmc1 = &rx51_vmmc1,
- .vpll1 = &rx51_vpll1,
- .vpll2 = &rx51_vpll2,
- .vsim = &rx51_vsim,
- .vintana1 = &rx51_vintana1,
- .vintana2 = &rx51_vintana2,
- .vintdig = &rx51_vintdig,
- .vio = &rx51_vio,
-};
-
-static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata_or_module = {
- .power_gpio = 98,
-};
-
-/* Audio setup data */
-static struct aic3x_setup_data rx51_aic34_setup = {
- .gpio_func[0] = AIC3X_GPIO1_FUNC_DISABLED,
- .gpio_func[1] = AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT,
-};
-
-static struct aic3x_pdata rx51_aic3x_data = {
- .setup = &rx51_aic34_setup,
- .gpio_reset = 60,
-};
-
-static struct aic3x_pdata rx51_aic3x_data2 = {
- .gpio_reset = 60,
-};
-
-#if IS_ENABLED(CONFIG_I2C_SI4713) && IS_ENABLED(CONFIG_PLATFORM_SI4713)
-static struct si4713_platform_data rx51_si4713_platform_data = {
- .is_platform_device = true
-};
-#endif
-
-static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = {
-#if IS_ENABLED(CONFIG_I2C_SI4713) && IS_ENABLED(CONFIG_PLATFORM_SI4713)
- {
- I2C_BOARD_INFO("si4713", 0x63),
- .platform_data = &rx51_si4713_platform_data,
- },
-#endif
- {
- I2C_BOARD_INFO("tlv320aic3x", 0x18),
- .platform_data = &rx51_aic3x_data,
- },
- {
- I2C_BOARD_INFO("tlv320aic3x", 0x19),
- .platform_data = &rx51_aic3x_data2,
- },
-#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
- {
- I2C_BOARD_INFO("tsl2563", 0x29),
- .platform_data = &rx51_tsl2563_platform_data,
- },
-#endif
-#if defined(CONFIG_LEDS_LP5523) || defined(CONFIG_LEDS_LP5523_MODULE)
- {
- I2C_BOARD_INFO("lp5523", 0x32),
- .platform_data = &rx51_lp5523_platform_data,
- },
-#endif
- {
- I2C_BOARD_INFO("bq27200", 0x55),
- },
- {
- I2C_BOARD_INFO("tpa6130a2", 0x60),
- .platform_data = &rx51_tpa6130a2_data,
- }
-};
-
-static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_3[] = {
-#if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
- {
- I2C_BOARD_INFO("lis3lv02d", 0x1d),
- .platform_data = &rx51_lis3lv02d_data,
- },
-#endif
-};
-
-static int __init rx51_i2c_init(void)
-{
-#if IS_ENABLED(CONFIG_I2C_SI4713) && IS_ENABLED(CONFIG_PLATFORM_SI4713)
- int err;
-#endif
-
- if ((system_rev >= SYSTEM_REV_S_USES_VAUX3 && system_rev < 0x100) ||
- system_rev >= SYSTEM_REV_B_USES_VAUX3) {
- rx51_twldata.vaux3 = &rx51_vaux3_mmc;
- /* Only older boards use VMMC2 for internal MMC */
- rx51_vmmc2.num_consumer_supplies--;
- } else {
- rx51_twldata.vaux3 = &rx51_vaux3_cam;
- }
- rx51_twldata.vmmc2 = &rx51_vmmc2;
- omap3_pmic_get_config(&rx51_twldata,
- TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC,
- TWL_COMMON_REGULATOR_VDAC);
-
- rx51_twldata.vdac->constraints.apply_uV = true;
- rx51_twldata.vdac->constraints.name = "VDAC";
-
- omap_pmic_init(1, 2200, "twl5030", 7 + OMAP_INTC_START, &rx51_twldata);
-#if IS_ENABLED(CONFIG_I2C_SI4713) && IS_ENABLED(CONFIG_PLATFORM_SI4713)
- err = gpio_request_one(RX51_FMTX_IRQ, GPIOF_DIR_IN, "si4713 irq");
- if (err) {
- printk(KERN_ERR "Cannot request si4713 irq gpio. %d\n", err);
- return err;
- }
- rx51_peripherals_i2c_board_info_2[0].irq = gpio_to_irq(RX51_FMTX_IRQ);
-#endif
- omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
- ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
-#if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
- rx51_lis3lv02d_data.irq2 = gpio_to_irq(LIS302_IRQ2_GPIO);
- rx51_peripherals_i2c_board_info_3[0].irq = gpio_to_irq(LIS302_IRQ1_GPIO);
-#endif
- omap_register_i2c_bus(3, 400, rx51_peripherals_i2c_board_info_3,
- ARRAY_SIZE(rx51_peripherals_i2c_board_info_3));
- return 0;
-}
-
-#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
- defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
-
-static struct mtd_partition onenand_partitions[] = {
- {
- .name = "bootloader",
- .offset = 0,
- .size = 0x20000,
- .mask_flags = MTD_WRITEABLE, /* Force read-only */
- },
- {
- .name = "config",
- .offset = MTDPART_OFS_APPEND,
- .size = 0x60000,
- },
- {
- .name = "log",
- .offset = MTDPART_OFS_APPEND,
- .size = 0x40000,
- },
- {
- .name = "kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = 0x200000,
- },
- {
- .name = "initfs",
- .offset = MTDPART_OFS_APPEND,
- .size = 0x200000,
- },
- {
- .name = "rootfs",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct omap_onenand_platform_data board_onenand_data[] = {
- {
- .cs = 0,
- .gpio_irq = 65,
- .parts = onenand_partitions,
- .nr_parts = ARRAY_SIZE(onenand_partitions),
- .flags = ONENAND_SYNC_READWRITE,
- }
-};
-#endif
-
-static struct gpio rx51_wl1251_gpios[] __initdata = {
- { RX51_WL1251_IRQ_GPIO, GPIOF_IN, "wl1251 irq" },
-};
-
-static void __init rx51_init_wl1251(void)
-{
- int irq, ret;
-
- ret = gpio_request_array(rx51_wl1251_gpios,
- ARRAY_SIZE(rx51_wl1251_gpios));
- if (ret < 0)
- goto error;
-
- irq = gpio_to_irq(RX51_WL1251_IRQ_GPIO);
- if (irq < 0)
- goto err_irq;
-
- wl1251_pdata.power_gpio = RX51_WL1251_POWER_GPIO;
- rx51_peripherals_spi_board_info[RX51_SPI_WL1251].irq = irq;
-
- return;
-
-err_irq:
- gpio_free(RX51_WL1251_IRQ_GPIO);
-error:
- printk(KERN_ERR "wl1251 board initialisation failed\n");
- wl1251_pdata.power_gpio = -1;
-
- /*
- * Now rx51_peripherals_spi_board_info[1].irq is zero and
- * set_power is null, and wl1251_probe() will fail.
- */
-}
-
-static struct tsc2005_platform_data tsc2005_pdata = {
- .ts_pressure_max = 2048,
- .ts_pressure_fudge = 2,
- .ts_x_max = 4096,
- .ts_x_fudge = 4,
- .ts_y_max = 4096,
- .ts_y_fudge = 7,
- .ts_x_plate_ohm = 280,
- .esd_timeout_ms = 8000,
-};
-
-static struct gpio rx51_tsc2005_gpios[] __initdata = {
- { RX51_TSC2005_IRQ_GPIO, GPIOF_IN, "tsc2005 IRQ" },
- { RX51_TSC2005_RESET_GPIO, GPIOF_OUT_INIT_HIGH, "tsc2005 reset" },
-};
-
-static void rx51_tsc2005_set_reset(bool enable)
-{
- gpio_set_value(RX51_TSC2005_RESET_GPIO, enable);
-}
-
-static void __init rx51_init_tsc2005(void)
-{
- int r;
-
- omap_mux_init_gpio(RX51_TSC2005_RESET_GPIO, OMAP_PIN_OUTPUT);
- omap_mux_init_gpio(RX51_TSC2005_IRQ_GPIO, OMAP_PIN_INPUT_PULLUP);
-
- r = gpio_request_array(rx51_tsc2005_gpios,
- ARRAY_SIZE(rx51_tsc2005_gpios));
- if (r < 0) {
- printk(KERN_ERR "tsc2005 board initialization failed\n");
- tsc2005_pdata.esd_timeout_ms = 0;
- return;
- }
-
- tsc2005_pdata.set_reset = rx51_tsc2005_set_reset;
- rx51_peripherals_spi_board_info[RX51_SPI_TSC2005].irq =
- gpio_to_irq(RX51_TSC2005_IRQ_GPIO);
-}
-
-#if IS_ENABLED(CONFIG_OMAP_DM_TIMER)
-static struct pwm_omap_dmtimer_pdata __maybe_unused pwm_dmtimer_pdata = {
- .request_by_node = omap_dm_timer_request_by_node,
- .request_specific = omap_dm_timer_request_specific,
- .request = omap_dm_timer_request,
- .set_source = omap_dm_timer_set_source,
- .get_irq = omap_dm_timer_get_irq,
- .set_int_enable = omap_dm_timer_set_int_enable,
- .set_int_disable = omap_dm_timer_set_int_disable,
- .free = omap_dm_timer_free,
- .enable = omap_dm_timer_enable,
- .disable = omap_dm_timer_disable,
- .get_fclk = omap_dm_timer_get_fclk,
- .start = omap_dm_timer_start,
- .stop = omap_dm_timer_stop,
- .set_load = omap_dm_timer_set_load,
- .set_match = omap_dm_timer_set_match,
- .set_pwm = omap_dm_timer_set_pwm,
- .set_prescaler = omap_dm_timer_set_prescaler,
- .read_counter = omap_dm_timer_read_counter,
- .write_counter = omap_dm_timer_write_counter,
- .read_status = omap_dm_timer_read_status,
- .write_status = omap_dm_timer_write_status,
-};
-#endif
-
-#if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE)
-static struct lirc_rx51_platform_data rx51_lirc_data = {
- .set_max_mpu_wakeup_lat = omap_pm_set_max_mpu_wakeup_lat,
-};
-
-static struct platform_device rx51_lirc_device = {
- .name = "lirc_rx51",
- .id = -1,
- .dev = {
- .platform_data = &rx51_lirc_data,
- },
-};
-
-static void __init rx51_init_lirc(void)
-{
- platform_device_register(&rx51_lirc_device);
-}
-#else
-static void __init rx51_init_lirc(void)
-{
-}
-#endif
-
-static struct platform_device madc_hwmon = {
- .name = "twl4030_madc_hwmon",
- .id = -1,
-};
-
-static void __init rx51_init_twl4030_hwmon(void)
-{
- platform_device_register(&madc_hwmon);
-}
-
-static struct platform_device omap3_rom_rng_device = {
- .name = "omap3-rom-rng",
- .id = -1,
- .dev = {
- .platform_data = rx51_secure_rng_call,
- },
-};
-
-static void __init rx51_init_omap3_rom_rng(void)
-{
- if (omap_type() == OMAP2_DEVICE_TYPE_SEC) {
- pr_info("RX-51: Registering OMAP3 HWRNG device\n");
- platform_device_register(&omap3_rom_rng_device);
- }
-}
-
-void __init rx51_peripherals_init(void)
-{
- rx51_gpio_init();
- rx51_i2c_init();
- regulator_has_full_constraints();
- gpmc_onenand_init(board_onenand_data);
- rx51_add_gpio_keys();
- rx51_init_wl1251();
- rx51_init_tsc2005();
- rx51_init_lirc();
- spi_register_board_info(rx51_peripherals_spi_board_info,
- ARRAY_SIZE(rx51_peripherals_spi_board_info));
-
- partition = omap_mux_get("core");
- if (partition)
- omap_hsmmc_init(mmc);
-
- rx51_charger_init();
- rx51_init_twl4030_hwmon();
- rx51_init_omap3_rom_rng();
-}
-
+++ /dev/null
-/*
- * linux/arch/arm/mach-omap2/board-rx51-video.c
- *
- * Copyright (C) 2010 Nokia
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/spi/spi.h>
-#include <linux/mm.h>
-#include <asm/mach-types.h>
-#include <linux/platform_data/omapdss.h>
-#include <video/omap-panel-data.h>
-
-#include <linux/platform_data/spi-omap2-mcspi.h>
-
-#include "soc.h"
-#include "board-rx51.h"
-#include "display.h"
-
-#include "mux.h"
-
-#define RX51_LCD_RESET_GPIO 90
-
-#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
-
-static struct connector_atv_platform_data rx51_tv_pdata = {
- .name = "tv",
- .source = "venc.0",
- .invert_polarity = false,
-};
-
-static struct platform_device rx51_tv_connector_device = {
- .name = "connector-analog-tv",
- .id = 0,
- .dev.platform_data = &rx51_tv_pdata,
-};
-
-static struct omap_dss_board_info rx51_dss_board_info = {
- .default_display_name = "lcd",
-};
-
-static int __init rx51_video_init(void)
-{
- if (!machine_is_nokia_rx51())
- return 0;
-
- if (omap_mux_init_gpio(RX51_LCD_RESET_GPIO, OMAP_PIN_OUTPUT)) {
- pr_err("%s cannot configure MUX for LCD RESET\n", __func__);
- return 0;
- }
-
- omap_display_init(&rx51_dss_board_info);
-
- platform_device_register(&rx51_tv_connector_device);
-
- return 0;
-}
-
-omap_subsys_initcall(rx51_video_init);
-#endif /* defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) */
+++ /dev/null
-/*
- * Board support file for Nokia N900 (aka RX-51).
- *
- * Copyright (C) 2007, 2008 Nokia
- * Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
- * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/usb/phy.h>
-#include <linux/usb/musb.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <linux/omap-dma.h>
-
-#include "common.h"
-#include "mux.h"
-#include "gpmc.h"
-#include "pm.h"
-#include "soc.h"
-#include "sdram-nokia.h"
-#include "omap-secure.h"
-
-#define RX51_GPIO_SLEEP_IND 162
-
-static struct gpio_led gpio_leds[] = {
- {
- .name = "sleep_ind",
- .gpio = RX51_GPIO_SLEEP_IND,
- },
-};
-
-static struct gpio_led_platform_data gpio_led_info = {
- .leds = gpio_leds,
- .num_leds = ARRAY_SIZE(gpio_leds),
-};
-
-static struct platform_device leds_gpio = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &gpio_led_info,
- },
-};
-
-/*
- * cpuidle C-states definition for rx51.
- *
- * The 'exit_latency' field is the sum of sleep
- * and wake-up latencies.
-
- ---------------------------------------------
- | state | exit_latency | target_residency |
- ---------------------------------------------
- | C1 | 110 + 162 | 5 |
- | C2 | 106 + 180 | 309 |
- | C3 | 107 + 410 | 46057 |
- | C4 | 121 + 3374 | 46057 |
- | C5 | 855 + 1146 | 46057 |
- | C6 | 7580 + 4134 | 484329 |
- | C7 | 7505 + 15274 | 484329 |
- ---------------------------------------------
-
-*/
-
-extern void __init rx51_peripherals_init(void);
-
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
- { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#endif
-
-static struct omap_musb_board_data musb_board_data = {
- .interface_type = MUSB_INTERFACE_ULPI,
- .mode = MUSB_OTG,
- .power = 0,
-};
-
-static void __init rx51_init(void)
-{
- struct omap_sdrc_params *sdrc_params;
-
- omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
- omap_serial_init();
-
- sdrc_params = nokia_get_sdram_timings();
- omap_sdrc_init(sdrc_params, sdrc_params);
-
- usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
- usb_musb_init(&musb_board_data);
- rx51_peripherals_init();
-
- if (omap_type() == OMAP2_DEVICE_TYPE_SEC) {
-#ifdef CONFIG_ARM_ERRATA_430973
- pr_info("RX-51: Enabling ARM errata 430973 workaround\n");
- /* set IBE to 1 */
- rx51_secure_update_aux_cr(BIT(6), 0);
-#endif
- }
-
- /* Ensure SDRC pins are mux'd for self-refresh */
- omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
- omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
-
- platform_device_register(&leds_gpio);
-}
-
-static void __init rx51_reserve(void)
-{
- omap_reserve();
-}
-
-MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
- /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */
- .atag_offset = 0x100,
- .reserve = rx51_reserve,
- .map_io = omap3_map_io,
- .init_early = omap3430_init_early,
- .init_irq = omap3_init_irq,
- .init_machine = rx51_init,
- .init_late = omap3430_init_late,
- .init_time = omap_init_time,
- .restart = omap3xxx_restart,
-MACHINE_END
+++ /dev/null
-/*
- * Defines for rx51 boards
- */
-
-#ifndef _OMAP_BOARD_RX51_H
-#define _OMAP_BOARD_RX51_H
-
-extern void __init rx51_peripherals_init(void);
-extern void __init rx51_video_mem_init(void);
-
-#endif
#include "common.h"
#include "common-board-devices.h"
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
- defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846)
static struct omap2_mcspi_device_config ads7846_mcspi_config = {
.turbo_mode = 0,
};
static inline void omap_init_sti(void) {}
-#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_OMAP24XX)
#include <linux/platform_data/spi-omap2-mcspi.h>
/*-------------------------------------------------------------------------*/
-#if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
- defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
-#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
+#if IS_ENABLED(CONFIG_VIDEO_OMAP2_VOUT)
+#if IS_ENABLED(CONFIG_FB_OMAP2)
static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
};
#else
#include "soc.h"
#include "display.h"
-#if defined(CONFIG_DRM_OMAP) || defined(CONFIG_DRM_OMAP_MODULE)
+#if IS_ENABLED(CONFIG_DRM_OMAP)
static struct omap_drm_platform_data platform_data;
int __init omap_init_vrfb(void) { return 0; }
#endif
-#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
+#if IS_ENABLED(CONFIG_FB_OMAP2)
static u64 omap_fb_dma_mask = ~(u32)0;
static struct omapfb_platform_data omapfb_config;
u32 flags;
};
-#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+#if IS_ENABLED(CONFIG_SMSC911X)
extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d);
#include "hsmmc.h"
#include "control.h"
-#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
+#if IS_ENABLED(CONFIG_MMC_OMAP_HS)
static u16 control_pbias_offset;
static u16 control_devconf1_offset;
void (*init_card)(struct mmc_card *card);
};
-#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
+#if IS_ENABLED(CONFIG_MMC_OMAP_HS)
void omap_hsmmc_init(struct omap2_hsmmc_info *);
void omap_hsmmc_late_init(struct omap2_hsmmc_info *);
}
#endif /* CONFIG_ARCH_OMAP4 */
-#if defined(CONFIG_SND_OMAP_SOC_OMAP_TWL4030) || \
- defined(CONFIG_SND_OMAP_SOC_OMAP_TWL4030_MODULE)
+#if IS_ENABLED(CONFIG_SND_OMAP_SOC_OMAP_TWL4030)
#include <linux/platform_data/omap-twl4030.h>
/* Commonly used configuration */
bool "ARM Ltd. RealView family"
depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 || ARCH_MULTI_V7
select ARM_AMBA
+ select ARM_GIC
select ARM_TIMER_SP804
+ select CLK_SP810
select COMMON_CLK_VERSATILE
select GPIO_PL061 if GPIOLIB
- select ICST
- select PLAT_VERSATILE
- select PLAT_VERSATILE_SCHED_CLOCK
- help
- This enables support for ARM Ltd RealView boards.
-
-if ARCH_REALVIEW
-
-config REALVIEW_DT
- bool "Support RealView(R) Device Tree based boot"
- select ARM_GIC
- select CLK_SP810
- select HAVE_SMP
+ select HAVE_ARM_SCU if SMP
+ select HAVE_ARM_TWD if SMP
+ select HAVE_PATA_PLATFORM
+ select HAVE_TCM
select ICST
select MACH_REALVIEW_EB if ARCH_MULTI_V5
select MFD_SYSCON
+ select PLAT_VERSATILE
+ select PLAT_VERSATILE_SCHED_CLOCK
select POWER_RESET
select POWER_RESET_VERSATILE
select POWER_SUPPLY
- select SMP_ON_UP if SMP
select SOC_REALVIEW
select USE_OF
help
- Include support for booting the ARM(R) RealView(R) evaluation
- boards using a device tree machine description.
+ This enables support for ARM Ltd RealView boards.
+
+if ARCH_REALVIEW
config MACH_REALVIEW_EB
bool "Support RealView(R) Emulation Baseboard"
config REALVIEW_EB_A9MP
bool "Support Multicore Cortex-A9 Tile"
depends on MACH_REALVIEW_EB && ARCH_MULTI_V7
- select HAVE_ARM_SCU if SMP
- select HAVE_ARM_TWD if SMP
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
help
config REALVIEW_EB_ARM11MP
bool "Support ARM11MPCore Tile"
depends on MACH_REALVIEW_EB && ARCH_MULTI_V6
- select HAVE_ARM_SCU if SMP
- select HAVE_ARM_TWD if SMP
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
help
Enable support for the ARM11MPCore tile fitted to the Realview(R)
Emulation Baseboard platform.
-config REALVIEW_EB_ARM11MP_REVB
- bool "Support ARM11MPCore RevB Tile"
- depends on REALVIEW_EB_ARM11MP && ARCH_MULTI_V6
- help
- Enable support for the ARM11MPCore Revision B tile on the
- Realview(R) Emulation Baseboard platform. Since there are device
- address differences, a kernel built with this option enabled is
- not compatible with other revisions of the ARM11MPCore tile.
-
config MACH_REALVIEW_PB11MP
bool "Support RealView(R) Platform Baseboard for ARM11MPCore"
depends on ARCH_MULTI_V6
- select ARM_GIC
- select HAVE_ARM_SCU if SMP
- select HAVE_ARM_TWD if SMP
- select HAVE_PATA_PLATFORM
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
help
config MACH_REALVIEW_PB1176
bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S"
depends on ARCH_MULTI_V6
- select ARM_GIC
select CPU_V6
select HAVE_TCM
select MIGHT_HAVE_CACHE_L2X0
Include support for the ARM(R) RealView(R) Platform Baseboard for
ARM1176JZF-S.
-config REALVIEW_PB1176_SECURE_FLASH
- bool "Allow access to the secure flash memory block"
- depends on MACH_REALVIEW_PB1176
- default n
- help
- Select this option if Linux will only run in secure mode on the
- RealView PB1176 platform and access to the secure flash memory
- block (64MB @ 0x3c000000) is required.
-
config MACH_REALVIEW_PBA8
bool "Support RealView(R) Platform Baseboard for Cortex(tm)-A8 platform"
depends on ARCH_MULTI_V7
- select ARM_GIC
- select HAVE_PATA_PLATFORM
help
Include support for the ARM(R) RealView Platform Baseboard for
Cortex(tm)-A8. This platform has an on-board Cortex-A8 and has
config MACH_REALVIEW_PBX
bool "Support RealView(R) Platform Baseboard Explore for Cortex-A9"
depends on ARCH_MULTI_V7
- select ARM_GIC
- select HAVE_ARM_SCU if SMP
- select HAVE_ARM_TWD if SMP
- select HAVE_PATA_PLATFORM
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
select ZONE_DMA
Include support for the ARM(R) RealView(R) Platform Baseboard
Explore.
-config REALVIEW_HIGH_PHYS_OFFSET
- bool "High physical base address for the RealView platform"
- depends on MMU && !MACH_REALVIEW_PB1176
- default y
- help
- RealView boards other than PB1176 have the RAM available at
- 0x70000000, 256MB of which being mirrored at 0x00000000. If
- the board supports 512MB of RAM, this option allows the
- memory to be accessed contiguously at the high physical
- offset. On the PBX board, disabling this option allows 1GB of
- RAM to be used with HIGHMEM.
-
endif
#
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-versatile/include
-obj-y := core.o
-obj-$(CONFIG_REALVIEW_DT) += realview-dt.o
+obj-y += realview-dt.o
obj-$(CONFIG_SMP) += platsmp-dt.o
-
-ifdef CONFIG_ATAGS
-obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o
-obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o
-obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o
-obj-$(CONFIG_MACH_REALVIEW_PBA8) += realview_pba8.o
-obj-$(CONFIG_MACH_REALVIEW_PBX) += realview_pbx.o
-obj-$(CONFIG_SMP) += platsmp.o
-endif
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+++ /dev/null
-/*
- * Copyright (C) 2007 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_BOARD_EB_H
-#define __ASM_ARCH_BOARD_EB_H
-
-#include "platform.h"
-
-/*
- * RealView EB + ARM11MPCore peripheral addresses
- */
-#define REALVIEW_EB_UART0_BASE 0x10009000 /* UART 0 */
-#define REALVIEW_EB_UART1_BASE 0x1000A000 /* UART 1 */
-#define REALVIEW_EB_UART2_BASE 0x1000B000 /* UART 2 */
-#define REALVIEW_EB_UART3_BASE 0x1000C000 /* UART 3 */
-#define REALVIEW_EB_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
-#define REALVIEW_EB_WATCHDOG_BASE 0x10010000 /* watchdog interface */
-#define REALVIEW_EB_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
-#define REALVIEW_EB_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
-#define REALVIEW_EB_GPIO0_BASE 0x10013000 /* GPIO port 0 */
-#define REALVIEW_EB_RTC_BASE 0x10017000 /* Real Time Clock */
-#define REALVIEW_EB_CLCD_BASE 0x10020000 /* CLCD */
-#define REALVIEW_EB_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
-#define REALVIEW_EB_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
-#define REALVIEW_EB_SMC_BASE 0x10080000 /* Static memory controller */
-
-#define REALVIEW_EB_FLASH_BASE 0x40000000
-#define REALVIEW_EB_FLASH_SIZE SZ_64M
-#define REALVIEW_EB_ETH_BASE 0x4E000000 /* Ethernet */
-#define REALVIEW_EB_USB_BASE 0x4F000000 /* USB */
-
-#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
-#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x10100000
-#define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */
-#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
-#else
-#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x1F000000
-#define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */
-#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
-#endif
-
-#define REALVIEW_EB11MP_PRIV_MEM_SIZE SZ_8K
-#define REALVIEW_EB11MP_PRIV_MEM_OFF(x) (REALVIEW_EB11MP_PRIV_MEM_BASE + (x))
-
-#define REALVIEW_EB11MP_SCU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0) /* SCU registers */
-#define REALVIEW_EB11MP_GIC_CPU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0100) /* Generic interrupt controller CPU interface */
-#define REALVIEW_EB11MP_TWD_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0600)
-#define REALVIEW_EB11MP_GIC_DIST_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x1000) /* Generic interrupt controller distributor */
-
-/*
- * Core tile identification (REALVIEW_SYS_PROCID)
- */
-#define REALVIEW_EB_PROC_MASK 0xFF000000
-#define REALVIEW_EB_PROC_ARM7TDMI 0x00000000
-#define REALVIEW_EB_PROC_ARM9 0x02000000
-#define REALVIEW_EB_PROC_ARM11 0x04000000
-#define REALVIEW_EB_PROC_ARM11MP 0x06000000
-#define REALVIEW_EB_PROC_A9MP 0x0C000000
-
-#define check_eb_proc(proc_type) \
- ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_EB_PROC_MASK) \
- == proc_type)
-
-#ifdef CONFIG_REALVIEW_EB_ARM11MP
-#define core_tile_eb11mp() check_eb_proc(REALVIEW_EB_PROC_ARM11MP)
-#else
-#define core_tile_eb11mp() 0
-#endif
-
-#ifdef CONFIG_REALVIEW_EB_A9MP
-#define core_tile_a9mp() check_eb_proc(REALVIEW_EB_PROC_A9MP)
-#else
-#define core_tile_a9mp() 0
-#endif
-
-#define machine_is_realview_eb_mp() \
- (machine_is_realview_eb() && (core_tile_eb11mp() || core_tile_a9mp()))
-
-#endif /* __ASM_ARCH_BOARD_EB_H */
+++ /dev/null
-/*
- * Copyright (C) 2008 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_BOARD_PB1176_H
-#define __ASM_ARCH_BOARD_PB1176_H
-
-#include "platform.h"
-
-/*
- * Peripheral addresses
- */
-#define REALVIEW_PB1176_UART4_BASE 0x10009000 /* UART 4 */
-#define REALVIEW_PB1176_SCTL_BASE 0x10100000 /* System controller */
-#define REALVIEW_PB1176_SMC_BASE 0x10111000 /* SMC */
-#define REALVIEW_PB1176_DMC_BASE 0x10109000 /* DMC configuration */
-#define REALVIEW_PB1176_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
-#define REALVIEW_PB1176_FLASH_BASE 0x30000000
-#define REALVIEW_PB1176_FLASH_SIZE SZ_64M
-#define REALVIEW_PB1176_SEC_FLASH_BASE 0x3C000000 /* Secure flash */
-#define REALVIEW_PB1176_SEC_FLASH_SIZE SZ_64M
-
-#define REALVIEW_PB1176_TIMER0_1_BASE 0x10104000 /* Timer 0 and 1 */
-#define REALVIEW_PB1176_TIMER2_3_BASE 0x10105000 /* Timer 2 and 3 */
-#define REALVIEW_PB1176_TIMER4_5_BASE 0x10106000 /* Timer 4 and 5 */
-#define REALVIEW_PB1176_WATCHDOG_BASE 0x10107000 /* watchdog interface */
-#define REALVIEW_PB1176_RTC_BASE 0x10108000 /* Real Time Clock */
-#define REALVIEW_PB1176_GPIO0_BASE 0x1010A000 /* GPIO port 0 */
-#define REALVIEW_PB1176_SSP_BASE 0x1010B000 /* Synchronous Serial Port */
-#define REALVIEW_PB1176_UART0_BASE 0x1010C000 /* UART 0 */
-#define REALVIEW_PB1176_UART1_BASE 0x1010D000 /* UART 1 */
-#define REALVIEW_PB1176_UART2_BASE 0x1010E000 /* UART 2 */
-#define REALVIEW_PB1176_UART3_BASE 0x1010F000 /* UART 3 */
-#define REALVIEW_PB1176_CLCD_BASE 0x10112000 /* CLCD */
-#define REALVIEW_PB1176_ETH_BASE 0x3A000000 /* Ethernet */
-#define REALVIEW_PB1176_USB_BASE 0x3B000000 /* USB */
-
-/*
- * PCI regions
- */
-#define REALVIEW_PB1176_PCI_BASE 0x60000000 /* PCI self config */
-#define REALVIEW_PB1176_PCI_CFG_BASE 0x61000000 /* PCI config */
-#define REALVIEW_PB1176_PCI_IO_BASE0 0x62000000 /* PCI IO region */
-#define REALVIEW_PB1176_PCI_MEM_BASE0 0x63000000 /* Memory region 1 */
-#define REALVIEW_PB1176_PCI_MEM_BASE1 0x64000000 /* Memory region 2 */
-#define REALVIEW_PB1176_PCI_MEM_BASE2 0x68000000 /* Memory region 3 */
-
-#define REALVIEW_PB1176_PCI_BASE_SIZE 0x01000000 /* 16MB */
-#define REALVIEW_PB1176_PCI_CFG_BASE_SIZE 0x01000000 /* 16MB */
-#define REALVIEW_PB1176_PCI_IO_BASE0_SIZE 0x01000000 /* 16MB */
-#define REALVIEW_PB1176_PCI_MEM_BASE0_SIZE 0x01000000 /* 16MB */
-#define REALVIEW_PB1176_PCI_MEM_BASE1_SIZE 0x04000000 /* 64MB */
-#define REALVIEW_PB1176_PCI_MEM_BASE2_SIZE 0x08000000 /* 128MB */
-
-#define REALVIEW_DC1176_GIC_CPU_BASE 0x10120000 /* GIC CPU interface, on devchip */
-#define REALVIEW_DC1176_GIC_DIST_BASE 0x10121000 /* GIC distributor, on devchip */
-#define REALVIEW_DC1176_ROM_BASE 0x10200000 /* 16KiB NRAM preudo-ROM, on devchip */
-#define REALVIEW_PB1176_GIC_CPU_BASE 0x10040000 /* GIC CPU interface, on FPGA */
-#define REALVIEW_PB1176_GIC_DIST_BASE 0x10041000 /* GIC distributor, on FPGA */
-#define REALVIEW_PB1176_L220_BASE 0x10110000 /* L220 registers */
-
-/*
- * Control register SYS_RESETCTL Bit 8 is set to 1 to force a soft reset
- */
-#define REALVIEW_PB1176_SYS_SOFT_RESET 0x0100
-
-#endif /* __ASM_ARCH_BOARD_PB1176_H */
+++ /dev/null
-/*
- * Copyright (C) 2008 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_BOARD_PB11MP_H
-#define __ASM_ARCH_BOARD_PB11MP_H
-
-#include "platform.h"
-
-/*
- * Peripheral addresses
- */
-#define REALVIEW_PB11MP_UART0_BASE 0x10009000 /* UART 0 */
-#define REALVIEW_PB11MP_UART1_BASE 0x1000A000 /* UART 1 */
-#define REALVIEW_PB11MP_UART2_BASE 0x1000B000 /* UART 2 */
-#define REALVIEW_PB11MP_UART3_BASE 0x1000C000 /* UART 3 */
-#define REALVIEW_PB11MP_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
-#define REALVIEW_PB11MP_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */
-#define REALVIEW_PB11MP_WATCHDOG_BASE 0x10010000 /* watchdog interface */
-#define REALVIEW_PB11MP_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
-#define REALVIEW_PB11MP_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
-#define REALVIEW_PB11MP_GPIO0_BASE 0x10013000 /* GPIO port 0 */
-#define REALVIEW_PB11MP_RTC_BASE 0x10017000 /* Real Time Clock */
-#define REALVIEW_PB11MP_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */
-#define REALVIEW_PB11MP_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */
-#define REALVIEW_PB11MP_SCTL_BASE 0x1001A000 /* System Controller */
-#define REALVIEW_PB11MP_CLCD_BASE 0x10020000 /* CLCD */
-#define REALVIEW_PB11MP_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */
-#define REALVIEW_PB11MP_DMC_BASE 0x100E0000 /* DMC configuration */
-#define REALVIEW_PB11MP_SMC_BASE 0x100E1000 /* SMC configuration */
-#define REALVIEW_PB11MP_CAN_BASE 0x100E2000 /* CAN bus */
-#define REALVIEW_PB11MP_CF_BASE 0x18000000 /* Compact flash */
-#define REALVIEW_PB11MP_CF_MEM_BASE 0x18003000 /* SMC for Compact flash */
-#define REALVIEW_PB11MP_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */
-#define REALVIEW_PB11MP_FLASH0_BASE 0x40000000
-#define REALVIEW_PB11MP_FLASH0_SIZE SZ_64M
-#define REALVIEW_PB11MP_FLASH1_BASE 0x44000000
-#define REALVIEW_PB11MP_FLASH1_SIZE SZ_64M
-#define REALVIEW_PB11MP_ETH_BASE 0x4E000000 /* Ethernet */
-#define REALVIEW_PB11MP_USB_BASE 0x4F000000 /* USB */
-#define REALVIEW_PB11MP_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */
-#define REALVIEW_PB11MP_LT_BASE 0xC0000000 /* Logic Tile expansion */
-#define REALVIEW_PB11MP_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */
-#define REALVIEW_PB11MP_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */
-
-#define REALVIEW_PB11MP_SYS_PLD_CTRL1 0x74
-
-/*
- * PB11MPCore PCI regions
- */
-#define REALVIEW_PB11MP_PCI_BASE 0x90040000 /* PCI-X Unit base */
-#define REALVIEW_PB11MP_PCI_IO_BASE 0x90050000 /* IO Region on AHB */
-#define REALVIEW_PB11MP_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */
-
-#define REALVIEW_PB11MP_PCI_BASE_SIZE 0x10000 /* 16 Kb */
-#define REALVIEW_PB11MP_PCI_IO_SIZE 0x1000 /* 4 Kb */
-#define REALVIEW_PB11MP_PCI_MEM_SIZE 0x20000000 /* 512 MB */
-
-/*
- * Testchip peripheral and fpga gic regions
- */
-#define REALVIEW_TC11MP_PRIV_MEM_BASE 0x1F000000
-#define REALVIEW_TC11MP_PRIV_MEM_SIZE SZ_8K
-#define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */
-#define REALVIEW_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */
-#define REALVIEW_TC11MP_TWD_BASE 0x1F000600
-#define REALVIEW_TC11MP_GIC_DIST_BASE 0x1F001000 /* Test chip interrupt controller distributor */
-#define REALVIEW_TC11MP_L220_BASE 0x1F002000 /* L220 registers */
-
- /*
- * Values for REALVIEW_SYS_RESET_CTRL
- */
-#define REALVIEW_PB11MP_SYS_CTRL_RESET_CONFIGCLR 0x01
-#define REALVIEW_PB11MP_SYS_CTRL_RESET_CONFIGINIT 0x02
-#define REALVIEW_PB11MP_SYS_CTRL_RESET_DLLRESET 0x03
-#define REALVIEW_PB11MP_SYS_CTRL_RESET_PLLRESET 0x04
-#define REALVIEW_PB11MP_SYS_CTRL_RESET_POR 0x05
-#define REALVIEW_PB11MP_SYS_CTRL_RESET_DoC 0x06
-
-#define REALVIEW_PB11MP_SYS_CTRL_LED (1 << 0)
-
-#endif /* __ASM_ARCH_BOARD_PB11MP_H */
+++ /dev/null
-/*
- * Copyright (C) 2008 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_BOARD_PBA8_H
-#define __ASM_ARCH_BOARD_PBA8_H
-
-#include "platform.h"
-
-/*
- * Peripheral addresses
- */
-#define REALVIEW_PBA8_UART0_BASE 0x10009000 /* UART 0 */
-#define REALVIEW_PBA8_UART1_BASE 0x1000A000 /* UART 1 */
-#define REALVIEW_PBA8_UART2_BASE 0x1000B000 /* UART 2 */
-#define REALVIEW_PBA8_UART3_BASE 0x1000C000 /* UART 3 */
-#define REALVIEW_PBA8_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
-#define REALVIEW_PBA8_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */
-#define REALVIEW_PBA8_WATCHDOG_BASE 0x10010000 /* watchdog interface */
-#define REALVIEW_PBA8_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
-#define REALVIEW_PBA8_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
-#define REALVIEW_PBA8_GPIO0_BASE 0x10013000 /* GPIO port 0 */
-#define REALVIEW_PBA8_RTC_BASE 0x10017000 /* Real Time Clock */
-#define REALVIEW_PBA8_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */
-#define REALVIEW_PBA8_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */
-#define REALVIEW_PBA8_SCTL_BASE 0x1001A000 /* System Controller */
-#define REALVIEW_PBA8_CLCD_BASE 0x10020000 /* CLCD */
-#define REALVIEW_PBA8_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */
-#define REALVIEW_PBA8_DMC_BASE 0x100E0000 /* DMC configuration */
-#define REALVIEW_PBA8_SMC_BASE 0x100E1000 /* SMC configuration */
-#define REALVIEW_PBA8_CAN_BASE 0x100E2000 /* CAN bus */
-#define REALVIEW_PBA8_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */
-#define REALVIEW_PBA8_FLASH0_BASE 0x40000000
-#define REALVIEW_PBA8_FLASH0_SIZE SZ_64M
-#define REALVIEW_PBA8_FLASH1_BASE 0x44000000
-#define REALVIEW_PBA8_FLASH1_SIZE SZ_64M
-#define REALVIEW_PBA8_ETH_BASE 0x4E000000 /* Ethernet */
-#define REALVIEW_PBA8_USB_BASE 0x4F000000 /* USB */
-#define REALVIEW_PBA8_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */
-#define REALVIEW_PBA8_LT_BASE 0xC0000000 /* Logic Tile expansion */
-#define REALVIEW_PBA8_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */
-#define REALVIEW_PBA8_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */
-
-#define REALVIEW_PBA8_SYS_PLD_CTRL1 0x74
-
-/*
- * PBA8 PCI regions
- */
-#define REALVIEW_PBA8_PCI_BASE 0x90040000 /* PCI-X Unit base */
-#define REALVIEW_PBA8_PCI_IO_BASE 0x90050000 /* IO Region on AHB */
-#define REALVIEW_PBA8_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */
-
-#define REALVIEW_PBA8_PCI_BASE_SIZE 0x10000 /* 16 Kb */
-#define REALVIEW_PBA8_PCI_IO_SIZE 0x1000 /* 4 Kb */
-#define REALVIEW_PBA8_PCI_MEM_SIZE 0x20000000 /* 512 MB */
-
-#endif /* __ASM_ARCH_BOARD_PBA8_H */
+++ /dev/null
-/*
- * Copyright (C) 2009 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_BOARD_PBX_H
-#define __ASM_ARCH_BOARD_PBX_H
-
-#include "platform.h"
-
-/*
- * Peripheral addresses
- */
-#define REALVIEW_PBX_UART0_BASE 0x10009000 /* UART 0 */
-#define REALVIEW_PBX_UART1_BASE 0x1000A000 /* UART 1 */
-#define REALVIEW_PBX_UART2_BASE 0x1000B000 /* UART 2 */
-#define REALVIEW_PBX_UART3_BASE 0x1000C000 /* UART 3 */
-#define REALVIEW_PBX_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
-#define REALVIEW_PBX_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */
-#define REALVIEW_PBX_WATCHDOG_BASE 0x10010000 /* watchdog interface */
-#define REALVIEW_PBX_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
-#define REALVIEW_PBX_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
-#define REALVIEW_PBX_GPIO0_BASE 0x10013000 /* GPIO port 0 */
-#define REALVIEW_PBX_RTC_BASE 0x10017000 /* Real Time Clock */
-#define REALVIEW_PBX_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */
-#define REALVIEW_PBX_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */
-#define REALVIEW_PBX_SCTL_BASE 0x1001A000 /* System Controller */
-#define REALVIEW_PBX_CLCD_BASE 0x10020000 /* CLCD */
-#define REALVIEW_PBX_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */
-#define REALVIEW_PBX_DMC_BASE 0x100E0000 /* DMC configuration */
-#define REALVIEW_PBX_SMC_BASE 0x100E1000 /* SMC configuration */
-#define REALVIEW_PBX_CAN_BASE 0x100E2000 /* CAN bus */
-#define REALVIEW_PBX_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */
-#define REALVIEW_PBX_FLASH0_BASE 0x40000000
-#define REALVIEW_PBX_FLASH0_SIZE SZ_64M
-#define REALVIEW_PBX_FLASH1_BASE 0x44000000
-#define REALVIEW_PBX_FLASH1_SIZE SZ_64M
-#define REALVIEW_PBX_ETH_BASE 0x4E000000 /* Ethernet */
-#define REALVIEW_PBX_USB_BASE 0x4F000000 /* USB */
-#define REALVIEW_PBX_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */
-#define REALVIEW_PBX_LT_BASE 0xC0000000 /* Logic Tile expansion */
-#define REALVIEW_PBX_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */
-#define REALVIEW_PBX_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */
-
-/*
- * Tile-specific addresses
- */
-#define REALVIEW_PBX_TILE_SCU_BASE 0x1F000000 /* SCU registers */
-#define REALVIEW_PBX_TILE_GIC_CPU_BASE 0x1F000100 /* Private Generic interrupt controller CPU interface */
-#define REALVIEW_PBX_TILE_TWD_BASE 0x1F000600
-#define REALVIEW_PBX_TILE_TWD_PERCPU_BASE 0x1F000700
-#define REALVIEW_PBX_TILE_TWD_SIZE 0x00000100
-#define REALVIEW_PBX_TILE_GIC_DIST_BASE 0x1F001000 /* Private Generic interrupt controller distributor */
-#define REALVIEW_PBX_TILE_L220_BASE 0x1F002000 /* L220 registers */
-
-#define REALVIEW_PBX_SYS_PLD_CTRL1 0x74
-
-/*
- * PBX PCI regions
- */
-#define REALVIEW_PBX_PCI_BASE 0x90040000 /* PCI-X Unit base */
-#define REALVIEW_PBX_PCI_IO_BASE 0x90050000 /* IO Region on AHB */
-#define REALVIEW_PBX_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */
-
-#define REALVIEW_PBX_PCI_BASE_SIZE 0x10000 /* 16 Kb */
-#define REALVIEW_PBX_PCI_IO_SIZE 0x1000 /* 4 Kb */
-#define REALVIEW_PBX_PCI_MEM_SIZE 0x20000000 /* 512 MB */
-
-/*
- * Core tile identification (REALVIEW_SYS_PROCID)
- */
-#define REALVIEW_PBX_PROC_MASK 0xFF000000
-#define REALVIEW_PBX_PROC_ARM7TDMI 0x00000000
-#define REALVIEW_PBX_PROC_ARM9 0x02000000
-#define REALVIEW_PBX_PROC_ARM11 0x04000000
-#define REALVIEW_PBX_PROC_ARM11MP 0x06000000
-#define REALVIEW_PBX_PROC_A9MP 0x0C000000
-#define REALVIEW_PBX_PROC_A8 0x0E000000
-
-#define check_pbx_proc(proc_type) \
- ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_PBX_PROC_MASK) \
- == proc_type)
-
-#ifdef CONFIG_MACH_REALVIEW_PBX
-#define core_tile_pbx11mp() check_pbx_proc(REALVIEW_PBX_PROC_ARM11MP)
-#define core_tile_pbxa9mp() check_pbx_proc(REALVIEW_PBX_PROC_A9MP)
-#define core_tile_pbxa8() check_pbx_proc(REALVIEW_PBX_PROC_A8)
-#else
-#define core_tile_pbx11mp() 0
-#define core_tile_pbxa9mp() 0
-#define core_tile_pbxa8() 0
-#endif
-
-#endif /* __ASM_ARCH_BOARD_PBX_H */
+++ /dev/null
-/*
- * linux/arch/arm/mach-realview/core.c
- *
- * Copyright (C) 1999 - 2003 ARM Limited
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/device.h>
-#include <linux/interrupt.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/clcd.h>
-#include <linux/platform_data/video-clcd-versatile.h>
-#include <linux/io.h>
-#include <linux/smsc911x.h>
-#include <linux/smc91x.h>
-#include <linux/ata_platform.h>
-#include <linux/amba/mmci.h>
-#include <linux/gfp.h>
-#include <linux/mtd/physmap.h>
-#include <linux/memblock.h>
-
-#include <clocksource/timer-sp804.h>
-#include "hardware.h"
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <asm/hardware/icst.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/map.h>
-
-#include "platform.h"
-
-#include <plat/sched_clock.h>
-
-#include "core.h"
-
-#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
-
-static void realview_flash_set_vpp(struct platform_device *pdev, int on)
-{
- u32 val;
-
- val = __raw_readl(REALVIEW_FLASHCTRL);
- if (on)
- val |= REALVIEW_FLASHPROG_FLVPPEN;
- else
- val &= ~REALVIEW_FLASHPROG_FLVPPEN;
- __raw_writel(val, REALVIEW_FLASHCTRL);
-}
-
-static struct physmap_flash_data realview_flash_data = {
- .width = 4,
- .set_vpp = realview_flash_set_vpp,
-};
-
-struct platform_device realview_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &realview_flash_data,
- },
-};
-
-int realview_flash_register(struct resource *res, u32 num)
-{
- realview_flash_device.resource = res;
- realview_flash_device.num_resources = num;
- return platform_device_register(&realview_flash_device);
-}
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_32BIT,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
- .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct smc91x_platdata smc91x_platdata = {
- .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT |
- SMC91X_NOWAIT,
-};
-
-static struct platform_device realview_eth_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = 2,
-};
-
-int realview_eth_register(const char *name, struct resource *res)
-{
- if (name)
- realview_eth_device.name = name;
- realview_eth_device.resource = res;
- if (strcmp(realview_eth_device.name, "smsc911x") == 0)
- realview_eth_device.dev.platform_data = &smsc911x_config;
- else
- realview_eth_device.dev.platform_data = &smc91x_platdata;
-
- return platform_device_register(&realview_eth_device);
-}
-
-struct platform_device realview_usb_device = {
- .name = "isp1760",
- .num_resources = 2,
-};
-
-int realview_usb_register(struct resource *res)
-{
- realview_usb_device.resource = res;
- return platform_device_register(&realview_usb_device);
-}
-
-static struct pata_platform_info pata_platform_data = {
- .ioport_shift = 1,
-};
-
-static struct resource pata_resources[] = {
- [0] = {
- .start = REALVIEW_CF_BASE,
- .end = REALVIEW_CF_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = REALVIEW_CF_BASE + 0x100,
- .end = REALVIEW_CF_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device realview_cf_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(pata_resources),
- .resource = pata_resources,
- .dev = {
- .platform_data = &pata_platform_data,
- },
-};
-
-static struct resource realview_leds_resources[] = {
- {
- .start = REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET,
- .end = REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET + 4,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device realview_leds_device = {
- .name = "versatile-leds",
- .id = -1,
- .num_resources = ARRAY_SIZE(realview_leds_resources),
- .resource = realview_leds_resources,
-};
-
-static struct resource realview_i2c_resource = {
- .start = REALVIEW_I2C_BASE,
- .end = REALVIEW_I2C_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
-};
-
-struct platform_device realview_i2c_device = {
- .name = "versatile-i2c",
- .id = 0,
- .num_resources = 1,
- .resource = &realview_i2c_resource,
-};
-
-static struct i2c_board_info realview_i2c_board_info[] = {
- {
- I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
- },
-};
-
-static int __init realview_i2c_init(void)
-{
- return i2c_register_board_info(0, realview_i2c_board_info,
- ARRAY_SIZE(realview_i2c_board_info));
-}
-arch_initcall(realview_i2c_init);
-
-#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
-
-/*
- * This is only used if GPIOLIB support is disabled
- */
-static unsigned int realview_mmc_status(struct device *dev)
-{
- struct amba_device *adev = container_of(dev, struct amba_device, dev);
- u32 mask;
-
- if (machine_is_realview_pb1176()) {
- static bool inserted = false;
-
- /*
- * The PB1176 does not have the status register,
- * assume it is inserted at startup, then invert
- * for each call so card insertion/removal will
- * be detected anyway. This will not be called if
- * GPIO on PL061 is active, which is the proper
- * way to do this on the PB1176.
- */
- inserted = !inserted;
- return inserted ? 0 : 1;
- }
-
- if (adev->res.start == REALVIEW_MMCI0_BASE)
- mask = 1;
- else
- mask = 2;
-
- return readl(REALVIEW_SYSMCI) & mask;
-}
-
-struct mmci_platform_data realview_mmc0_plat_data = {
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
- .status = realview_mmc_status,
- .gpio_wp = 17,
- .gpio_cd = 16,
- .cd_invert = true,
-};
-
-struct mmci_platform_data realview_mmc1_plat_data = {
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
- .status = realview_mmc_status,
- .gpio_wp = 19,
- .gpio_cd = 18,
- .cd_invert = true,
-};
-
-void __init realview_init_early(void)
-{
- void __iomem *sys = __io_address(REALVIEW_SYS_BASE);
-
- versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000);
-}
-
-/*
- * CLCD support.
- */
-#define SYS_CLCD_NLCDIOON (1 << 2)
-#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
-#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
-#define SYS_CLCD_ID_MASK (0x1f << 8)
-#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
-#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
-#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
-#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
-#define SYS_CLCD_ID_VGA (0x1f << 8)
-
-/*
- * Disable all display connectors on the interface module.
- */
-static void realview_clcd_disable(struct clcd_fb *fb)
-{
- void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
- u32 val;
-
- val = readl(sys_clcd);
- val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
- writel(val, sys_clcd);
-}
-
-/*
- * Enable the relevant connector on the interface module.
- */
-static void realview_clcd_enable(struct clcd_fb *fb)
-{
- void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
- u32 val;
-
- /*
- * Enable the PSUs
- */
- val = readl(sys_clcd);
- val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
- writel(val, sys_clcd);
-}
-
-/*
- * Detect which LCD panel is connected, and return the appropriate
- * clcd_panel structure. Note: we do not have any information on
- * the required timings for the 8.4in panel, so we presently assume
- * VGA timings.
- */
-static int realview_clcd_setup(struct clcd_fb *fb)
-{
- void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
- const char *panel_name, *vga_panel_name;
- unsigned long framesize;
- u32 val;
-
- if (machine_is_realview_eb()) {
- /* VGA, 16bpp */
- framesize = 640 * 480 * 2;
- vga_panel_name = "VGA";
- } else {
- /* XVGA, 16bpp */
- framesize = 1024 * 768 * 2;
- vga_panel_name = "XVGA";
- }
-
- val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
- if (val == SYS_CLCD_ID_SANYO_3_8)
- panel_name = "Sanyo TM38QV67A02A";
- else if (val == SYS_CLCD_ID_SANYO_2_5)
- panel_name = "Sanyo QVGA Portrait";
- else if (val == SYS_CLCD_ID_EPSON_2_2)
- panel_name = "Epson L2F50113T00";
- else if (val == SYS_CLCD_ID_VGA)
- panel_name = vga_panel_name;
- else {
- pr_err("CLCD: unknown LCD panel ID 0x%08x, using VGA\n", val);
- panel_name = vga_panel_name;
- }
-
- fb->panel = versatile_clcd_get_panel(panel_name);
- if (!fb->panel)
- return -EINVAL;
-
- return versatile_clcd_setup_dma(fb, framesize);
-}
-
-struct clcd_board clcd_plat_data = {
- .name = "RealView",
- .caps = CLCD_CAP_ALL,
- .check = clcdfb_check,
- .decode = clcdfb_decode,
- .disable = realview_clcd_disable,
- .enable = realview_clcd_enable,
- .setup = realview_clcd_setup,
- .mmap = versatile_clcd_mmap_dma,
- .remove = versatile_clcd_remove_dma,
-};
-
-/*
- * Where is the timer (VA)?
- */
-void __iomem *timer0_va_base;
-void __iomem *timer1_va_base;
-void __iomem *timer2_va_base;
-void __iomem *timer3_va_base;
-
-/*
- * Set up the clock source and clock events devices
- */
-void __init realview_timer_init(unsigned int timer_irq)
-{
- u32 val;
-
- /*
- * set clock frequency:
- * REALVIEW_REFCLK is 32KHz
- * REALVIEW_TIMCLK is 1MHz
- */
- val = readl(__io_address(REALVIEW_SCTL_BASE));
- writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
- (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
- (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
- (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
- __io_address(REALVIEW_SCTL_BASE));
-
- /*
- * Initialise to a known state (all timers off)
- */
- sp804_timer_disable(timer0_va_base);
- sp804_timer_disable(timer1_va_base);
- sp804_timer_disable(timer2_va_base);
- sp804_timer_disable(timer3_va_base);
-
- sp804_clocksource_init(timer3_va_base, "timer3");
- sp804_clockevents_init(timer0_va_base, timer_irq, "timer0");
-}
-
-/*
- * Setup the memory banks.
- */
-void realview_fixup(struct tag *tags, char **from)
-{
- /*
- * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
- * Half of this is mirrored at 0.
- */
-#ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
- memblock_add(0x70000000, SZ_512M);
-#else
- memblock_add(0, SZ_256M);
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2004 ARM Limited
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_REALVIEW_H
-#define __ASM_ARCH_REALVIEW_H
-
-#include <linux/amba/bus.h>
-#include <linux/io.h>
-
-#include <asm/setup.h>
-
-#define APB_DEVICE(name, busid, base, plat) \
-static AMBA_APB_DEVICE(name, busid, 0, REALVIEW_##base##_BASE, base##_IRQ, plat)
-
-#define AHB_DEVICE(name, busid, base, plat) \
-static AMBA_AHB_DEVICE(name, busid, 0, REALVIEW_##base##_BASE, base##_IRQ, plat)
-
-struct machine_desc;
-
-extern struct platform_device realview_flash_device;
-extern struct platform_device realview_cf_device;
-extern struct platform_device realview_leds_device;
-extern struct platform_device realview_i2c_device;
-extern struct mmci_platform_data realview_mmc0_plat_data;
-extern struct mmci_platform_data realview_mmc1_plat_data;
-extern struct clcd_board clcd_plat_data;
-extern void __iomem *timer0_va_base;
-extern void __iomem *timer1_va_base;
-extern void __iomem *timer2_va_base;
-extern void __iomem *timer3_va_base;
-
-extern void realview_timer_init(unsigned int timer_irq);
-extern int realview_flash_register(struct resource *res, u32 num);
-extern int realview_eth_register(const char *name, struct resource *res);
-extern int realview_usb_register(struct resource *res);
-extern void realview_init_early(void);
-extern void realview_fixup(struct tag *tags, char **from);
-
-extern const struct smp_operations realview_smp_ops;
-extern void realview_cpu_die(unsigned int cpu);
-
-#endif
+++ /dev/null
-/*
- * This file contains the hardware definitions of the RealView boards.
- *
- * Copyright (C) 2003 ARM Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-
-/* macro to get at IO space when running virtually */
-#ifdef CONFIG_MMU
-/*
- * Statically mapped addresses:
- *
- * 10xx xxxx -> fbxx xxxx
- * 1exx xxxx -> fdxx xxxx
- * 1fxx xxxx -> fexx xxxx
- */
-#define IO_ADDRESS(x) (((x) & 0x03ffffff) + 0xfb000000)
-#else
-#define IO_ADDRESS(x) (x)
-#endif
-#define __io_address(n) IOMEM(IO_ADDRESS(n))
-
-#endif
--- /dev/null
+void realview_cpu_die(unsigned int cpu);
+++ /dev/null
-/*
- * Copyright (C) 2007 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_IRQS_EB_H
-#define __MACH_IRQS_EB_H
-
-#define IRQ_LOCALTIMER 29
-#define IRQ_EB_GIC_START 32
-
-/*
- * RealView EB interrupt sources
- */
-#define IRQ_EB_WDOG (IRQ_EB_GIC_START + 0) /* Watchdog timer */
-#define IRQ_EB_SOFT (IRQ_EB_GIC_START + 1) /* Software interrupt */
-#define IRQ_EB_COMMRx (IRQ_EB_GIC_START + 2) /* Debug Comm Rx interrupt */
-#define IRQ_EB_COMMTx (IRQ_EB_GIC_START + 3) /* Debug Comm Tx interrupt */
-#define IRQ_EB_TIMER0_1 (IRQ_EB_GIC_START + 4) /* Timer 0 and 1 */
-#define IRQ_EB_TIMER2_3 (IRQ_EB_GIC_START + 5) /* Timer 2 and 3 */
-#define IRQ_EB_GPIO0 (IRQ_EB_GIC_START + 6) /* GPIO 0 */
-#define IRQ_EB_GPIO1 (IRQ_EB_GIC_START + 7) /* GPIO 1 */
-#define IRQ_EB_GPIO2 (IRQ_EB_GIC_START + 8) /* GPIO 2 */
- /* 9 reserved */
-#define IRQ_EB_RTC (IRQ_EB_GIC_START + 10) /* Real Time Clock */
-#define IRQ_EB_SSP (IRQ_EB_GIC_START + 11) /* Synchronous Serial Port */
-#define IRQ_EB_UART0 (IRQ_EB_GIC_START + 12) /* UART 0 on development chip */
-#define IRQ_EB_UART1 (IRQ_EB_GIC_START + 13) /* UART 1 on development chip */
-#define IRQ_EB_UART2 (IRQ_EB_GIC_START + 14) /* UART 2 on development chip */
-#define IRQ_EB_UART3 (IRQ_EB_GIC_START + 15) /* UART 3 on development chip */
-#define IRQ_EB_SCI (IRQ_EB_GIC_START + 16) /* Smart Card Interface */
-#define IRQ_EB_MMCI0A (IRQ_EB_GIC_START + 17) /* Multimedia Card 0A */
-#define IRQ_EB_MMCI0B (IRQ_EB_GIC_START + 18) /* Multimedia Card 0B */
-#define IRQ_EB_AACI (IRQ_EB_GIC_START + 19) /* Audio Codec */
-#define IRQ_EB_KMI0 (IRQ_EB_GIC_START + 20) /* Keyboard/Mouse port 0 */
-#define IRQ_EB_KMI1 (IRQ_EB_GIC_START + 21) /* Keyboard/Mouse port 1 */
-#define IRQ_EB_CHARLCD (IRQ_EB_GIC_START + 22) /* Character LCD */
-#define IRQ_EB_CLCD (IRQ_EB_GIC_START + 23) /* CLCD controller */
-#define IRQ_EB_DMA (IRQ_EB_GIC_START + 24) /* DMA controller */
-#define IRQ_EB_PWRFAIL (IRQ_EB_GIC_START + 25) /* Power failure */
-#define IRQ_EB_PISMO (IRQ_EB_GIC_START + 26) /* PISMO interface */
-#define IRQ_EB_DoC (IRQ_EB_GIC_START + 27) /* Disk on Chip memory controller */
-#define IRQ_EB_ETH (IRQ_EB_GIC_START + 28) /* Ethernet controller */
-#define IRQ_EB_USB (IRQ_EB_GIC_START + 29) /* USB controller */
-#define IRQ_EB_TSPEN (IRQ_EB_GIC_START + 30) /* Touchscreen pen */
-#define IRQ_EB_TSKPAD (IRQ_EB_GIC_START + 31) /* Touchscreen keypad */
-
-/*
- * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile)
- */
-#define IRQ_EB11MP_AACI (IRQ_EB_GIC_START + 0)
-#define IRQ_EB11MP_TIMER0_1 (IRQ_EB_GIC_START + 1)
-#define IRQ_EB11MP_TIMER2_3 (IRQ_EB_GIC_START + 2)
-#define IRQ_EB11MP_USB (IRQ_EB_GIC_START + 3)
-#define IRQ_EB11MP_UART0 (IRQ_EB_GIC_START + 4)
-#define IRQ_EB11MP_UART1 (IRQ_EB_GIC_START + 5)
-#define IRQ_EB11MP_RTC (IRQ_EB_GIC_START + 6)
-#define IRQ_EB11MP_KMI0 (IRQ_EB_GIC_START + 7)
-#define IRQ_EB11MP_KMI1 (IRQ_EB_GIC_START + 8)
-#define IRQ_EB11MP_ETH (IRQ_EB_GIC_START + 9)
-#define IRQ_EB11MP_EB_IRQ1 (IRQ_EB_GIC_START + 10) /* main GIC */
-#define IRQ_EB11MP_EB_IRQ2 (IRQ_EB_GIC_START + 11) /* tile GIC */
-#define IRQ_EB11MP_EB_FIQ1 (IRQ_EB_GIC_START + 12) /* main GIC */
-#define IRQ_EB11MP_EB_FIQ2 (IRQ_EB_GIC_START + 13) /* tile GIC */
-#define IRQ_EB11MP_MMCI0A (IRQ_EB_GIC_START + 14)
-#define IRQ_EB11MP_MMCI0B (IRQ_EB_GIC_START + 15)
-
-#define IRQ_EB11MP_PMU_CPU0 (IRQ_EB_GIC_START + 17)
-#define IRQ_EB11MP_PMU_CPU1 (IRQ_EB_GIC_START + 18)
-#define IRQ_EB11MP_PMU_CPU2 (IRQ_EB_GIC_START + 19)
-#define IRQ_EB11MP_PMU_CPU3 (IRQ_EB_GIC_START + 20)
-#define IRQ_EB11MP_PMU_SCU0 (IRQ_EB_GIC_START + 21)
-#define IRQ_EB11MP_PMU_SCU1 (IRQ_EB_GIC_START + 22)
-#define IRQ_EB11MP_PMU_SCU2 (IRQ_EB_GIC_START + 23)
-#define IRQ_EB11MP_PMU_SCU3 (IRQ_EB_GIC_START + 24)
-#define IRQ_EB11MP_PMU_SCU4 (IRQ_EB_GIC_START + 25)
-#define IRQ_EB11MP_PMU_SCU5 (IRQ_EB_GIC_START + 26)
-#define IRQ_EB11MP_PMU_SCU6 (IRQ_EB_GIC_START + 27)
-#define IRQ_EB11MP_PMU_SCU7 (IRQ_EB_GIC_START + 28)
-
-#define IRQ_EB11MP_L220_EVENT (IRQ_EB_GIC_START + 29)
-#define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30)
-#define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31)
-
-/*
- * The 11MPcore tile leaves the following unconnected.
- */
-#define IRQ_EB11MP_UART2 0
-#define IRQ_EB11MP_UART3 0
-#define IRQ_EB11MP_CLCD 0
-#define IRQ_EB11MP_DMA 0
-#define IRQ_EB11MP_WDOG 0
-#define IRQ_EB11MP_GPIO0 0
-#define IRQ_EB11MP_GPIO1 0
-#define IRQ_EB11MP_GPIO2 0
-#define IRQ_EB11MP_SCI 0
-#define IRQ_EB11MP_SSP 0
-
-#define NR_GIC_EB11MP 2
-
-#endif /* __MACH_IRQS_EB_H */
+++ /dev/null
-/*
- * Copyright (C) 2008 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_IRQS_PB1176_H
-#define __MACH_IRQS_PB1176_H
-
-#define IRQ_DC1176_GIC_START 32
-#define IRQ_PB1176_GIC_START 64
-
-/*
- * ARM1176 DevChip interrupt sources (primary GIC)
- */
-#define IRQ_DC1176_WATCHDOG (IRQ_DC1176_GIC_START + 0) /* Watchdog timer */
-#define IRQ_DC1176_SOFTINT (IRQ_DC1176_GIC_START + 1) /* Software interrupt */
-#define IRQ_DC1176_COMMRx (IRQ_DC1176_GIC_START + 2) /* Debug Comm Rx interrupt */
-#define IRQ_DC1176_COMMTx (IRQ_DC1176_GIC_START + 3) /* Debug Comm Tx interrupt */
-#define IRQ_DC1176_CORE_PMU (IRQ_DC1176_GIC_START + 7) /* Core PMU interrupt */
-#define IRQ_DC1176_TIMER0 (IRQ_DC1176_GIC_START + 8) /* Timer 0 */
-#define IRQ_DC1176_TIMER1 (IRQ_DC1176_GIC_START + 9) /* Timer 1 */
-#define IRQ_DC1176_TIMER2 (IRQ_DC1176_GIC_START + 10) /* Timer 2 */
-#define IRQ_DC1176_APC (IRQ_DC1176_GIC_START + 11)
-#define IRQ_DC1176_IEC (IRQ_DC1176_GIC_START + 12)
-#define IRQ_DC1176_L2CC (IRQ_DC1176_GIC_START + 13)
-#define IRQ_DC1176_RTC (IRQ_DC1176_GIC_START + 14)
-#define IRQ_DC1176_CLCD (IRQ_DC1176_GIC_START + 15) /* CLCD controller */
-#define IRQ_DC1176_GPIO0 (IRQ_DC1176_GIC_START + 16)
-#define IRQ_DC1176_SSP (IRQ_DC1176_GIC_START + 17) /* SSP port */
-#define IRQ_DC1176_UART0 (IRQ_DC1176_GIC_START + 18) /* UART 0 on development chip */
-#define IRQ_DC1176_UART1 (IRQ_DC1176_GIC_START + 19) /* UART 1 on development chip */
-#define IRQ_DC1176_UART2 (IRQ_DC1176_GIC_START + 20) /* UART 2 on development chip */
-#define IRQ_DC1176_UART3 (IRQ_DC1176_GIC_START + 21) /* UART 3 on development chip */
-
-#define IRQ_DC1176_PB_IRQ2 (IRQ_DC1176_GIC_START + 30) /* tile GIC */
-#define IRQ_DC1176_PB_IRQ1 (IRQ_DC1176_GIC_START + 31) /* main GIC */
-
-/*
- * RealView PB1176 interrupt sources (secondary GIC)
- */
-#define IRQ_PB1176_MMCI0A (IRQ_PB1176_GIC_START + 1) /* Multimedia Card 0A */
-#define IRQ_PB1176_MMCI0B (IRQ_PB1176_GIC_START + 2) /* Multimedia Card 0A */
-#define IRQ_PB1176_KMI0 (IRQ_PB1176_GIC_START + 3) /* Keyboard/Mouse port 0 */
-#define IRQ_PB1176_KMI1 (IRQ_PB1176_GIC_START + 4) /* Keyboard/Mouse port 1 */
-#define IRQ_PB1176_SCI (IRQ_PB1176_GIC_START + 5)
-#define IRQ_PB1176_UART4 (IRQ_PB1176_GIC_START + 6) /* UART 4 on baseboard */
-#define IRQ_PB1176_CHARLCD (IRQ_PB1176_GIC_START + 7) /* Character LCD */
-#define IRQ_PB1176_GPIO1 (IRQ_PB1176_GIC_START + 8)
-#define IRQ_PB1176_GPIO2 (IRQ_PB1176_GIC_START + 9)
-#define IRQ_PB1176_ETH (IRQ_PB1176_GIC_START + 10) /* Ethernet controller */
-#define IRQ_PB1176_USB (IRQ_PB1176_GIC_START + 11) /* USB controller */
-
-#define IRQ_PB1176_PISMO (IRQ_PB1176_GIC_START + 16)
-
-#define IRQ_PB1176_AACI (IRQ_PB1176_GIC_START + 19) /* Audio Codec */
-
-#define IRQ_PB1176_TIMER0_1 (IRQ_PB1176_GIC_START + 22)
-#define IRQ_PB1176_TIMER2_3 (IRQ_PB1176_GIC_START + 23)
-#define IRQ_PB1176_DMAC (IRQ_PB1176_GIC_START + 24) /* DMA controller */
-#define IRQ_PB1176_RTC (IRQ_PB1176_GIC_START + 25) /* Real Time Clock */
-
-#define IRQ_PB1176_SCTL -1
-
-#endif /* __MACH_IRQS_PB1176_H */
+++ /dev/null
-/*
- * Copyright (C) 2008 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_IRQS_PB11MP_H
-#define __MACH_IRQS_PB11MP_H
-
-#define IRQ_LOCALTIMER 29
-#define IRQ_TC11MP_GIC_START 32
-#define IRQ_PB11MP_GIC_START 64
-
-/*
- * ARM11MPCore test chip interrupt sources (primary GIC on the test chip)
- */
-#define IRQ_TC11MP_AACI (IRQ_TC11MP_GIC_START + 0)
-#define IRQ_TC11MP_TIMER0_1 (IRQ_TC11MP_GIC_START + 1)
-#define IRQ_TC11MP_TIMER2_3 (IRQ_TC11MP_GIC_START + 2)
-#define IRQ_TC11MP_USB (IRQ_TC11MP_GIC_START + 3)
-#define IRQ_TC11MP_UART0 (IRQ_TC11MP_GIC_START + 4)
-#define IRQ_TC11MP_UART1 (IRQ_TC11MP_GIC_START + 5)
-#define IRQ_TC11MP_RTC (IRQ_TC11MP_GIC_START + 6)
-#define IRQ_TC11MP_KMI0 (IRQ_TC11MP_GIC_START + 7)
-#define IRQ_TC11MP_KMI1 (IRQ_TC11MP_GIC_START + 8)
-#define IRQ_TC11MP_ETH (IRQ_TC11MP_GIC_START + 9)
-#define IRQ_TC11MP_PB_IRQ1 (IRQ_TC11MP_GIC_START + 10) /* main GIC */
-#define IRQ_TC11MP_PB_IRQ2 (IRQ_TC11MP_GIC_START + 11) /* tile GIC */
-#define IRQ_TC11MP_PB_FIQ1 (IRQ_TC11MP_GIC_START + 12) /* main GIC */
-#define IRQ_TC11MP_PB_FIQ2 (IRQ_TC11MP_GIC_START + 13) /* tile GIC */
-#define IRQ_TC11MP_MMCI0A (IRQ_TC11MP_GIC_START + 14)
-#define IRQ_TC11MP_MMCI0B (IRQ_TC11MP_GIC_START + 15)
-
-#define IRQ_TC11MP_PMU_CPU0 (IRQ_TC11MP_GIC_START + 17)
-#define IRQ_TC11MP_PMU_CPU1 (IRQ_TC11MP_GIC_START + 18)
-#define IRQ_TC11MP_PMU_CPU2 (IRQ_TC11MP_GIC_START + 19)
-#define IRQ_TC11MP_PMU_CPU3 (IRQ_TC11MP_GIC_START + 20)
-#define IRQ_TC11MP_PMU_SCU0 (IRQ_TC11MP_GIC_START + 21)
-#define IRQ_TC11MP_PMU_SCU1 (IRQ_TC11MP_GIC_START + 22)
-#define IRQ_TC11MP_PMU_SCU2 (IRQ_TC11MP_GIC_START + 23)
-#define IRQ_TC11MP_PMU_SCU3 (IRQ_TC11MP_GIC_START + 24)
-#define IRQ_TC11MP_PMU_SCU4 (IRQ_TC11MP_GIC_START + 25)
-#define IRQ_TC11MP_PMU_SCU5 (IRQ_TC11MP_GIC_START + 26)
-#define IRQ_TC11MP_PMU_SCU6 (IRQ_TC11MP_GIC_START + 27)
-#define IRQ_TC11MP_PMU_SCU7 (IRQ_TC11MP_GIC_START + 28)
-
-#define IRQ_TC11MP_L220_EVENT (IRQ_TC11MP_GIC_START + 29)
-#define IRQ_TC11MP_L220_SLAVE (IRQ_TC11MP_GIC_START + 30)
-#define IRQ_TC11MP_L220_DECODE (IRQ_TC11MP_GIC_START + 31)
-
-/*
- * RealView PB11MPCore GIC interrupt sources (secondary GIC on the board)
- */
-#define IRQ_PB11MP_WATCHDOG (IRQ_PB11MP_GIC_START + 0) /* Watchdog timer */
-#define IRQ_PB11MP_SOFT (IRQ_PB11MP_GIC_START + 1) /* Software interrupt */
-#define IRQ_PB11MP_COMMRx (IRQ_PB11MP_GIC_START + 2) /* Debug Comm Rx interrupt */
-#define IRQ_PB11MP_COMMTx (IRQ_PB11MP_GIC_START + 3) /* Debug Comm Tx interrupt */
-#define IRQ_PB11MP_GPIO0 (IRQ_PB11MP_GIC_START + 6) /* GPIO 0 */
-#define IRQ_PB11MP_GPIO1 (IRQ_PB11MP_GIC_START + 7) /* GPIO 1 */
-#define IRQ_PB11MP_GPIO2 (IRQ_PB11MP_GIC_START + 8) /* GPIO 2 */
- /* 9 reserved */
-#define IRQ_PB11MP_RTC_GIC1 (IRQ_PB11MP_GIC_START + 10) /* Real Time Clock */
-#define IRQ_PB11MP_SSP (IRQ_PB11MP_GIC_START + 11) /* Synchronous Serial Port */
-#define IRQ_PB11MP_UART0_GIC1 (IRQ_PB11MP_GIC_START + 12) /* UART 0 on development chip */
-#define IRQ_PB11MP_UART1_GIC1 (IRQ_PB11MP_GIC_START + 13) /* UART 1 on development chip */
-#define IRQ_PB11MP_UART2 (IRQ_PB11MP_GIC_START + 14) /* UART 2 on development chip */
-#define IRQ_PB11MP_UART3 (IRQ_PB11MP_GIC_START + 15) /* UART 3 on development chip */
-#define IRQ_PB11MP_SCI (IRQ_PB11MP_GIC_START + 16) /* Smart Card Interface */
-#define IRQ_PB11MP_MMCI0A_GIC1 (IRQ_PB11MP_GIC_START + 17) /* Multimedia Card 0A */
-#define IRQ_PB11MP_MMCI0B_GIC1 (IRQ_PB11MP_GIC_START + 18) /* Multimedia Card 0B */
-#define IRQ_PB11MP_AACI_GIC1 (IRQ_PB11MP_GIC_START + 19) /* Audio Codec */
-#define IRQ_PB11MP_KMI0_GIC1 (IRQ_PB11MP_GIC_START + 20) /* Keyboard/Mouse port 0 */
-#define IRQ_PB11MP_KMI1_GIC1 (IRQ_PB11MP_GIC_START + 21) /* Keyboard/Mouse port 1 */
-#define IRQ_PB11MP_CHARLCD (IRQ_PB11MP_GIC_START + 22) /* Character LCD */
-#define IRQ_PB11MP_CLCD (IRQ_PB11MP_GIC_START + 23) /* CLCD controller */
-#define IRQ_PB11MP_DMAC (IRQ_PB11MP_GIC_START + 24) /* DMA controller */
-#define IRQ_PB11MP_PWRFAIL (IRQ_PB11MP_GIC_START + 25) /* Power failure */
-#define IRQ_PB11MP_PISMO (IRQ_PB11MP_GIC_START + 26) /* PISMO interface */
-#define IRQ_PB11MP_DoC (IRQ_PB11MP_GIC_START + 27) /* Disk on Chip memory controller */
-#define IRQ_PB11MP_ETH_GIC1 (IRQ_PB11MP_GIC_START + 28) /* Ethernet controller */
-#define IRQ_PB11MP_USB_GIC1 (IRQ_PB11MP_GIC_START + 29) /* USB controller */
-#define IRQ_PB11MP_TSPEN (IRQ_PB11MP_GIC_START + 30) /* Touchscreen pen */
-#define IRQ_PB11MP_TSKPAD (IRQ_PB11MP_GIC_START + 31) /* Touchscreen keypad */
-
-#endif /* __MACH_IRQS_PB11MP_H */
+++ /dev/null
-/*
- * Copyright (C) 2008 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_IRQS_PBA8_H
-#define __MACH_IRQS_PBA8_H
-
-#define IRQ_PBA8_GIC_START 32
-
-/*
- * PB-A8 on-board gic irq sources
- */
-#define IRQ_PBA8_WATCHDOG (IRQ_PBA8_GIC_START + 0) /* Watchdog timer */
-#define IRQ_PBA8_SOFT (IRQ_PBA8_GIC_START + 1) /* Software interrupt */
-#define IRQ_PBA8_COMMRx (IRQ_PBA8_GIC_START + 2) /* Debug Comm Rx interrupt */
-#define IRQ_PBA8_COMMTx (IRQ_PBA8_GIC_START + 3) /* Debug Comm Tx interrupt */
-#define IRQ_PBA8_TIMER0_1 (IRQ_PBA8_GIC_START + 4) /* Timer 0/1 (default timer) */
-#define IRQ_PBA8_TIMER2_3 (IRQ_PBA8_GIC_START + 5) /* Timer 2/3 */
-#define IRQ_PBA8_GPIO0 (IRQ_PBA8_GIC_START + 6) /* GPIO 0 */
-#define IRQ_PBA8_GPIO1 (IRQ_PBA8_GIC_START + 7) /* GPIO 1 */
-#define IRQ_PBA8_GPIO2 (IRQ_PBA8_GIC_START + 8) /* GPIO 2 */
- /* 9 reserved */
-#define IRQ_PBA8_RTC (IRQ_PBA8_GIC_START + 10) /* Real Time Clock */
-#define IRQ_PBA8_SSP (IRQ_PBA8_GIC_START + 11) /* Synchronous Serial Port */
-#define IRQ_PBA8_UART0 (IRQ_PBA8_GIC_START + 12) /* UART 0 on development chip */
-#define IRQ_PBA8_UART1 (IRQ_PBA8_GIC_START + 13) /* UART 1 on development chip */
-#define IRQ_PBA8_UART2 (IRQ_PBA8_GIC_START + 14) /* UART 2 on development chip */
-#define IRQ_PBA8_UART3 (IRQ_PBA8_GIC_START + 15) /* UART 3 on development chip */
-#define IRQ_PBA8_SCI (IRQ_PBA8_GIC_START + 16) /* Smart Card Interface */
-#define IRQ_PBA8_MMCI0A (IRQ_PBA8_GIC_START + 17) /* Multimedia Card 0A */
-#define IRQ_PBA8_MMCI0B (IRQ_PBA8_GIC_START + 18) /* Multimedia Card 0B */
-#define IRQ_PBA8_AACI (IRQ_PBA8_GIC_START + 19) /* Audio Codec */
-#define IRQ_PBA8_KMI0 (IRQ_PBA8_GIC_START + 20) /* Keyboard/Mouse port 0 */
-#define IRQ_PBA8_KMI1 (IRQ_PBA8_GIC_START + 21) /* Keyboard/Mouse port 1 */
-#define IRQ_PBA8_CHARLCD (IRQ_PBA8_GIC_START + 22) /* Character LCD */
-#define IRQ_PBA8_CLCD (IRQ_PBA8_GIC_START + 23) /* CLCD controller */
-#define IRQ_PBA8_DMAC (IRQ_PBA8_GIC_START + 24) /* DMA controller */
-#define IRQ_PBA8_PWRFAIL (IRQ_PBA8_GIC_START + 25) /* Power failure */
-#define IRQ_PBA8_PISMO (IRQ_PBA8_GIC_START + 26) /* PISMO interface */
-#define IRQ_PBA8_DoC (IRQ_PBA8_GIC_START + 27) /* Disk on Chip memory controller */
-#define IRQ_PBA8_ETH (IRQ_PBA8_GIC_START + 28) /* Ethernet controller */
-#define IRQ_PBA8_USB (IRQ_PBA8_GIC_START + 29) /* USB controller */
-#define IRQ_PBA8_TSPEN (IRQ_PBA8_GIC_START + 30) /* Touchscreen pen */
-#define IRQ_PBA8_TSKPAD (IRQ_PBA8_GIC_START + 31) /* Touchscreen keypad */
-
-#define IRQ_PBA8_PMU (IRQ_PBA8_GIC_START + 47) /* Cortex-A8 PMU */
-
-/* ... */
-#define IRQ_PBA8_PCI0 (IRQ_PBA8_GIC_START + 50)
-#define IRQ_PBA8_PCI1 (IRQ_PBA8_GIC_START + 51)
-#define IRQ_PBA8_PCI2 (IRQ_PBA8_GIC_START + 52)
-#define IRQ_PBA8_PCI3 (IRQ_PBA8_GIC_START + 53)
-
-#define IRQ_PBA8_SMC -1
-#define IRQ_PBA8_SCTL -1
-
-#endif /* __MACH_IRQS_PBA8_H */
+++ /dev/null
-/*
- * Copyright (C) 2009 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __MACH_IRQS_PBX_H
-#define __MACH_IRQS_PBX_H
-
-#define IRQ_LOCALTIMER 29
-#define IRQ_PBX_GIC_START 32
-
-/*
- * PBX on-board gic irq sources
- */
-#define IRQ_PBX_WATCHDOG (IRQ_PBX_GIC_START + 0) /* Watchdog timer */
-#define IRQ_PBX_SOFT (IRQ_PBX_GIC_START + 1) /* Software interrupt */
-#define IRQ_PBX_COMMRx (IRQ_PBX_GIC_START + 2) /* Debug Comm Rx interrupt */
-#define IRQ_PBX_COMMTx (IRQ_PBX_GIC_START + 3) /* Debug Comm Tx interrupt */
-#define IRQ_PBX_TIMER0_1 (IRQ_PBX_GIC_START + 4) /* Timer 0/1 (default timer) */
-#define IRQ_PBX_TIMER2_3 (IRQ_PBX_GIC_START + 5) /* Timer 2/3 */
-#define IRQ_PBX_GPIO0 (IRQ_PBX_GIC_START + 6) /* GPIO 0 */
-#define IRQ_PBX_GPIO1 (IRQ_PBX_GIC_START + 7) /* GPIO 1 */
-#define IRQ_PBX_GPIO2 (IRQ_PBX_GIC_START + 8) /* GPIO 2 */
- /* 9 reserved */
-#define IRQ_PBX_RTC (IRQ_PBX_GIC_START + 10) /* Real Time Clock */
-#define IRQ_PBX_SSP (IRQ_PBX_GIC_START + 11) /* Synchronous Serial Port */
-#define IRQ_PBX_UART0 (IRQ_PBX_GIC_START + 12) /* UART 0 on development chip */
-#define IRQ_PBX_UART1 (IRQ_PBX_GIC_START + 13) /* UART 1 on development chip */
-#define IRQ_PBX_UART2 (IRQ_PBX_GIC_START + 14) /* UART 2 on development chip */
-#define IRQ_PBX_UART3 (IRQ_PBX_GIC_START + 15) /* UART 3 on development chip */
-#define IRQ_PBX_SCI (IRQ_PBX_GIC_START + 16) /* Smart Card Interface */
-#define IRQ_PBX_MMCI0A (IRQ_PBX_GIC_START + 17) /* Multimedia Card 0A */
-#define IRQ_PBX_MMCI0B (IRQ_PBX_GIC_START + 18) /* Multimedia Card 0B */
-#define IRQ_PBX_AACI (IRQ_PBX_GIC_START + 19) /* Audio Codec */
-#define IRQ_PBX_KMI0 (IRQ_PBX_GIC_START + 20) /* Keyboard/Mouse port 0 */
-#define IRQ_PBX_KMI1 (IRQ_PBX_GIC_START + 21) /* Keyboard/Mouse port 1 */
-#define IRQ_PBX_CHARLCD (IRQ_PBX_GIC_START + 22) /* Character LCD */
-#define IRQ_PBX_CLCD (IRQ_PBX_GIC_START + 23) /* CLCD controller */
-#define IRQ_PBX_DMAC (IRQ_PBX_GIC_START + 24) /* DMA controller */
-#define IRQ_PBX_PWRFAIL (IRQ_PBX_GIC_START + 25) /* Power failure */
-#define IRQ_PBX_PISMO (IRQ_PBX_GIC_START + 26) /* PISMO interface */
-#define IRQ_PBX_DoC (IRQ_PBX_GIC_START + 27) /* Disk on Chip memory controller */
-#define IRQ_PBX_ETH (IRQ_PBX_GIC_START + 28) /* Ethernet controller */
-#define IRQ_PBX_USB (IRQ_PBX_GIC_START + 29) /* USB controller */
-#define IRQ_PBX_TSPEN (IRQ_PBX_GIC_START + 30) /* Touchscreen pen */
-#define IRQ_PBX_TSKPAD (IRQ_PBX_GIC_START + 31) /* Touchscreen keypad */
-
-#define IRQ_PBX_PMU_SCU0 (IRQ_PBX_GIC_START + 32) /* SCU PMU Interrupts (11mp) */
-#define IRQ_PBX_PMU_SCU1 (IRQ_PBX_GIC_START + 33)
-#define IRQ_PBX_PMU_SCU2 (IRQ_PBX_GIC_START + 34)
-#define IRQ_PBX_PMU_SCU3 (IRQ_PBX_GIC_START + 35)
-#define IRQ_PBX_PMU_SCU4 (IRQ_PBX_GIC_START + 36)
-#define IRQ_PBX_PMU_SCU5 (IRQ_PBX_GIC_START + 37)
-#define IRQ_PBX_PMU_SCU6 (IRQ_PBX_GIC_START + 38)
-#define IRQ_PBX_PMU_SCU7 (IRQ_PBX_GIC_START + 39)
-
-#define IRQ_PBX_WATCHDOG1 (IRQ_PBX_GIC_START + 40) /* Watchdog1 timer */
-#define IRQ_PBX_TIMER4_5 (IRQ_PBX_GIC_START + 41) /* Timer 0/1 (default timer) */
-#define IRQ_PBX_TIMER6_7 (IRQ_PBX_GIC_START + 42) /* Timer 2/3 */
-/* ... */
-#define IRQ_PBX_PMU_CPU0 (IRQ_PBX_GIC_START + 44) /* CPU PMU Interrupts */
-#define IRQ_PBX_PMU_CPU1 (IRQ_PBX_GIC_START + 45)
-#define IRQ_PBX_PMU_CPU2 (IRQ_PBX_GIC_START + 46)
-#define IRQ_PBX_PMU_CPU3 (IRQ_PBX_GIC_START + 47)
-
-/* ... */
-#define IRQ_PBX_PCI0 (IRQ_PBX_GIC_START + 50)
-#define IRQ_PBX_PCI1 (IRQ_PBX_GIC_START + 51)
-#define IRQ_PBX_PCI2 (IRQ_PBX_GIC_START + 52)
-#define IRQ_PBX_PCI3 (IRQ_PBX_GIC_START + 53)
-
-#define IRQ_PBX_SMC -1
-#define IRQ_PBX_SCTL -1
-
-#endif /* __MACH_IRQS_PBX_H */
+++ /dev/null
-/*
- * Copyright (c) ARM Limited 2003. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_PLATFORM_H
-#define __ASM_ARCH_PLATFORM_H
-
-/*
- * Memory definitions
- */
-#define REALVIEW_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)...*/
-#define REALVIEW_BOOT_ROM_HI 0x30000000
-#define REALVIEW_BOOT_ROM_BASE REALVIEW_BOOT_ROM_HI /* Normal position */
-#define REALVIEW_BOOT_ROM_SIZE SZ_64M
-
-#define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */
-#define REALVIEW_SSRAM_SIZE SZ_2M
-
-/*
- * SDRAM
- */
-#define REALVIEW_SDRAM_BASE 0x00000000
-
-/*
- * Logic expansion modules
- *
- */
-
-
-/* ------------------------------------------------------------------------
- * RealView Registers
- * ------------------------------------------------------------------------
- *
- */
-#define REALVIEW_SYS_ID_OFFSET 0x00
-#define REALVIEW_SYS_SW_OFFSET 0x04
-#define REALVIEW_SYS_LED_OFFSET 0x08
-#define REALVIEW_SYS_OSC0_OFFSET 0x0C
-
-#define REALVIEW_SYS_OSC1_OFFSET 0x10
-#define REALVIEW_SYS_OSC2_OFFSET 0x14
-#define REALVIEW_SYS_OSC3_OFFSET 0x18
-#define REALVIEW_SYS_OSC4_OFFSET 0x1C /* OSC1 for RealView/AB */
-
-#define REALVIEW_SYS_LOCK_OFFSET 0x20
-#define REALVIEW_SYS_100HZ_OFFSET 0x24
-#define REALVIEW_SYS_CFGDATA1_OFFSET 0x28
-#define REALVIEW_SYS_CFGDATA2_OFFSET 0x2C
-#define REALVIEW_SYS_FLAGS_OFFSET 0x30
-#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30
-#define REALVIEW_SYS_FLAGSCLR_OFFSET 0x34
-#define REALVIEW_SYS_NVFLAGS_OFFSET 0x38
-#define REALVIEW_SYS_NVFLAGSSET_OFFSET 0x38
-#define REALVIEW_SYS_NVFLAGSCLR_OFFSET 0x3C
-#define REALVIEW_SYS_RESETCTL_OFFSET 0x40
-#define REALVIEW_SYS_PCICTL_OFFSET 0x44
-#define REALVIEW_SYS_MCI_OFFSET 0x48
-#define REALVIEW_SYS_FLASH_OFFSET 0x4C
-#define REALVIEW_SYS_CLCD_OFFSET 0x50
-#define REALVIEW_SYS_CLCDSER_OFFSET 0x54
-#define REALVIEW_SYS_BOOTCS_OFFSET 0x58
-#define REALVIEW_SYS_24MHz_OFFSET 0x5C
-#define REALVIEW_SYS_MISC_OFFSET 0x60
-#define REALVIEW_SYS_IOSEL_OFFSET 0x70
-#define REALVIEW_SYS_PROCID_OFFSET 0x84
-#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0
-#define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4
-#define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8
-#define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC
-#define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0
-
-#define REALVIEW_SYS_BASE 0x10000000
-#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
-#define REALVIEW_SYS_SW (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET)
-#define REALVIEW_SYS_LED (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET)
-#define REALVIEW_SYS_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET)
-#define REALVIEW_SYS_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET)
-
-#define REALVIEW_SYS_LOCK (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET)
-#define REALVIEW_SYS_100HZ (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET)
-#define REALVIEW_SYS_CFGDATA1 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET)
-#define REALVIEW_SYS_CFGDATA2 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET)
-#define REALVIEW_SYS_FLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET)
-#define REALVIEW_SYS_FLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET)
-#define REALVIEW_SYS_FLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET)
-#define REALVIEW_SYS_NVFLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET)
-#define REALVIEW_SYS_NVFLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET)
-#define REALVIEW_SYS_NVFLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET)
-#define REALVIEW_SYS_RESETCTL (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET)
-#define REALVIEW_SYS_PCICTL (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET)
-#define REALVIEW_SYS_MCI (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET)
-#define REALVIEW_SYS_FLASH (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET)
-#define REALVIEW_SYS_CLCD (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET)
-#define REALVIEW_SYS_CLCDSER (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET)
-#define REALVIEW_SYS_BOOTCS (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
-#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
-#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
-#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
-#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET)
-#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
-#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
-#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
-#define REALVIEW_SYS_TEST_OSC3 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET)
-#define REALVIEW_SYS_TEST_OSC4 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET)
-
-/* ------------------------------------------------------------------------
- * RealView control registers
- * ------------------------------------------------------------------------
- */
-
-/*
- * REALVIEW_IDFIELD
- *
- * 31:24 = manufacturer (0x41 = ARM)
- * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
- * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
- * 11:4 = build value
- * 3:0 = revision number (0x1 = rev B (AHB))
- */
-
-/*
- * REALVIEW_SYS_LOCK
- * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
- * SYS_CLD, SYS_BOOTCS
- */
-#define REALVIEW_SYS_LOCK_LOCKED (1 << 16)
-#define REALVIEW_SYS_LOCK_VAL 0xA05F /* Enable write access */
-
-/*
- * REALVIEW_SYS_FLASH
- */
-#define REALVIEW_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
-
-/*
- * REALVIEW_INTREG
- * - used to acknowledge and control MMCI and UART interrupts
- */
-#define REALVIEW_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */
-#define REALVIEW_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */
-#define REALVIEW_INTREG_CARDIN 0x08 /* MMCI card in detect */
- /* write 1 to acknowledge and clear */
-#define REALVIEW_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */
-#define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */
-
-/*
- * RealView common peripheral addresses
- */
-#define REALVIEW_SCTL_BASE 0x10001000 /* System controller */
-#define REALVIEW_I2C_BASE 0x10002000 /* I2C control */
-#define REALVIEW_AACI_BASE 0x10004000 /* Audio */
-#define REALVIEW_MMCI0_BASE 0x10005000 /* MMC interface */
-#define REALVIEW_KMI0_BASE 0x10006000 /* KMI interface */
-#define REALVIEW_KMI1_BASE 0x10007000 /* KMI 2nd interface */
-#define REALVIEW_CHAR_LCD_BASE 0x10008000 /* Character LCD */
-#define REALVIEW_SCI_BASE 0x1000E000 /* Smart card controller */
-#define REALVIEW_GPIO1_BASE 0x10014000 /* GPIO port 1 */
-#define REALVIEW_GPIO2_BASE 0x10015000 /* GPIO port 2 */
-#define REALVIEW_DMC_BASE 0x10018000 /* DMC configuration */
-#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */
-
-/* PCI space */
-#define REALVIEW_PCI_BASE 0x41000000 /* PCI Interface */
-#define REALVIEW_PCI_CFG_BASE 0x42000000
-#define REALVIEW_PCI_MEM_BASE0 0x44000000
-#define REALVIEW_PCI_MEM_BASE1 0x50000000
-#define REALVIEW_PCI_MEM_BASE2 0x60000000
-/* Sizes of above maps */
-#define REALVIEW_PCI_BASE_SIZE 0x01000000
-#define REALVIEW_PCI_CFG_BASE_SIZE 0x02000000
-#define REALVIEW_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */
-#define REALVIEW_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */
-#define REALVIEW_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */
-
-#define REALVIEW_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
-#define REALVIEW_LT_BASE 0x80000000 /* Logic Tile expansion */
-
-/*
- * CompactFlash
- */
-#define REALVIEW_CF_BASE 0x18000000 /* CompactFlash */
-#define REALVIEW_CF_MEM_BASE 0x18003000 /* SMC for CompactFlash */
-
-/*
- * Disk on Chip
- */
-#define REALVIEW_DOC_BASE 0x2C000000
-#define REALVIEW_DOC_SIZE (16 << 20)
-#define REALVIEW_DOC_PAGE_SIZE 512
-#define REALVIEW_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE)
-
-#define ERASE_UNIT_PAGES 32
-#define START_PAGE 0x80
-
-/*
- * LED settings, bits [7:0]
- */
-#define REALVIEW_SYS_LED0 (1 << 0)
-#define REALVIEW_SYS_LED1 (1 << 1)
-#define REALVIEW_SYS_LED2 (1 << 2)
-#define REALVIEW_SYS_LED3 (1 << 3)
-#define REALVIEW_SYS_LED4 (1 << 4)
-#define REALVIEW_SYS_LED5 (1 << 5)
-#define REALVIEW_SYS_LED6 (1 << 6)
-#define REALVIEW_SYS_LED7 (1 << 7)
-
-#define ALL_LEDS 0xFF
-
-#define LED_BANK REALVIEW_SYS_LED
-
-/*
- * Control registers
- */
-#define REALVIEW_IDFIELD_OFFSET 0x0 /* RealView build information */
-#define REALVIEW_FLASHPROG_OFFSET 0x4 /* Flash devices */
-#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */
-#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */
-
-/*
- * System controller bit assignment
- */
-#define REALVIEW_REFCLK 0
-#define REALVIEW_TIMCLK 1
-
-#define REALVIEW_TIMER1_EnSel 15
-#define REALVIEW_TIMER2_EnSel 17
-#define REALVIEW_TIMER3_EnSel 19
-#define REALVIEW_TIMER4_EnSel 21
-
-
-#define REALVIEW_CSR_BASE 0x10000000
-#define REALVIEW_CSR_SIZE 0x10000000
-
-#endif /* __ASM_ARCH_PLATFORM_H */
#include <asm/smp_scu.h>
#include <plat/platsmp.h>
-
-#include "core.h"
+#include "hotplug.h"
#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30
+++ /dev/null
-/*
- * linux/arch/arm/mach-realview/platsmp.c
- *
- * Copyright (C) 2002 ARM Ltd.
- * All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-#include <linux/io.h>
-
-#include "hardware.h"
-#include <asm/mach-types.h>
-#include <asm/smp_scu.h>
-
-#include "board-eb.h"
-#include "board-pb11mp.h"
-#include "board-pbx.h"
-
-#include <plat/platsmp.h>
-
-#include "core.h"
-
-static void __iomem *scu_base_addr(void)
-{
- if (machine_is_realview_eb_mp())
- return __io_address(REALVIEW_EB11MP_SCU_BASE);
- else if (machine_is_realview_pb11mp())
- return __io_address(REALVIEW_TC11MP_SCU_BASE);
- else if (machine_is_realview_pbx() &&
- (core_tile_pbx11mp() || core_tile_pbxa9mp()))
- return __io_address(REALVIEW_PBX_TILE_SCU_BASE);
- else
- return (void __iomem *)0;
-}
-
-/*
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system.
- */
-static void __init realview_smp_init_cpus(void)
-{
- void __iomem *scu_base = scu_base_addr();
- unsigned int i, ncores;
-
- ncores = scu_base ? scu_get_core_count(scu_base) : 1;
-
- /* sanity check */
- if (ncores > nr_cpu_ids) {
- pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
- ncores, nr_cpu_ids);
- ncores = nr_cpu_ids;
- }
-
- for (i = 0; i < ncores; i++)
- set_cpu_possible(i, true);
-}
-
-static void __init realview_smp_prepare_cpus(unsigned int max_cpus)
-{
-
- scu_enable(scu_base_addr());
-
- /*
- * Write the address of secondary startup into the
- * system-wide flags register. The BootMonitor waits
- * until it receives a soft interrupt, and then the
- * secondary CPU branches to this address.
- */
- __raw_writel(virt_to_phys(versatile_secondary_startup),
- __io_address(REALVIEW_SYS_FLAGSSET));
-}
-
-const struct smp_operations realview_smp_ops __initconst = {
- .smp_init_cpus = realview_smp_init_cpus,
- .smp_prepare_cpus = realview_smp_prepare_cpus,
- .smp_secondary_init = versatile_secondary_init,
- .smp_boot_secondary = versatile_boot_secondary,
-#ifdef CONFIG_HOTPLUG_CPU
- .cpu_die = realview_cpu_die,
-#endif
-};
+++ /dev/null
-/*
- * linux/arch/arm/mach-realview/realview_eb.c
- *
- * Copyright (C) 2004 ARM Limited
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/device.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/pl061.h>
-#include <linux/amba/mmci.h>
-#include <linux/amba/pl022.h>
-#include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
-#include <linux/platform_data/clk-realview.h>
-#include <linux/reboot.h>
-
-#include "hardware.h"
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <asm/pgtable.h>
-#include <asm/hardware/cache-l2x0.h>
-#include <asm/smp_twd.h>
-#include <asm/system_info.h>
-#include <asm/outercache.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-
-#include "board-eb.h"
-#include "irqs-eb.h"
-
-#include "core.h"
-
-static struct map_desc realview_eb_io_desc[] __initdata = {
- {
- .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
- .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_EB_GIC_CPU_BASE),
- .pfn = __phys_to_pfn(REALVIEW_EB_GIC_CPU_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_EB_GIC_DIST_BASE),
- .pfn = __phys_to_pfn(REALVIEW_EB_GIC_DIST_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
- .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_EB_TIMER0_1_BASE),
- .pfn = __phys_to_pfn(REALVIEW_EB_TIMER0_1_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_EB_TIMER2_3_BASE),
- .pfn = __phys_to_pfn(REALVIEW_EB_TIMER2_3_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- },
-#ifdef CONFIG_DEBUG_LL
- {
- .virtual = IO_ADDRESS(REALVIEW_EB_UART0_BASE),
- .pfn = __phys_to_pfn(REALVIEW_EB_UART0_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }
-#endif
-};
-
-static struct map_desc realview_eb11mp_io_desc[] __initdata = {
- {
- .virtual = IO_ADDRESS(REALVIEW_EB11MP_PRIV_MEM_BASE),
- .pfn = __phys_to_pfn(REALVIEW_EB11MP_PRIV_MEM_BASE),
- .length = REALVIEW_EB11MP_PRIV_MEM_SIZE,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE),
- .pfn = __phys_to_pfn(REALVIEW_EB11MP_L220_BASE),
- .length = SZ_8K,
- .type = MT_DEVICE,
- }
-};
-
-static void __init realview_eb_map_io(void)
-{
- iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc));
- if (core_tile_eb11mp() || core_tile_a9mp())
- iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc));
-}
-
-static struct pl061_platform_data gpio0_plat_data = {
- .gpio_base = 0,
-};
-
-static struct pl061_platform_data gpio1_plat_data = {
- .gpio_base = 8,
-};
-
-static struct pl061_platform_data gpio2_plat_data = {
- .gpio_base = 16,
-};
-
-static struct pl022_ssp_controller ssp0_plat_data = {
- .bus_id = 0,
- .enable_dma = 0,
- .num_chipselect = 1,
-};
-
-/*
- * RealView EB AMBA devices
- */
-
-/*
- * These devices are connected via the core APB bridge
- */
-#define GPIO2_IRQ { IRQ_EB_GPIO2 }
-#define GPIO3_IRQ { IRQ_EB_GPIO3 }
-
-#define AACI_IRQ { IRQ_EB_AACI }
-#define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B }
-#define KMI0_IRQ { IRQ_EB_KMI0 }
-#define KMI1_IRQ { IRQ_EB_KMI1 }
-
-/*
- * These devices are connected directly to the multi-layer AHB switch
- */
-#define EB_SMC_IRQ { }
-#define MPMC_IRQ { }
-#define EB_CLCD_IRQ { IRQ_EB_CLCD }
-#define DMAC_IRQ { IRQ_EB_DMA }
-
-/*
- * These devices are connected via the core APB bridge
- */
-#define SCTL_IRQ { }
-#define EB_WATCHDOG_IRQ { IRQ_EB_WDOG }
-#define EB_GPIO0_IRQ { IRQ_EB_GPIO0 }
-#define GPIO1_IRQ { IRQ_EB_GPIO1 }
-#define EB_RTC_IRQ { IRQ_EB_RTC }
-
-/*
- * These devices are connected via the DMA APB bridge
- */
-#define SCI_IRQ { IRQ_EB_SCI }
-#define EB_UART0_IRQ { IRQ_EB_UART0 }
-#define EB_UART1_IRQ { IRQ_EB_UART1 }
-#define EB_UART2_IRQ { IRQ_EB_UART2 }
-#define EB_UART3_IRQ { IRQ_EB_UART3 }
-#define EB_SSP_IRQ { IRQ_EB_SSP }
-
-/* FPGA Primecells */
-APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
-APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
-APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
-APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
-APB_DEVICE(uart3, "fpga:uart3", EB_UART3, NULL);
-
-/* DevChip Primecells */
-AHB_DEVICE(smc, "dev:smc", EB_SMC, NULL);
-AHB_DEVICE(clcd, "dev:clcd", EB_CLCD, &clcd_plat_data);
-AHB_DEVICE(dmac, "dev:dmac", DMAC, NULL);
-AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
-APB_DEVICE(wdog, "dev:wdog", EB_WATCHDOG, NULL);
-APB_DEVICE(gpio0, "dev:gpio0", EB_GPIO0, &gpio0_plat_data);
-APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
-APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
-APB_DEVICE(rtc, "dev:rtc", EB_RTC, NULL);
-APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
-APB_DEVICE(uart0, "dev:uart0", EB_UART0, NULL);
-APB_DEVICE(uart1, "dev:uart1", EB_UART1, NULL);
-APB_DEVICE(uart2, "dev:uart2", EB_UART2, NULL);
-APB_DEVICE(ssp0, "dev:ssp0", EB_SSP, &ssp0_plat_data);
-
-static struct amba_device *amba_devs[] __initdata = {
- &dmac_device,
- &uart0_device,
- &uart1_device,
- &uart2_device,
- &uart3_device,
- &smc_device,
- &clcd_device,
- &sctl_device,
- &wdog_device,
- &gpio0_device,
- &gpio1_device,
- &gpio2_device,
- &rtc_device,
- &sci0_device,
- &ssp0_device,
- &aaci_device,
- &mmc0_device,
- &kmi0_device,
- &kmi1_device,
-};
-
-/*
- * RealView EB platform devices
- */
-static struct resource realview_eb_flash_resource = {
- .start = REALVIEW_EB_FLASH_BASE,
- .end = REALVIEW_EB_FLASH_BASE + REALVIEW_EB_FLASH_SIZE - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct resource realview_eb_eth_resources[] = {
- [0] = {
- .start = REALVIEW_EB_ETH_BASE,
- .end = REALVIEW_EB_ETH_BASE + SZ_64K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_EB_ETH,
- .end = IRQ_EB_ETH,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- },
-};
-
-/*
- * Detect and register the correct Ethernet device. RealView/EB rev D
- * platforms use the newer SMSC LAN9118 Ethernet chip
- */
-static int eth_device_register(void)
-{
- void __iomem *eth_addr = ioremap(REALVIEW_EB_ETH_BASE, SZ_4K);
- const char *name = NULL;
- u32 idrev;
-
- if (!eth_addr)
- return -ENOMEM;
-
- idrev = readl(eth_addr + 0x50);
- if ((idrev & 0xFFFF0000) != 0x01180000)
- /* SMSC LAN9118 not present, use LAN91C111 instead */
- name = "smc91x";
-
- iounmap(eth_addr);
- return realview_eth_register(name, realview_eb_eth_resources);
-}
-
-static struct resource realview_eb_isp1761_resources[] = {
- [0] = {
- .start = REALVIEW_EB_USB_BASE,
- .end = REALVIEW_EB_USB_BASE + SZ_128K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_EB_USB,
- .end = IRQ_EB_USB,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct resource pmu_resources[] = {
- [0] = {
- .start = IRQ_EB11MP_PMU_CPU0,
- .end = IRQ_EB11MP_PMU_CPU0,
- .flags = IORESOURCE_IRQ,
- },
- [1] = {
- .start = IRQ_EB11MP_PMU_CPU1,
- .end = IRQ_EB11MP_PMU_CPU1,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .start = IRQ_EB11MP_PMU_CPU2,
- .end = IRQ_EB11MP_PMU_CPU2,
- .flags = IORESOURCE_IRQ,
- },
- [3] = {
- .start = IRQ_EB11MP_PMU_CPU3,
- .end = IRQ_EB11MP_PMU_CPU3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device pmu_device = {
- .id = -1,
- .num_resources = ARRAY_SIZE(pmu_resources),
- .resource = pmu_resources,
-};
-
-static struct resource char_lcd_resources[] = {
- {
- .start = REALVIEW_CHAR_LCD_BASE,
- .end = (REALVIEW_CHAR_LCD_BASE + SZ_4K - 1),
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_EB_CHARLCD,
- .end = IRQ_EB_CHARLCD,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device char_lcd_device = {
- .name = "arm-charlcd",
- .id = -1,
- .num_resources = ARRAY_SIZE(char_lcd_resources),
- .resource = char_lcd_resources,
-};
-
-static void __init gic_init_irq(void)
-{
- if (core_tile_eb11mp() || core_tile_a9mp()) {
- unsigned int pldctrl;
-
- /* new irq mode */
- writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
- pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
- pldctrl |= 0x00800000;
- writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
- writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
-
- /* core tile GIC, primary */
- gic_init(0, 29, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE),
- __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
-
-#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
- /* board GIC, secondary */
- gic_init(1, 96, __io_address(REALVIEW_EB_GIC_DIST_BASE),
- __io_address(REALVIEW_EB_GIC_CPU_BASE));
- gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
-#endif
- } else {
- /* board GIC, primary */
- gic_init(0, 29, __io_address(REALVIEW_EB_GIC_DIST_BASE),
- __io_address(REALVIEW_EB_GIC_CPU_BASE));
- }
-}
-
-/*
- * Fix up the IRQ numbers for the RealView EB/ARM11MPCore tile
- */
-static void realview_eb11mp_fixup(void)
-{
- /* AMBA devices */
- dmac_device.irq[0] = IRQ_EB11MP_DMA;
- uart0_device.irq[0] = IRQ_EB11MP_UART0;
- uart1_device.irq[0] = IRQ_EB11MP_UART1;
- uart2_device.irq[0] = IRQ_EB11MP_UART2;
- uart3_device.irq[0] = IRQ_EB11MP_UART3;
- clcd_device.irq[0] = IRQ_EB11MP_CLCD;
- wdog_device.irq[0] = IRQ_EB11MP_WDOG;
- gpio0_device.irq[0] = IRQ_EB11MP_GPIO0;
- gpio1_device.irq[0] = IRQ_EB11MP_GPIO1;
- gpio2_device.irq[0] = IRQ_EB11MP_GPIO2;
- rtc_device.irq[0] = IRQ_EB11MP_RTC;
- sci0_device.irq[0] = IRQ_EB11MP_SCI;
- ssp0_device.irq[0] = IRQ_EB11MP_SSP;
- aaci_device.irq[0] = IRQ_EB11MP_AACI;
- mmc0_device.irq[0] = IRQ_EB11MP_MMCI0A;
- mmc0_device.irq[1] = IRQ_EB11MP_MMCI0B;
- kmi0_device.irq[0] = IRQ_EB11MP_KMI0;
- kmi1_device.irq[0] = IRQ_EB11MP_KMI1;
-
- /* platform devices */
- realview_eb_eth_resources[1].start = IRQ_EB11MP_ETH;
- realview_eb_eth_resources[1].end = IRQ_EB11MP_ETH;
- realview_eb_isp1761_resources[1].start = IRQ_EB11MP_USB;
- realview_eb_isp1761_resources[1].end = IRQ_EB11MP_USB;
-}
-
-#ifdef CONFIG_HAVE_ARM_TWD
-static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
- REALVIEW_EB11MP_TWD_BASE,
- IRQ_LOCALTIMER);
-
-static void __init realview_eb_twd_init(void)
-{
- if (core_tile_eb11mp() || core_tile_a9mp()) {
- int err = twd_local_timer_register(&twd_local_timer);
- if (err)
- pr_err("twd_local_timer_register failed %d\n", err);
- }
-}
-#else
-#define realview_eb_twd_init() do { } while(0)
-#endif
-
-static void __init realview_eb_timer_init(void)
-{
- unsigned int timer_irq;
-
- timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE);
- timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20;
- timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE);
- timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20;
-
- if (core_tile_eb11mp() || core_tile_a9mp())
- timer_irq = IRQ_EB11MP_TIMER0_1;
- else
- timer_irq = IRQ_EB_TIMER0_1;
-
- realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
- realview_timer_init(timer_irq);
- realview_eb_twd_init();
-}
-
-static void realview_eb_restart(enum reboot_mode mode, const char *cmd)
-{
- void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
- void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
-
- /*
- * To reset, we hit the on-board reset register
- * in the system FPGA
- */
- __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
- if (core_tile_eb11mp())
- __raw_writel(0x0008, reset_ctrl);
- dsb();
-}
-
-static void __init realview_eb_init(void)
-{
- int i;
-
- if (core_tile_eb11mp() || core_tile_a9mp()) {
- realview_eb11mp_fixup();
-
-#ifdef CONFIG_CACHE_L2X0
- /*
- * The PL220 needs to be manually configured as the hardware
- * doesn't report the correct sizes.
- * 1MB (128KB/way), 8-way associativity, event monitor and
- * parity enabled, ignore share bit, no force write allocate
- * Bits: .... ...0 0111 1001 0000 .... .... ....
- */
- l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
-
- /*
- * due to a bug in the l220 cache controller, we must not call
- * the sync function. stub it out here instead!
- */
- outer_cache.sync = NULL;
-#endif
- pmu_device.name = core_tile_a9mp() ? "armv7-pmu" : "armv6-pmu";
- platform_device_register(&pmu_device);
- }
-
- realview_flash_register(&realview_eb_flash_resource, 1);
- platform_device_register(&realview_i2c_device);
- platform_device_register(&char_lcd_device);
- platform_device_register(&realview_leds_device);
- eth_device_register();
- realview_usb_register(realview_eb_isp1761_resources);
-
- for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
- struct amba_device *d = amba_devs[i];
- amba_device_register(d, &iomem_resource);
- }
-}
-
-MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
- /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
- .atag_offset = 0x100,
- .smp = smp_ops(realview_smp_ops),
- .fixup = realview_fixup,
- .map_io = realview_eb_map_io,
- .init_early = realview_init_early,
- .init_irq = gic_init_irq,
- .init_time = realview_eb_timer_init,
- .init_machine = realview_eb_init,
-#ifdef CONFIG_ZONE_DMA
- .dma_zone_size = SZ_256M,
-#endif
- .restart = realview_eb_restart,
-MACHINE_END
+++ /dev/null
-/*
- * linux/arch/arm/mach-realview/realview_pb1176.c
- *
- * Copyright (C) 2008 ARM Limited
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/device.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/pl061.h>
-#include <linux/amba/mmci.h>
-#include <linux/amba/pl022.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/partitions.h>
-#include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
-#include <linux/platform_data/clk-realview.h>
-#include <linux/reboot.h>
-#include <linux/memblock.h>
-
-#include "hardware.h"
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <asm/pgtable.h>
-#include <asm/hardware/cache-l2x0.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-
-#include "board-pb1176.h"
-#include "irqs-pb1176.h"
-
-#include "core.h"
-
-static struct map_desc realview_pb1176_io_desc[] __initdata = {
- {
- .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
- .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_CPU_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PB1176_GIC_CPU_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_DIST_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PB1176_GIC_DIST_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_CPU_BASE),
- .pfn = __phys_to_pfn(REALVIEW_DC1176_GIC_CPU_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_DIST_BASE),
- .pfn = __phys_to_pfn(REALVIEW_DC1176_GIC_DIST_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
- .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER0_1_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PB1176_TIMER0_1_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER2_3_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PB1176_TIMER2_3_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_PB1176_L220_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PB1176_L220_BASE),
- .length = SZ_8K,
- .type = MT_DEVICE,
- },
-#ifdef CONFIG_DEBUG_LL
- {
- .virtual = IO_ADDRESS(REALVIEW_PB1176_UART0_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PB1176_UART0_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- },
-#endif
-};
-
-static void __init realview_pb1176_map_io(void)
-{
- iotable_init(realview_pb1176_io_desc, ARRAY_SIZE(realview_pb1176_io_desc));
-}
-
-static struct pl061_platform_data gpio0_plat_data = {
- .gpio_base = 0,
-};
-
-static struct pl061_platform_data gpio1_plat_data = {
- .gpio_base = 8,
-};
-
-static struct pl061_platform_data gpio2_plat_data = {
- .gpio_base = 16,
-};
-
-static struct pl022_ssp_controller ssp0_plat_data = {
- .bus_id = 0,
- .enable_dma = 0,
- .num_chipselect = 1,
-};
-
-/*
- * RealView PB1176 AMBA devices
- */
-#define GPIO2_IRQ { IRQ_PB1176_GPIO2 }
-#define GPIO3_IRQ { IRQ_PB1176_GPIO3 }
-#define AACI_IRQ { IRQ_PB1176_AACI }
-#define MMCI0_IRQ { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B }
-#define KMI0_IRQ { IRQ_PB1176_KMI0 }
-#define KMI1_IRQ { IRQ_PB1176_KMI1 }
-#define PB1176_SMC_IRQ { }
-#define MPMC_IRQ { }
-#define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD }
-#define SCTL_IRQ { }
-#define PB1176_WATCHDOG_IRQ { IRQ_DC1176_WATCHDOG }
-#define PB1176_GPIO0_IRQ { IRQ_DC1176_GPIO0 }
-#define GPIO1_IRQ { IRQ_PB1176_GPIO1 }
-#define PB1176_RTC_IRQ { IRQ_DC1176_RTC }
-#define SCI_IRQ { IRQ_PB1176_SCI }
-#define PB1176_UART0_IRQ { IRQ_DC1176_UART0 }
-#define PB1176_UART1_IRQ { IRQ_DC1176_UART1 }
-#define PB1176_UART2_IRQ { IRQ_DC1176_UART2 }
-#define PB1176_UART3_IRQ { IRQ_DC1176_UART3 }
-#define PB1176_UART4_IRQ { IRQ_PB1176_UART4 }
-#define PB1176_SSP_IRQ { IRQ_DC1176_SSP }
-
-/* FPGA Primecells */
-APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
-APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
-APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
-APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
-APB_DEVICE(uart4, "fpga:uart4", PB1176_UART4, NULL);
-
-/* DevChip Primecells */
-AHB_DEVICE(smc, "dev:smc", PB1176_SMC, NULL);
-AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
-APB_DEVICE(wdog, "dev:wdog", PB1176_WATCHDOG, NULL);
-APB_DEVICE(gpio0, "dev:gpio0", PB1176_GPIO0, &gpio0_plat_data);
-APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
-APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
-APB_DEVICE(rtc, "dev:rtc", PB1176_RTC, NULL);
-APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
-APB_DEVICE(uart0, "dev:uart0", PB1176_UART0, NULL);
-APB_DEVICE(uart1, "dev:uart1", PB1176_UART1, NULL);
-APB_DEVICE(uart2, "dev:uart2", PB1176_UART2, NULL);
-APB_DEVICE(uart3, "dev:uart3", PB1176_UART3, NULL);
-APB_DEVICE(ssp0, "dev:ssp0", PB1176_SSP, &ssp0_plat_data);
-AHB_DEVICE(clcd, "dev:clcd", PB1176_CLCD, &clcd_plat_data);
-
-static struct amba_device *amba_devs[] __initdata = {
- &uart0_device,
- &uart1_device,
- &uart2_device,
- &uart3_device,
- &uart4_device,
- &smc_device,
- &clcd_device,
- &sctl_device,
- &wdog_device,
- &gpio0_device,
- &gpio1_device,
- &gpio2_device,
- &rtc_device,
- &sci0_device,
- &ssp0_device,
- &aaci_device,
- &mmc0_device,
- &kmi0_device,
- &kmi1_device,
-};
-
-/*
- * RealView PB1176 platform devices
- */
-static struct resource realview_pb1176_flash_resources[] = {
- {
- .start = REALVIEW_PB1176_FLASH_BASE,
- .end = REALVIEW_PB1176_FLASH_BASE + REALVIEW_PB1176_FLASH_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_REALVIEW_PB1176_SECURE_FLASH
- {
- .start = REALVIEW_PB1176_SEC_FLASH_BASE,
- .end = REALVIEW_PB1176_SEC_FLASH_BASE + REALVIEW_PB1176_SEC_FLASH_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-#endif
-};
-
-static struct physmap_flash_data pb1176_rom_pdata = {
- .probe_type = "map_rom",
- .width = 4,
- .nr_parts = 0,
-};
-
-static struct resource pb1176_rom_resources[] = {
- /*
- * This exposes the PB1176 DevChip ROM as an MTD ROM mapping.
- * The reference manual states that this is actually a pseudo-ROM
- * programmed in NVRAM.
- */
- {
- .start = REALVIEW_DC1176_ROM_BASE,
- .end = REALVIEW_DC1176_ROM_BASE + SZ_16K - 1,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct platform_device pb1176_rom_device = {
- .name = "physmap-flash",
- .id = -1,
- .num_resources = ARRAY_SIZE(pb1176_rom_resources),
- .resource = pb1176_rom_resources,
- .dev = {
- .platform_data = &pb1176_rom_pdata,
- },
-};
-
-static struct resource realview_pb1176_smsc911x_resources[] = {
- [0] = {
- .start = REALVIEW_PB1176_ETH_BASE,
- .end = REALVIEW_PB1176_ETH_BASE + SZ_64K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PB1176_ETH,
- .end = IRQ_PB1176_ETH,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct resource realview_pb1176_isp1761_resources[] = {
- [0] = {
- .start = REALVIEW_PB1176_USB_BASE,
- .end = REALVIEW_PB1176_USB_BASE + SZ_128K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PB1176_USB,
- .end = IRQ_PB1176_USB,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct resource pmu_resource = {
- .start = IRQ_DC1176_CORE_PMU,
- .end = IRQ_DC1176_CORE_PMU,
- .flags = IORESOURCE_IRQ,
-};
-
-static struct platform_device pmu_device = {
- .name = "armv6-pmu",
- .id = -1,
- .num_resources = 1,
- .resource = &pmu_resource,
-};
-
-static struct resource char_lcd_resources[] = {
- {
- .start = REALVIEW_CHAR_LCD_BASE,
- .end = (REALVIEW_CHAR_LCD_BASE + SZ_4K - 1),
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PB1176_CHARLCD,
- .end = IRQ_PB1176_CHARLCD,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device char_lcd_device = {
- .name = "arm-charlcd",
- .id = -1,
- .num_resources = ARRAY_SIZE(char_lcd_resources),
- .resource = char_lcd_resources,
-};
-
-static void __init gic_init_irq(void)
-{
- /* ARM1176 DevChip GIC, primary */
- gic_init(0, IRQ_DC1176_GIC_START,
- __io_address(REALVIEW_DC1176_GIC_DIST_BASE),
- __io_address(REALVIEW_DC1176_GIC_CPU_BASE));
-
- /* board GIC, secondary */
- gic_init(1, IRQ_PB1176_GIC_START,
- __io_address(REALVIEW_PB1176_GIC_DIST_BASE),
- __io_address(REALVIEW_PB1176_GIC_CPU_BASE));
- gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1);
-}
-
-static void __init realview_pb1176_timer_init(void)
-{
- timer0_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE);
- timer1_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE) + 0x20;
- timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE);
- timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20;
-
- realview_clk_init(__io_address(REALVIEW_SYS_BASE), true);
- realview_timer_init(IRQ_DC1176_TIMER0);
-}
-
-static void realview_pb1176_restart(enum reboot_mode mode, const char *cmd)
-{
- void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
- void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
- __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
- __raw_writel(REALVIEW_PB1176_SYS_SOFT_RESET, reset_ctrl);
- dsb();
-}
-
-static void realview_pb1176_fixup(struct tag *tags, char **from)
-{
- /*
- * RealView PB1176 only has 128MB of RAM mapped at 0.
- */
- memblock_add(0, SZ_128M);
-}
-
-static void __init realview_pb1176_init(void)
-{
- int i;
-
-#ifdef CONFIG_CACHE_L2X0
- /*
- * The PL220 needs to be manually configured as the hardware
- * doesn't report the correct sizes.
- * 128kB (16kB/way), 8-way associativity, event monitor and
- * parity enabled, ignore share bit, no force write allocate
- * Bits: .... ...0 0111 0011 0000 .... .... ....
- */
- l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff);
-#endif
-
- realview_flash_register(realview_pb1176_flash_resources,
- ARRAY_SIZE(realview_pb1176_flash_resources));
- platform_device_register(&pb1176_rom_device);
- realview_eth_register(NULL, realview_pb1176_smsc911x_resources);
- platform_device_register(&realview_i2c_device);
- realview_usb_register(realview_pb1176_isp1761_resources);
- platform_device_register(&pmu_device);
- platform_device_register(&char_lcd_device);
- platform_device_register(&realview_leds_device);
-
- for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
- struct amba_device *d = amba_devs[i];
- amba_device_register(d, &iomem_resource);
- }
-}
-
-MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
- /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
- .atag_offset = 0x100,
- .fixup = realview_pb1176_fixup,
- .map_io = realview_pb1176_map_io,
- .init_early = realview_init_early,
- .init_irq = gic_init_irq,
- .init_time = realview_pb1176_timer_init,
- .init_machine = realview_pb1176_init,
-#ifdef CONFIG_ZONE_DMA
- .dma_zone_size = SZ_256M,
-#endif
- .restart = realview_pb1176_restart,
-MACHINE_END
+++ /dev/null
-/*
- * linux/arch/arm/mach-realview/realview_pb11mp.c
- *
- * Copyright (C) 2008 ARM Limited
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/device.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/pl061.h>
-#include <linux/amba/mmci.h>
-#include <linux/amba/pl022.h>
-#include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
-#include <linux/platform_data/clk-realview.h>
-#include <linux/reboot.h>
-
-#include "hardware.h"
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <asm/pgtable.h>
-#include <asm/hardware/cache-l2x0.h>
-#include <asm/smp_twd.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-#include <asm/outercache.h>
-
-#include "board-pb11mp.h"
-#include "irqs-pb11mp.h"
-
-#include "core.h"
-
-static struct map_desc realview_pb11mp_io_desc[] __initdata = {
- {
- .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
- .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_CPU_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_CPU_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_DIST_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, { /* Maps the SCU, GIC CPU interface, TWD, GIC DIST */
- .virtual = IO_ADDRESS(REALVIEW_TC11MP_PRIV_MEM_BASE),
- .pfn = __phys_to_pfn(REALVIEW_TC11MP_PRIV_MEM_BASE),
- .length = REALVIEW_TC11MP_PRIV_MEM_SIZE,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
- .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER0_1_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER0_1_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER2_3_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER2_3_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_TC11MP_L220_BASE),
- .pfn = __phys_to_pfn(REALVIEW_TC11MP_L220_BASE),
- .length = SZ_8K,
- .type = MT_DEVICE,
- },
-#ifdef CONFIG_DEBUG_LL
- {
- .virtual = IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PB11MP_UART0_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- },
-#endif
-};
-
-static void __init realview_pb11mp_map_io(void)
-{
- iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc));
-}
-
-static struct pl061_platform_data gpio0_plat_data = {
- .gpio_base = 0,
-};
-
-static struct pl061_platform_data gpio1_plat_data = {
- .gpio_base = 8,
-};
-
-static struct pl061_platform_data gpio2_plat_data = {
- .gpio_base = 16,
-};
-
-static struct pl022_ssp_controller ssp0_plat_data = {
- .bus_id = 0,
- .enable_dma = 0,
- .num_chipselect = 1,
-};
-
-/*
- * RealView PB11MPCore AMBA devices
- */
-
-#define GPIO2_IRQ { IRQ_PB11MP_GPIO2 }
-#define GPIO3_IRQ { IRQ_PB11MP_GPIO3 }
-#define AACI_IRQ { IRQ_TC11MP_AACI }
-#define MMCI0_IRQ { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B }
-#define KMI0_IRQ { IRQ_TC11MP_KMI0 }
-#define KMI1_IRQ { IRQ_TC11MP_KMI1 }
-#define PB11MP_SMC_IRQ { }
-#define MPMC_IRQ { }
-#define PB11MP_CLCD_IRQ { IRQ_PB11MP_CLCD }
-#define DMAC_IRQ { IRQ_PB11MP_DMAC }
-#define SCTL_IRQ { }
-#define PB11MP_WATCHDOG_IRQ { IRQ_PB11MP_WATCHDOG }
-#define PB11MP_GPIO0_IRQ { IRQ_PB11MP_GPIO0 }
-#define GPIO1_IRQ { IRQ_PB11MP_GPIO1 }
-#define PB11MP_RTC_IRQ { IRQ_TC11MP_RTC }
-#define SCI_IRQ { IRQ_PB11MP_SCI }
-#define PB11MP_UART0_IRQ { IRQ_TC11MP_UART0 }
-#define PB11MP_UART1_IRQ { IRQ_TC11MP_UART1 }
-#define PB11MP_UART2_IRQ { IRQ_PB11MP_UART2 }
-#define PB11MP_UART3_IRQ { IRQ_PB11MP_UART3 }
-#define PB11MP_SSP_IRQ { IRQ_PB11MP_SSP }
-
-/* FPGA Primecells */
-APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
-APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
-APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
-APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
-APB_DEVICE(uart3, "fpga:uart3", PB11MP_UART3, NULL);
-
-/* DevChip Primecells */
-AHB_DEVICE(smc, "dev:smc", PB11MP_SMC, NULL);
-AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
-APB_DEVICE(wdog, "dev:wdog", PB11MP_WATCHDOG, NULL);
-APB_DEVICE(gpio0, "dev:gpio0", PB11MP_GPIO0, &gpio0_plat_data);
-APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
-APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
-APB_DEVICE(rtc, "dev:rtc", PB11MP_RTC, NULL);
-APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
-APB_DEVICE(uart0, "dev:uart0", PB11MP_UART0, NULL);
-APB_DEVICE(uart1, "dev:uart1", PB11MP_UART1, NULL);
-APB_DEVICE(uart2, "dev:uart2", PB11MP_UART2, NULL);
-APB_DEVICE(ssp0, "dev:ssp0", PB11MP_SSP, &ssp0_plat_data);
-
-/* Primecells on the NEC ISSP chip */
-AHB_DEVICE(clcd, "issp:clcd", PB11MP_CLCD, &clcd_plat_data);
-AHB_DEVICE(dmac, "issp:dmac", DMAC, NULL);
-
-static struct amba_device *amba_devs[] __initdata = {
- &dmac_device,
- &uart0_device,
- &uart1_device,
- &uart2_device,
- &uart3_device,
- &smc_device,
- &clcd_device,
- &sctl_device,
- &wdog_device,
- &gpio0_device,
- &gpio1_device,
- &gpio2_device,
- &rtc_device,
- &sci0_device,
- &ssp0_device,
- &aaci_device,
- &mmc0_device,
- &kmi0_device,
- &kmi1_device,
-};
-
-/*
- * RealView PB11MPCore platform devices
- */
-static struct resource realview_pb11mp_flash_resource[] = {
- [0] = {
- .start = REALVIEW_PB11MP_FLASH0_BASE,
- .end = REALVIEW_PB11MP_FLASH0_BASE + REALVIEW_PB11MP_FLASH0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = REALVIEW_PB11MP_FLASH1_BASE,
- .end = REALVIEW_PB11MP_FLASH1_BASE + REALVIEW_PB11MP_FLASH1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct resource realview_pb11mp_smsc911x_resources[] = {
- [0] = {
- .start = REALVIEW_PB11MP_ETH_BASE,
- .end = REALVIEW_PB11MP_ETH_BASE + SZ_64K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TC11MP_ETH,
- .end = IRQ_TC11MP_ETH,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct resource realview_pb11mp_isp1761_resources[] = {
- [0] = {
- .start = REALVIEW_PB11MP_USB_BASE,
- .end = REALVIEW_PB11MP_USB_BASE + SZ_128K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TC11MP_USB,
- .end = IRQ_TC11MP_USB,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct resource pmu_resources[] = {
- [0] = {
- .start = IRQ_TC11MP_PMU_CPU0,
- .end = IRQ_TC11MP_PMU_CPU0,
- .flags = IORESOURCE_IRQ,
- },
- [1] = {
- .start = IRQ_TC11MP_PMU_CPU1,
- .end = IRQ_TC11MP_PMU_CPU1,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .start = IRQ_TC11MP_PMU_CPU2,
- .end = IRQ_TC11MP_PMU_CPU2,
- .flags = IORESOURCE_IRQ,
- },
- [3] = {
- .start = IRQ_TC11MP_PMU_CPU3,
- .end = IRQ_TC11MP_PMU_CPU3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device pmu_device = {
- .name = "armv6-pmu",
- .id = -1,
- .num_resources = ARRAY_SIZE(pmu_resources),
- .resource = pmu_resources,
-};
-
-static void __init gic_init_irq(void)
-{
- unsigned int pldctrl;
-
- /* new irq mode with no DCC */
- writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
- pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
- pldctrl |= 2 << 22;
- writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
- writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
-
- /* ARM11MPCore test chip GIC, primary */
- gic_init(0, 29, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE),
- __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
-
- /* board GIC, secondary */
- gic_init(1, IRQ_PB11MP_GIC_START,
- __io_address(REALVIEW_PB11MP_GIC_DIST_BASE),
- __io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
- gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1);
-}
-
-#ifdef CONFIG_HAVE_ARM_TWD
-static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
- REALVIEW_TC11MP_TWD_BASE,
- IRQ_LOCALTIMER);
-
-static void __init realview_pb11mp_twd_init(void)
-{
- int err = twd_local_timer_register(&twd_local_timer);
- if (err)
- pr_err("twd_local_timer_register failed %d\n", err);
-}
-#else
-#define realview_pb11mp_twd_init() do {} while(0)
-#endif
-
-static void __init realview_pb11mp_timer_init(void)
-{
- timer0_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE);
- timer1_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE) + 0x20;
- timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE);
- timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20;
-
- realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
- realview_timer_init(IRQ_TC11MP_TIMER0_1);
- realview_pb11mp_twd_init();
-}
-
-static void realview_pb11mp_restart(enum reboot_mode mode, const char *cmd)
-{
- void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
- void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
-
- /*
- * To reset, we hit the on-board reset register
- * in the system FPGA
- */
- __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
- __raw_writel(0x0000, reset_ctrl);
- __raw_writel(0x0004, reset_ctrl);
- dsb();
-}
-
-static void __init realview_pb11mp_init(void)
-{
- int i;
-
-#ifdef CONFIG_CACHE_L2X0
- /*
- * The PL220 needs to be manually configured as the hardware
- * doesn't report the correct sizes.
- * 1MB (128KB/way), 8-way associativity, event monitor and
- * parity enabled, ignore share bit, no force write allocate
- * Bits: .... ...0 0111 1001 0000 .... .... ....
- */
- l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff);
- /*
- * due to a bug in the l220 cache controller, we must not call
- * the sync function. stub it out here instead!
- */
- outer_cache.sync = NULL;
-#endif
-
- realview_flash_register(realview_pb11mp_flash_resource,
- ARRAY_SIZE(realview_pb11mp_flash_resource));
- realview_eth_register(NULL, realview_pb11mp_smsc911x_resources);
- platform_device_register(&realview_i2c_device);
- platform_device_register(&realview_cf_device);
- platform_device_register(&realview_leds_device);
- realview_usb_register(realview_pb11mp_isp1761_resources);
- platform_device_register(&pmu_device);
-
- for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
- struct amba_device *d = amba_devs[i];
- amba_device_register(d, &iomem_resource);
- }
-}
-
-MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
- /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
- .atag_offset = 0x100,
- .smp = smp_ops(realview_smp_ops),
- .fixup = realview_fixup,
- .map_io = realview_pb11mp_map_io,
- .init_early = realview_init_early,
- .init_irq = gic_init_irq,
- .init_time = realview_pb11mp_timer_init,
- .init_machine = realview_pb11mp_init,
-#ifdef CONFIG_ZONE_DMA
- .dma_zone_size = SZ_256M,
-#endif
- .restart = realview_pb11mp_restart,
-MACHINE_END
+++ /dev/null
-/*
- * linux/arch/arm/mach-realview/realview_pba8.c
- *
- * Copyright (C) 2008 ARM Limited
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/device.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/pl061.h>
-#include <linux/amba/mmci.h>
-#include <linux/amba/pl022.h>
-#include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
-#include <linux/platform_data/clk-realview.h>
-#include <linux/reboot.h>
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <asm/pgtable.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-
-#include "hardware.h"
-#include "board-pba8.h"
-#include "irqs-pba8.h"
-
-#include "core.h"
-
-static struct map_desc realview_pba8_io_desc[] __initdata = {
- {
- .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
- .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_PBA8_GIC_CPU_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PBA8_GIC_CPU_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_PBA8_GIC_DIST_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PBA8_GIC_DIST_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
- .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_PBA8_TIMER0_1_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PBA8_TIMER0_1_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_PBA8_TIMER2_3_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PBA8_TIMER2_3_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- },
-#ifdef CONFIG_DEBUG_LL
- {
- .virtual = IO_ADDRESS(REALVIEW_PBA8_UART0_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PBA8_UART0_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- },
-#endif
-};
-
-static void __init realview_pba8_map_io(void)
-{
- iotable_init(realview_pba8_io_desc, ARRAY_SIZE(realview_pba8_io_desc));
-}
-
-static struct pl061_platform_data gpio0_plat_data = {
- .gpio_base = 0,
-};
-
-static struct pl061_platform_data gpio1_plat_data = {
- .gpio_base = 8,
-};
-
-static struct pl061_platform_data gpio2_plat_data = {
- .gpio_base = 16,
-};
-
-static struct pl022_ssp_controller ssp0_plat_data = {
- .bus_id = 0,
- .enable_dma = 0,
- .num_chipselect = 1,
-};
-
-/*
- * RealView PBA8Core AMBA devices
- */
-
-#define GPIO2_IRQ { IRQ_PBA8_GPIO2 }
-#define GPIO3_IRQ { IRQ_PBA8_GPIO3 }
-#define AACI_IRQ { IRQ_PBA8_AACI }
-#define MMCI0_IRQ { IRQ_PBA8_MMCI0A, IRQ_PBA8_MMCI0B }
-#define KMI0_IRQ { IRQ_PBA8_KMI0 }
-#define KMI1_IRQ { IRQ_PBA8_KMI1 }
-#define PBA8_SMC_IRQ { }
-#define MPMC_IRQ { }
-#define PBA8_CLCD_IRQ { IRQ_PBA8_CLCD }
-#define DMAC_IRQ { IRQ_PBA8_DMAC }
-#define SCTL_IRQ { }
-#define PBA8_WATCHDOG_IRQ { IRQ_PBA8_WATCHDOG }
-#define PBA8_GPIO0_IRQ { IRQ_PBA8_GPIO0 }
-#define GPIO1_IRQ { IRQ_PBA8_GPIO1 }
-#define PBA8_RTC_IRQ { IRQ_PBA8_RTC }
-#define SCI_IRQ { IRQ_PBA8_SCI }
-#define PBA8_UART0_IRQ { IRQ_PBA8_UART0 }
-#define PBA8_UART1_IRQ { IRQ_PBA8_UART1 }
-#define PBA8_UART2_IRQ { IRQ_PBA8_UART2 }
-#define PBA8_UART3_IRQ { IRQ_PBA8_UART3 }
-#define PBA8_SSP_IRQ { IRQ_PBA8_SSP }
-
-/* FPGA Primecells */
-APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
-APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
-APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
-APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
-APB_DEVICE(uart3, "fpga:uart3", PBA8_UART3, NULL);
-
-/* DevChip Primecells */
-AHB_DEVICE(smc, "dev:smc", PBA8_SMC, NULL);
-AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
-APB_DEVICE(wdog, "dev:wdog", PBA8_WATCHDOG, NULL);
-APB_DEVICE(gpio0, "dev:gpio0", PBA8_GPIO0, &gpio0_plat_data);
-APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
-APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
-APB_DEVICE(rtc, "dev:rtc", PBA8_RTC, NULL);
-APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
-APB_DEVICE(uart0, "dev:uart0", PBA8_UART0, NULL);
-APB_DEVICE(uart1, "dev:uart1", PBA8_UART1, NULL);
-APB_DEVICE(uart2, "dev:uart2", PBA8_UART2, NULL);
-APB_DEVICE(ssp0, "dev:ssp0", PBA8_SSP, &ssp0_plat_data);
-
-/* Primecells on the NEC ISSP chip */
-AHB_DEVICE(clcd, "issp:clcd", PBA8_CLCD, &clcd_plat_data);
-AHB_DEVICE(dmac, "issp:dmac", DMAC, NULL);
-
-static struct amba_device *amba_devs[] __initdata = {
- &dmac_device,
- &uart0_device,
- &uart1_device,
- &uart2_device,
- &uart3_device,
- &smc_device,
- &clcd_device,
- &sctl_device,
- &wdog_device,
- &gpio0_device,
- &gpio1_device,
- &gpio2_device,
- &rtc_device,
- &sci0_device,
- &ssp0_device,
- &aaci_device,
- &mmc0_device,
- &kmi0_device,
- &kmi1_device,
-};
-
-/*
- * RealView PB-A8 platform devices
- */
-static struct resource realview_pba8_flash_resource[] = {
- [0] = {
- .start = REALVIEW_PBA8_FLASH0_BASE,
- .end = REALVIEW_PBA8_FLASH0_BASE + REALVIEW_PBA8_FLASH0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = REALVIEW_PBA8_FLASH1_BASE,
- .end = REALVIEW_PBA8_FLASH1_BASE + REALVIEW_PBA8_FLASH1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct resource realview_pba8_smsc911x_resources[] = {
- [0] = {
- .start = REALVIEW_PBA8_ETH_BASE,
- .end = REALVIEW_PBA8_ETH_BASE + SZ_64K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PBA8_ETH,
- .end = IRQ_PBA8_ETH,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct resource realview_pba8_isp1761_resources[] = {
- [0] = {
- .start = REALVIEW_PBA8_USB_BASE,
- .end = REALVIEW_PBA8_USB_BASE + SZ_128K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PBA8_USB,
- .end = IRQ_PBA8_USB,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct resource pmu_resource = {
- .start = IRQ_PBA8_PMU,
- .end = IRQ_PBA8_PMU,
- .flags = IORESOURCE_IRQ,
-};
-
-static struct platform_device pmu_device = {
- .name = "armv7-pmu",
- .id = -1,
- .num_resources = 1,
- .resource = &pmu_resource,
-};
-
-static void __init gic_init_irq(void)
-{
- /* ARM PB-A8 on-board GIC */
- gic_init(0, IRQ_PBA8_GIC_START,
- __io_address(REALVIEW_PBA8_GIC_DIST_BASE),
- __io_address(REALVIEW_PBA8_GIC_CPU_BASE));
-}
-
-static void __init realview_pba8_timer_init(void)
-{
- timer0_va_base = __io_address(REALVIEW_PBA8_TIMER0_1_BASE);
- timer1_va_base = __io_address(REALVIEW_PBA8_TIMER0_1_BASE) + 0x20;
- timer2_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE);
- timer3_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE) + 0x20;
-
- realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
- realview_timer_init(IRQ_PBA8_TIMER0_1);
-}
-
-static void realview_pba8_restart(enum reboot_mode mode, const char *cmd)
-{
- void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
- void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
-
- /*
- * To reset, we hit the on-board reset register
- * in the system FPGA
- */
- __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
- __raw_writel(0x0000, reset_ctrl);
- __raw_writel(0x0004, reset_ctrl);
- dsb();
-}
-
-static void __init realview_pba8_init(void)
-{
- int i;
-
- realview_flash_register(realview_pba8_flash_resource,
- ARRAY_SIZE(realview_pba8_flash_resource));
- realview_eth_register(NULL, realview_pba8_smsc911x_resources);
- platform_device_register(&realview_i2c_device);
- platform_device_register(&realview_cf_device);
- platform_device_register(&realview_leds_device);
- realview_usb_register(realview_pba8_isp1761_resources);
- platform_device_register(&pmu_device);
-
- for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
- struct amba_device *d = amba_devs[i];
- amba_device_register(d, &iomem_resource);
- }
-}
-
-MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
- /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
- .atag_offset = 0x100,
- .fixup = realview_fixup,
- .map_io = realview_pba8_map_io,
- .init_early = realview_init_early,
- .init_irq = gic_init_irq,
- .init_time = realview_pba8_timer_init,
- .init_machine = realview_pba8_init,
-#ifdef CONFIG_ZONE_DMA
- .dma_zone_size = SZ_256M,
-#endif
- .restart = realview_pba8_restart,
-MACHINE_END
+++ /dev/null
-/*
- * arch/arm/mach-realview/realview_pbx.c
- *
- * Copyright (C) 2009 ARM Limited
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/device.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/pl061.h>
-#include <linux/amba/mmci.h>
-#include <linux/amba/pl022.h>
-#include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
-#include <linux/platform_data/clk-realview.h>
-#include <linux/reboot.h>
-#include <linux/memblock.h>
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <asm/smp_twd.h>
-#include <asm/pgtable.h>
-#include <asm/hardware/cache-l2x0.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-
-#include "hardware.h"
-#include "board-pbx.h"
-#include "irqs-pbx.h"
-
-#include "core.h"
-
-static struct map_desc realview_pbx_io_desc[] __initdata = {
- {
- .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
- .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_PBX_GIC_CPU_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PBX_GIC_CPU_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_PBX_GIC_DIST_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PBX_GIC_DIST_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
- .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_PBX_TIMER0_1_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PBX_TIMER0_1_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_PBX_TIMER2_3_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PBX_TIMER2_3_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- },
-#ifdef CONFIG_DEBUG_LL
- {
- .virtual = IO_ADDRESS(REALVIEW_PBX_UART0_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PBX_UART0_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- },
-#endif
-};
-
-static struct map_desc realview_local_io_desc[] __initdata = {
- {
- .virtual = IO_ADDRESS(REALVIEW_PBX_TILE_SCU_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PBX_TILE_SCU_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_PBX_TILE_GIC_DIST_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PBX_TILE_GIC_DIST_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_PBX_TILE_L220_BASE),
- .pfn = __phys_to_pfn(REALVIEW_PBX_TILE_L220_BASE),
- .length = SZ_8K,
- .type = MT_DEVICE,
- }
-};
-
-static void __init realview_pbx_map_io(void)
-{
- iotable_init(realview_pbx_io_desc, ARRAY_SIZE(realview_pbx_io_desc));
- if (core_tile_pbx11mp() || core_tile_pbxa9mp())
- iotable_init(realview_local_io_desc, ARRAY_SIZE(realview_local_io_desc));
-}
-
-static struct pl061_platform_data gpio0_plat_data = {
- .gpio_base = 0,
-};
-
-static struct pl061_platform_data gpio1_plat_data = {
- .gpio_base = 8,
-};
-
-static struct pl061_platform_data gpio2_plat_data = {
- .gpio_base = 16,
-};
-
-static struct pl022_ssp_controller ssp0_plat_data = {
- .bus_id = 0,
- .enable_dma = 0,
- .num_chipselect = 1,
-};
-
-/*
- * RealView PBXCore AMBA devices
- */
-
-#define GPIO2_IRQ { IRQ_PBX_GPIO2 }
-#define GPIO3_IRQ { IRQ_PBX_GPIO3 }
-#define AACI_IRQ { IRQ_PBX_AACI }
-#define MMCI0_IRQ { IRQ_PBX_MMCI0A, IRQ_PBX_MMCI0B }
-#define KMI0_IRQ { IRQ_PBX_KMI0 }
-#define KMI1_IRQ { IRQ_PBX_KMI1 }
-#define PBX_SMC_IRQ { }
-#define MPMC_IRQ { }
-#define PBX_CLCD_IRQ { IRQ_PBX_CLCD }
-#define DMAC_IRQ { IRQ_PBX_DMAC }
-#define SCTL_IRQ { }
-#define PBX_WATCHDOG_IRQ { IRQ_PBX_WATCHDOG }
-#define PBX_GPIO0_IRQ { IRQ_PBX_GPIO0 }
-#define GPIO1_IRQ { IRQ_PBX_GPIO1 }
-#define PBX_RTC_IRQ { IRQ_PBX_RTC }
-#define SCI_IRQ { IRQ_PBX_SCI }
-#define PBX_UART0_IRQ { IRQ_PBX_UART0 }
-#define PBX_UART1_IRQ { IRQ_PBX_UART1 }
-#define PBX_UART2_IRQ { IRQ_PBX_UART2 }
-#define PBX_UART3_IRQ { IRQ_PBX_UART3 }
-#define PBX_SSP_IRQ { IRQ_PBX_SSP }
-
-/* FPGA Primecells */
-APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
-APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
-APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
-APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
-APB_DEVICE(uart3, "fpga:uart3", PBX_UART3, NULL);
-
-/* DevChip Primecells */
-AHB_DEVICE(smc, "dev:smc", PBX_SMC, NULL);
-AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
-APB_DEVICE(wdog, "dev:wdog", PBX_WATCHDOG, NULL);
-APB_DEVICE(gpio0, "dev:gpio0", PBX_GPIO0, &gpio0_plat_data);
-APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
-APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
-APB_DEVICE(rtc, "dev:rtc", PBX_RTC, NULL);
-APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
-APB_DEVICE(uart0, "dev:uart0", PBX_UART0, NULL);
-APB_DEVICE(uart1, "dev:uart1", PBX_UART1, NULL);
-APB_DEVICE(uart2, "dev:uart2", PBX_UART2, NULL);
-APB_DEVICE(ssp0, "dev:ssp0", PBX_SSP, &ssp0_plat_data);
-
-/* Primecells on the NEC ISSP chip */
-AHB_DEVICE(clcd, "issp:clcd", PBX_CLCD, &clcd_plat_data);
-AHB_DEVICE(dmac, "issp:dmac", DMAC, NULL);
-
-static struct amba_device *amba_devs[] __initdata = {
- &dmac_device,
- &uart0_device,
- &uart1_device,
- &uart2_device,
- &uart3_device,
- &smc_device,
- &clcd_device,
- &sctl_device,
- &wdog_device,
- &gpio0_device,
- &gpio1_device,
- &gpio2_device,
- &rtc_device,
- &sci0_device,
- &ssp0_device,
- &aaci_device,
- &mmc0_device,
- &kmi0_device,
- &kmi1_device,
-};
-
-/*
- * RealView PB-X platform devices
- */
-static struct resource realview_pbx_flash_resources[] = {
- [0] = {
- .start = REALVIEW_PBX_FLASH0_BASE,
- .end = REALVIEW_PBX_FLASH0_BASE + REALVIEW_PBX_FLASH0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = REALVIEW_PBX_FLASH1_BASE,
- .end = REALVIEW_PBX_FLASH1_BASE + REALVIEW_PBX_FLASH1_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct resource realview_pbx_smsc911x_resources[] = {
- [0] = {
- .start = REALVIEW_PBX_ETH_BASE,
- .end = REALVIEW_PBX_ETH_BASE + SZ_64K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PBX_ETH,
- .end = IRQ_PBX_ETH,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct resource realview_pbx_isp1761_resources[] = {
- [0] = {
- .start = REALVIEW_PBX_USB_BASE,
- .end = REALVIEW_PBX_USB_BASE + SZ_128K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PBX_USB,
- .end = IRQ_PBX_USB,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-#ifdef CONFIG_CACHE_L2X0
-static struct resource pmu_resources[] = {
- [0] = {
- .start = IRQ_PBX_PMU_CPU0,
- .end = IRQ_PBX_PMU_CPU0,
- .flags = IORESOURCE_IRQ,
- },
- [1] = {
- .start = IRQ_PBX_PMU_CPU1,
- .end = IRQ_PBX_PMU_CPU1,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .start = IRQ_PBX_PMU_CPU2,
- .end = IRQ_PBX_PMU_CPU2,
- .flags = IORESOURCE_IRQ,
- },
- [3] = {
- .start = IRQ_PBX_PMU_CPU3,
- .end = IRQ_PBX_PMU_CPU3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device pmu_device = {
- .name = "armv7-pmu",
- .id = -1,
- .num_resources = ARRAY_SIZE(pmu_resources),
- .resource = pmu_resources,
-};
-#endif
-
-static void __init gic_init_irq(void)
-{
- /* ARM PBX on-board GIC */
- if (core_tile_pbx11mp() || core_tile_pbxa9mp()) {
- gic_init(0, 29, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE),
- __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE));
- } else {
- gic_init(0, IRQ_PBX_GIC_START,
- __io_address(REALVIEW_PBX_GIC_DIST_BASE),
- __io_address(REALVIEW_PBX_GIC_CPU_BASE));
- }
-}
-
-#ifdef CONFIG_HAVE_ARM_TWD
-static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
- REALVIEW_PBX_TILE_TWD_BASE,
- IRQ_LOCALTIMER);
-
-static void __init realview_pbx_twd_init(void)
-{
- int err = twd_local_timer_register(&twd_local_timer);
- if (err)
- pr_err("twd_local_timer_register failed %d\n", err);
-}
-#else
-#define realview_pbx_twd_init() do { } while(0)
-#endif
-
-static void __init realview_pbx_timer_init(void)
-{
- timer0_va_base = __io_address(REALVIEW_PBX_TIMER0_1_BASE);
- timer1_va_base = __io_address(REALVIEW_PBX_TIMER0_1_BASE) + 0x20;
- timer2_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE);
- timer3_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE) + 0x20;
-
- realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
- realview_timer_init(IRQ_PBX_TIMER0_1);
- realview_pbx_twd_init();
-}
-
-static void realview_pbx_fixup(struct tag *tags, char **from)
-{
-#ifdef CONFIG_SPARSEMEM
- /*
- * Memory configuration with SPARSEMEM enabled on RealView PBX (see
- * asm/mach/memory.h for more information).
- */
-
- memblock_add(0, SZ_256M);
- memblock_add(0x20000000, SZ_512M);
- memblock_add(0x80000000, SZ_256M);
-#else
- realview_fixup(tags, from);
-#endif
-}
-
-static void realview_pbx_restart(enum reboot_mode mode, const char *cmd)
-{
- void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
- void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
-
- /*
- * To reset, we hit the on-board reset register
- * in the system FPGA
- */
- __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
- __raw_writel(0x00F0, reset_ctrl);
- __raw_writel(0x00F4, reset_ctrl);
- dsb();
-}
-
-static void __init realview_pbx_init(void)
-{
- int i;
-
-#ifdef CONFIG_CACHE_L2X0
- if (core_tile_pbxa9mp()) {
- void __iomem *l2x0_base =
- __io_address(REALVIEW_PBX_TILE_L220_BASE);
-
- /* set RAM latencies to 1 cycle for eASIC */
- writel(0, l2x0_base + L310_TAG_LATENCY_CTRL);
- writel(0, l2x0_base + L310_DATA_LATENCY_CTRL);
-
- /* 16KB way size, 8-way associativity, parity disabled
- * Bits: .. 0 0 0 0 1 00 1 0 1 001 0 000 0 .... .... .... */
- l2x0_init(l2x0_base, 0x02520000, 0xc0000fff);
- platform_device_register(&pmu_device);
- }
-#endif
-
- realview_flash_register(realview_pbx_flash_resources,
- ARRAY_SIZE(realview_pbx_flash_resources));
- realview_eth_register(NULL, realview_pbx_smsc911x_resources);
- platform_device_register(&realview_i2c_device);
- platform_device_register(&realview_cf_device);
- platform_device_register(&realview_leds_device);
- realview_usb_register(realview_pbx_isp1761_resources);
-
- for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
- struct amba_device *d = amba_devs[i];
- amba_device_register(d, &iomem_resource);
- }
-}
-
-MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
- /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
- .atag_offset = 0x100,
- .smp = smp_ops(realview_smp_ops),
- .fixup = realview_pbx_fixup,
- .map_io = realview_pbx_map_io,
- .init_early = realview_init_early,
- .init_irq = gic_init_irq,
- .init_time = realview_pbx_timer_init,
- .init_machine = realview_pbx_init,
-#ifdef CONFIG_ZONE_DMA
- .dma_zone_size = SZ_256M,
-#endif
- .restart = realview_pbx_restart,
-MACHINE_END
select PM_GENERIC_DOMAINS
select RENESAS_IRQC
select SYS_SUPPORTS_SH_CMT
- select PCI_DOMAINS if PCI
config ARCH_RMOBILE
bool
select HAVE_ARM_TWD if SMP
select PINCTRL
select MFD_SYSCON
- select MIGHT_HAVE_PCI
help
Supports for ARM's SPEAR13XX family
select CPU_ARM926T
select ICST
select MFD_SYSCON
- select MIGHT_HAVE_PCI
select PLAT_VERSATILE
select POWER_RESET
select POWER_RESET_VERSATILE
#define CCM_PCDR (ccm + 0x0020)
#define SCM_GCCR (ccm + 0x0810)
-static void __init _mx1_clocks_init(unsigned long fref)
+static void __init mx1_clocks_init_dt(struct device_node *np)
{
+ ccm = of_iomap(np, 0);
+ BUG_ON(!ccm);
+
clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
- clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref);
+ clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", 32768);
clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000);
clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
imx_check_clocks(clk, ARRAY_SIZE(clk));
-}
-
-int __init mx1_clocks_init(unsigned long fref)
-{
- ccm = ioremap(MX1_CCM_BASE_ADDR, SZ_4K);
- BUG_ON(!ccm);
-
- _mx1_clocks_init(fref);
-
- clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx-gpt.0");
- clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx-gpt.0");
- clk_register_clkdev(clk[IMX1_CLK_DMA_GATE], "ahb", "imx1-dma");
- clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-dma");
- clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.0");
- clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.0");
- clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.1");
- clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.1");
- clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.2");
- clk_register_clkdev(clk[IMX1_CLK_UART3_GATE], "ipg", "imx1-uart.2");
- clk_register_clkdev(clk[IMX1_CLK_HCLK], NULL, "imx1-i2c.0");
- clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.0");
- clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.0");
- clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.1");
- clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.1");
- clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-fb.0");
- clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-fb.0");
- clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ahb", "imx1-fb.0");
-
- mxc_timer_init(MX1_TIM1_BASE_ADDR, MX1_TIM1_INT, GPT_TYPE_IMX1);
-
- return 0;
-}
-
-static void __init mx1_clocks_init_dt(struct device_node *np)
-{
- ccm = of_iomap(np, 0);
- BUG_ON(!ccm);
-
- _mx1_clocks_init(32768);
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o
obj-$(CONFIG_ARM_GIC_PM) += irq-gic-pm.o
-obj-$(CONFIG_REALVIEW_DT) += irq-gic-realview.o
+obj-$(CONFIG_ARCH_REALVIEW) += irq-gic-realview.o
obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o
obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o
obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-pci-msi.o irq-gic-v3-its-platform-msi.o
bool "Support ARM Versatile physmap OF"
depends on MTD_PHYSMAP_OF
depends on MFD_SYSCON
- default y if (ARCH_INTEGRATOR || ARCH_VERSATILE || REALVIEW_DT)
+ default y if (ARCH_INTEGRATOR || ARCH_VERSATILE || ARCH_REALVIEW)
help
This provides some extra DT physmap parsing for the ARM Versatile
platforms, basically to add a VPP (write protection) callback so
projects / cascardo / linux.git / commitdiff