ARM: LPAE: factor out T1SZ and TTBR1 computations

This patch moves the TTBR1 offset calculation and the T1SZ calculation out
of the TTB setup assembly code.  This should not affect functionality in
any way, but improves code readability as well as readability of subsequent
patches in this series.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Subash Patel <subash.rp@samsung.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
index 18f5cef..c6c6e6d 100644 (file)
--- a/arch/arm/include/asm/pgtable-3level-hwdef.h
+++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
@@ -79,4 +79,24 @@
 #define PHYS_MASK_SHIFT                (40)
 #define PHYS_MASK              ((1ULL << PHYS_MASK_SHIFT) - 1)
 
+/*
+ * TTBR0/TTBR1 split (PAGE_OFFSET):
+ *   0x40000000: T0SZ = 2, T1SZ = 0 (not used)
+ *   0x80000000: T0SZ = 0, T1SZ = 1
+ *   0xc0000000: T0SZ = 0, T1SZ = 2
+ *
+ * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
+ * booting secondary CPUs would end up using TTBR1 for the identity
+ * mapping set up in TTBR0.
+ */
+#if defined CONFIG_VMSPLIT_2G
+#define TTBR1_OFFSET   16                      /* skip two L1 entries */
+#elif defined CONFIG_VMSPLIT_3G
+#define TTBR1_OFFSET   (4096 * (1 + 3))        /* only L2, skip pgd + 3*pmd */
+#else
+#define TTBR1_OFFSET   0
+#endif
+
+#define TTBR1_SIZE     (((PAGE_OFFSET >> 30) - 1) << 16)
+
 #endif

diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 995857d..58ab747 100644 (file)
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -114,7 +114,7 @@ ENDPROC(cpu_v7_set_pte_ext)
         */
        .macro  v7_ttb_setup, zero, ttbr0, ttbr1, tmp
        ldr     \tmp, =swapper_pg_dir           @ swapper_pg_dir virtual address
-       cmp     \ttbr1, \tmp                    @ PHYS_OFFSET > PAGE_OFFSET? (branch below)
+       cmp     \ttbr1, \tmp                    @ PHYS_OFFSET > PAGE_OFFSET?
        mrc     p15, 0, \tmp, c2, c0, 2         @ TTB control register
        orr     \tmp, \tmp, #TTB_EAE
        ALT_SMP(orr     \tmp, \tmp, #TTB_FLAGS_SMP)
@@ -122,27 +122,14 @@ ENDPROC(cpu_v7_set_pte_ext)
        ALT_SMP(orr     \tmp, \tmp, #TTB_FLAGS_SMP << 16)
        ALT_UP(orr      \tmp, \tmp, #TTB_FLAGS_UP << 16)
        /*
-        * TTBR0/TTBR1 split (PAGE_OFFSET):
-        *   0x40000000: T0SZ = 2, T1SZ = 0 (not used)
-        *   0x80000000: T0SZ = 0, T1SZ = 1
-        *   0xc0000000: T0SZ = 0, T1SZ = 2
-        *
-        * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
-        * booting secondary CPUs would end up using TTBR1 for the identity
-        * mapping set up in TTBR0.
+        * Only use split TTBRs if PHYS_OFFSET <= PAGE_OFFSET (cmp above),
+        * otherwise booting secondary CPUs would end up using TTBR1 for the
+        * identity mapping set up in TTBR0.
         */
-       bhi     9001f                           @ PHYS_OFFSET > PAGE_OFFSET?
-       orr     \tmp, \tmp, #(((PAGE_OFFSET >> 30) - 1) << 16) @ TTBCR.T1SZ
-#if defined CONFIG_VMSPLIT_2G
-       /* PAGE_OFFSET == 0x80000000, T1SZ == 1 */
-       add     \ttbr1, \ttbr1, #1 << 4         @ skip two L1 entries
-#elif defined CONFIG_VMSPLIT_3G
-       /* PAGE_OFFSET == 0xc0000000, T1SZ == 2 */
-       add     \ttbr1, \ttbr1, #4096 * (1 + 3) @ only L2 used, skip pgd+3*pmd
-#endif
-       /* CONFIG_VMSPLIT_1G does not need TTBR1 adjustment */
-9001:  mcr     p15, 0, \tmp, c2, c0, 2         @ TTB control register
-       mcrr    p15, 1, \ttbr1, \zero, c2       @ load TTBR1
+       orrls   \tmp, \tmp, #TTBR1_SIZE                         @ TTBCR.T1SZ
+       mcr     p15, 0, \tmp, c2, c0, 2                         @ TTBCR
+       addls   \ttbr1, \ttbr1, #TTBR1_OFFSET
+       mcrr    p15, 1, \ttbr1, \zero, c2                       @ load TTBR1
        .endm
 
        __CPUINIT