ARM: document and update UNCACHEABLE_ADDR definitions

Document the UNCACHEABLE_ADDR definitions for footbridge and SA1100
so that we know where they're located and/or what they're accessing.
Change RiscPC to calculate the UNCACHEABLE_ADDR value from FLUSH_BASE
as that's where we locate that.

UNCACHEABLE_ADDR is used to perform an uncached access (ARMv4
terminology) necessary to force a CPU clock-switch to the memory-
speed clock, as required for entering WFI.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

diff --git a/arch/arm/mach-footbridge/include/mach/hardware.h b/arch/arm/mach-footbridge/include/mach/hardware.h
index 02f6d7a..20d5ad7 100644 (file)
--- a/arch/arm/mach-footbridge/include/mach/hardware.h
+++ b/arch/arm/mach-footbridge/include/mach/hardware.h
@@ -59,7 +59,7 @@
 #define XBUS_SWITCH_J17_11     ((*XBUS_SWITCH) & (1 << 5))
 #define XBUS_SWITCH_J17_9      ((*XBUS_SWITCH) & (1 << 6))
 
-#define UNCACHEABLE_ADDR       (ARMCSR_BASE + 0x108)
+#define UNCACHEABLE_ADDR       (ARMCSR_BASE + 0x108)   /* CSR_ROMBASEMASK */
 
 
 /* PIC irq control */

diff --git a/arch/arm/mach-rpc/include/mach/hardware.h b/arch/arm/mach-rpc/include/mach/hardware.h
index 257166b..aa79fa4 100644 (file)
--- a/arch/arm/mach-rpc/include/mach/hardware.h
+++ b/arch/arm/mach-rpc/include/mach/hardware.h
@@ -40,7 +40,7 @@
 #define SCREEN_END             0xdfc00000
 #define SCREEN_BASE            0xdf800000
 
-#define UNCACHEABLE_ADDR       0xdf010000
+#define UNCACHEABLE_ADDR       (FLUSH_BASE + 0x10000)
 
 /*
  * IO Addresses

diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
index 55c85ce..d944fd7 100644 (file)
--- a/arch/arm/mach-sa1100/include/mach/hardware.h
+++ b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -13,7 +13,7 @@
 #define __ASM_ARCH_HARDWARE_H
 
 
-#define UNCACHEABLE_ADDR       0xfa050000
+#define UNCACHEABLE_ADDR       0xfa050000      /* ICIP */
 
 
 /*