clk: divider: add CLK_DIVIDER_HIWORD_MASK flag

In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the
paradigm of reading-changing-writing the register contents.
Instead they use a hiword mask to indicate the changed bits.

When b01 should be set as setting divider, it also needs to indicate
the change by setting hiword mask (b11 << 16).

The patch adds divider flag for this usage.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 6024e60..6d55eb2 100644 (file)
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -227,8 +227,12 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
        if (divider->lock)
                spin_lock_irqsave(divider->lock, flags);
 
-       val = readl(divider->reg);
-       val &= ~(div_mask(divider) << divider->shift);
+       if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
+               val = div_mask(divider) << (divider->shift + 16);
+       } else {
+               val = readl(divider->reg);
+               val &= ~(div_mask(divider) << divider->shift);
+       }
        val |= value << divider->shift;
        writel(val, divider->reg);
 
@@ -255,6 +259,13 @@ static struct clk *_register_divider(struct device *dev, const char *name,
        struct clk *clk;
        struct clk_init_data init;
 
+       if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
+               if (width + shift > 16) {
+                       pr_warn("divider value exceeds LOWORD field\n");
+                       return ERR_PTR(-EINVAL);
+               }
+       }
+
        /* allocate the divider */
        div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
        if (!div) {

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 37ad979..d77f126 100644 (file)
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -257,6 +257,10 @@ struct clk_div_table {
  *     Some hardware implementations gracefully handle this case and allow a
  *     zero divisor by not modifying their input clock
  *     (divide by one / bypass).
+ * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
+ *   of this register, and mask of divider bits are in higher 16-bit of this
+ *   register.  While setting the divider bits, higher 16-bit should also be
+ *   updated to indicate changing divider bits.
  */
 struct clk_divider {
        struct clk_hw   hw;
@@ -271,6 +275,7 @@ struct clk_divider {
 #define CLK_DIVIDER_ONE_BASED          BIT(0)
 #define CLK_DIVIDER_POWER_OF_TWO       BIT(1)
 #define CLK_DIVIDER_ALLOW_ZERO         BIT(2)
+#define CLK_DIVIDER_HIWORD_MASK                BIT(3)
 
 extern const struct clk_ops clk_divider_ops;
 struct clk *clk_register_divider(struct device *dev, const char *name,