ARM: dts: rockchip: add watchdog node
authorHeiko Stuebner <heiko@sntech.de>
Wed, 30 Jul 2014 08:16:17 +0000 (10:16 +0200)
committerHeiko Stuebner <heiko@sntech.de>
Wed, 30 Jul 2014 10:14:44 +0000 (12:14 +0200)
This adds the Designware compatible watchdog found on RK3xxx Cortex-A9 SoCs.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm/boot/dts/rk3066a-bqcurie2.dts
arch/arm/boot/dts/rk3066a.dtsi
arch/arm/boot/dts/rk3188-radxarock.dts
arch/arm/boot/dts/rk3188.dtsi
arch/arm/boot/dts/rk3xxx.dtsi

index 8b479f7..042f821 100644 (file)
 &uart3 {
        status = "okay";
 };
+
+&wdt {
+       status = "okay";
+};
index 9c34da4..879a818 100644 (file)
        pinctrl-names = "default";
        pinctrl-0 = <&uart3_xfer>;
 };
+
+&wdt {
+       compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
+};
index 4195f5a..171b610 100644 (file)
 &uart3 {
        status = "okay";
 };
+
+&wdt {
+       status = "okay";
+};
index 27215e0..ee801a9 100644 (file)
        pinctrl-names = "default";
        pinctrl-0 = <&uart3_xfer>;
 };
+
+&wdt {
+       compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
+};
index c6f0561..8caf85d 100644 (file)
                status = "disabled";
        };
 
+       wdt: watchdog@2004c000 {
+               compatible = "snps,dw-wdt";
+               reg = <0x2004c000 0x100>;
+               clocks = <&cru PCLK_WDT>;
+               interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
        pwm2: pwm@20050020 {
                compatible = "rockchip,rk2928-pwm";
                reg = <0x20050020 0x10>;