drm/i915: run hsw_disable_pc8() later on resume

We want to run intel_uncore_early_sanitize() before we touch any
registers, because on BDW, when we resume, the FPGA_DBG_RM_NOCLAIM bit
is set, so we need to clear it - through intel_uncore_early_sanitize()
- before we do anything else. With the current code, we don't clear
the bit before our first register access, so we print a WARN
complaining about an unclaimed register error.

v1: Was called "drm/i915: run intel_uncore_early_sanitize earlier on
resume"
v2: Was called "drm/i915: run intel_uncore_early_sanitize earlier on
resume on non-VLV"
v3: This one, on top of the intel_resume_prepare() rework.
v4: Rebase.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 33b6fc4..0c7cf48 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -760,14 +760,16 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
        pci_set_master(dev->pdev);
 
-       if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
-               hsw_disable_pc8(dev_priv);
-       else if (IS_VALLEYVIEW(dev_priv))
+       if (IS_VALLEYVIEW(dev_priv))
                ret = vlv_resume_prepare(dev_priv, false);
        if (ret)
                DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
 
        intel_uncore_early_sanitize(dev, true);
+
+       if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+               hsw_disable_pc8(dev_priv);
+
        intel_uncore_sanitize(dev);
        intel_power_domains_init_hw(dev_priv);