Merge branch 'drm-intel-next' of git://people.freedesktop.org/~danvet/drm-intel into...

Daniel Vetter wrote
First pull request for 3.5-next, slightly large than usual because new
things kept coming in since the last pull for 3.4.
Highlights:
- first batch of hw enablement for vlv (Jesse et al) and hsw (Eugeni). pci
 ids are not yet added, and there's still quite a few patches to merge
 (mostly modesetting). To make QA easier I've decided to merge this stuff
 in pieces.
- loads of cleanups and prep patches spurred by the above. Especially vlv
 is a real frankenstein chip, but also hsw is stretching our driver's
 code design. Expect more to come in this area for 3.5.
- more gmbus fixes, cleanups and improvements by Daniel Kurtz. Again,
 there are more patches needed (and some already queued up), but I wanted
 to split this a bit for better testing.
- pwrite/pread rework and retuning. This series has been in the works for
 a few months already and a lot of i-g-t tests have been created for it.
 Now it's finally ready to be merged.  Note that one patch in this series
 touches include/pagemap.h, that patch is acked-by akpm.
- reduce mappable pressure and relocation throughput improvements from
 Chris.
- mmap offset exhaustion mitigation by Chris Wilson.
- a start at figuring out which codepaths in our messy dri1/ums+gem/kms
 driver we actually need to support by bailing out of unsupported case.
 The driver now refuses to load without kms on gen6+ and disallows a few
 ioctls that userspace never used in certain cases. More of this will
 definitely come.
- More decoupling of global gtt and ppgtt.
- Improved dual-link lvds detection by Takashi Iwai.
- Shut up the compiler + plus fix the fallout (Ben)
- Inverted panel brightness handling (mostly Acer manages to break things
 in this way).
- Small fixlets and adjustements and some minor things to help debugging.

Regression-wise QA reported quite a few issues on ivb, but all of them
turned out to be hw stability issues which are already fixed in
drm-intel-fixes (QA runs the nightly regression tests on -next alone,
without -fixes automatically merged in). There's still one issue open on
snb, it looks like occlusion query writes are not quite as cache coherent
as we've expected. With some of the pwrite adjustements we can now
reliably hit this. Kernel workaround for it is in the works."

* 'drm-intel-next' of git://people.freedesktop.org/~danvet/drm-intel: (101 commits)
  drm/i915: VCS is not the last ring
  drm/i915: Add a dual link lvds quirk for MacBook Pro 8,2
  drm/i915: make quirks more verbose
  drm/i915: dump the DMA fetch addr register on pre-gen6
  drm/i915/sdvo: Include YRPB as an additional TV output type
  drm/i915: disallow gem init ioctl on ilk
  drm/i915: refuse to load on gen6+ without kms
  drm/i915: extract gt interrupt handler
  drm/i915: use render gen to switch ring irq functions
  drm/i915: rip out old HWSTAM missed irq WA for vlv
  drm/i915: open code gen6+ ring irqs
  drm/i915: ring irq cleanups
  drm/i915: add SFUSE_STRAP registers for digital port detection
  drm/i915: add WM_LINETIME registers
  drm/i915: add WRPLL clocks
  drm/i915: add LCPLL control registers
  drm/i915: add SSC offsets for SBI access
  drm/i915: add port clock selection support for HSW
  drm/i915: add S PLL control
  drm/i915: add PIXCLK_GATE register
  ...

Conflicts:
	drivers/char/agp/intel-agp.h
	drivers/char/agp/intel-gtt.c
	drivers/gpu/drm/i915/i915_debugfs.c

diff --cc Documentation/kernel-parameters.txt
Simple merge

diff --cc drivers/char/agp/intel-agp.h
index 7ea18a5,0b07101..c009175
--- 1/drivers/char/agp/intel-agp.h
--- 2/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@@ -234,7 -235,19 +235,20 @@@
  #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG                0x0166
  #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB            0x0158  /* Server */
  #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG                0x015A
 +#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG                0x016A
+ #define PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB             0x0F00 /* VLV1 */
+ #define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG             0x0F30
+ #define PCI_DEVICE_ID_INTEL_HASWELL_HB                                0x0400 /* Desktop */
+ #define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG          0x0402
+ #define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG          0x0412
+ #define PCI_DEVICE_ID_INTEL_HASWELL_M_HB                      0x0404 /* Mobile */
+ #define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG          0x0406
+ #define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG          0x0416
+ #define PCI_DEVICE_ID_INTEL_HASWELL_S_HB                      0x0408 /* Server */
+ #define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG          0x040a
+ #define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG          0x041a
+ #define PCI_DEVICE_ID_INTEL_HASWELL_SDV               0x0c16 /* SDV */
+ #define PCI_DEVICE_ID_INTEL_HASWELL_E_HB                      0x0c04
  
  int intel_gmch_probe(struct pci_dev *pdev,
                               struct agp_bridge_data *bridge);

diff --cc drivers/char/agp/intel-gtt.c
index 7f025fb,7e223a2..1237e75
--- 1/drivers/char/agp/intel-gtt.c
--- 2/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@@ -1458,8 -1486,22 +1485,24 @@@ static const struct intel_gtt_driver_de
            "Ivybridge", &sandybridge_gtt_driver },
        { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
            "Ivybridge", &sandybridge_gtt_driver },
 +      { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG,
 +          "Ivybridge", &sandybridge_gtt_driver },
+       { PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG,
+           "ValleyView", &valleyview_gtt_driver },
+       { PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG,
+           "Haswell", &sandybridge_gtt_driver },
+       { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,
+           "Haswell", &sandybridge_gtt_driver },
+       { PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,
+           "Haswell", &sandybridge_gtt_driver },
+       { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,
+           "Haswell", &sandybridge_gtt_driver },
+       { PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,
+           "Haswell", &sandybridge_gtt_driver },
+       { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,
+           "Haswell", &sandybridge_gtt_driver },
+       { PCI_DEVICE_ID_INTEL_HASWELL_SDV,
+           "Haswell", &sandybridge_gtt_driver },
        { 0, NULL, NULL }
  };
  

diff --cc drivers/gpu/drm/drm_cache.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_debugfs.c
index b505b70,7e00995..967fb92
--- 1/drivers/gpu/drm/i915/i915_debugfs.c
--- 2/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@@ -1502,6 -1541,61 +1541,53 @@@ static int i915_ppgtt_info(struct seq_f
        return 0;
  }
  
 -static int
 -i915_debugfs_common_open(struct inode *inode,
 -                       struct file *filp)
 -{
 -      filp->private_data = inode->i_private;
 -      return 0;
 -}
 -
+ static int i915_dpio_info(struct seq_file *m, void *data)
+ {
+       struct drm_info_node *node = (struct drm_info_node *) m->private;
+       struct drm_device *dev = node->minor->dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       int ret;
+ 
+ 
+       if (!IS_VALLEYVIEW(dev)) {
+               seq_printf(m, "unsupported\n");
+               return 0;
+       }
+ 
+       ret = mutex_lock_interruptible(&dev->mode_config.mutex);
+       if (ret)
+               return ret;
+ 
+       seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
+ 
+       seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
+                  intel_dpio_read(dev_priv, _DPIO_DIV_A));
+       seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
+                  intel_dpio_read(dev_priv, _DPIO_DIV_B));
+ 
+       seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
+                  intel_dpio_read(dev_priv, _DPIO_REFSFR_A));
+       seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
+                  intel_dpio_read(dev_priv, _DPIO_REFSFR_B));
+ 
+       seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
+                  intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
+       seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
+                  intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
+ 
+       seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
+                  intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
+       seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
+                  intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
+ 
+       seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
+                  intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
+ 
+       mutex_unlock(&dev->mode_config.mutex);
+ 
+       return 0;
+ }
+ 
  static ssize_t
  i915_wedged_read(struct file *filp,
                 char __user *ubuf,

diff --cc drivers/gpu/drm/i915/i915_dma.c
index 785f67f,4636391..652f43f
--- 1/drivers/gpu/drm/i915/i915_dma.c
--- 2/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@@ -1216,16 -1207,12 +1222,14 @@@ static int i915_load_gem_init(struct dr
                /* PPGTT pdes are stolen from global gtt ptes, so shrink the
                 * aperture accordingly when using aliasing ppgtt. */
                gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
-               /* For paranoia keep the guard page in between. */
-               gtt_size -= PAGE_SIZE;
  
-               i915_gem_do_init(dev, 0, mappable_size, gtt_size);
+               i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
  
                ret = i915_gem_init_aliasing_ppgtt(dev);
 -              if (ret)
 +              if (ret) {
 +                      mutex_unlock(&dev->struct_mutex);
                        return ret;
 +              }
        } else {
                /* Let GEM Manage all of the aperture.
                 *

diff --cc drivers/gpu/drm/i915/i915_drv.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_drv.h
Simple merge

diff --cc drivers/gpu/drm/i915/i915_gem.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_gem_execbuffer.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_gem_gtt.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_reg.h
Simple merge

diff --cc drivers/gpu/drm/i915/intel_bios.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_display.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_drv.h
Simple merge

diff --cc drivers/gpu/drm/i915/intel_lvds.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_modes.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_ringbuffer.c
index e25581a,465a7da..dfdb613
--- 1/drivers/gpu/drm/i915/intel_ringbuffer.c
--- 2/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@@ -287,12 -287,12 +287,12 @@@ static int init_ring_common(struct inte
  
        I915_WRITE_CTL(ring,
                        ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 -                      | RING_REPORT_64K | RING_VALID);
 +                      | RING_VALID);
  
        /* If the head is still not zero, the ring is dead */
-       if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
-           I915_READ_START(ring) != obj->gtt_offset ||
-           (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
+       if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
+                    I915_READ_START(ring) == obj->gtt_offset &&
+                    (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
                DRM_ERROR("%s initialization failed "
                                "ctl %08x head %08x tail %08x start %08x\n",
                                ring->name,

diff --cc include/drm/drmP.h
Simple merge