drm/i915: add missing error capturing of the PIPESTAT reg

While checking the error capture path I noticed that we lacked the
power domain-on check for PIPESTAT so fix this by moving that to where
the rest of pipe registers are captured.

The move also revealed that we actually don't include this register in
the error report, so fix that too.

v2:
- patch introduced in v2 of the patchset
v3:
- add back !HAS_PCH_SPLIT check (Ville)
[ Ignore my previous comment about the gen<=5 || vlv check, I realized
  that it's the same as !HAS_PCH_SPLIT. ]

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 272aa7a..1c615cb 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -325,7 +325,6 @@ struct drm_i915_error_state {
        u32 gab_ctl;
        u32 gfx_mode;
        u32 extra_instdone[I915_NUM_INSTDONE_REG];
-       u32 pipestat[I915_MAX_PIPES];
        u64 fence[I915_MAX_NUM_FENCES];
        struct intel_overlay_error_state *overlay;
        struct intel_display_error_state *display;

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 667bb29..51e9978 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1029,7 +1029,6 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
                                   struct drm_i915_error_state *error)
 {
        struct drm_device *dev = dev_priv->dev;
-       int pipe;
 
        /* General organization
         * 1. Registers specific to a single generation
@@ -1081,8 +1080,6 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
                        error->ier = I915_READ16(IER);
                else
                        error->ier = I915_READ(IER);
-               for_each_pipe(pipe)
-                       error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
        }
 
        /* 4: Everything else */

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b39d036..8c852ba 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11911,6 +11911,7 @@ struct intel_display_error_state {
        struct intel_pipe_error_state {
                bool power_domain_on;
                u32 source;
+               u32 stat;
        } pipe[I915_MAX_PIPES];
 
        struct intel_plane_error_state {
@@ -11992,6 +11993,9 @@ intel_display_capture_error_state(struct drm_device *dev)
                }
 
                error->pipe[i].source = I915_READ(PIPESRC(i));
+
+               if (!HAS_PCH_SPLIT(dev))
+                       error->pipe[i].stat = I915_READ(PIPESTAT(i));
        }
 
        error->num_transcoders = INTEL_INFO(dev)->num_pipes;
@@ -12042,6 +12046,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
                err_printf(m, "  Power: %s\n",
                           error->pipe[i].power_domain_on ? "on" : "off");
                err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
+               err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
 
                err_printf(m, "Plane [%d]:\n", i);
                err_printf(m, "  CNTR: %08x\n", error->plane[i].control);