ARM: dts: artpec: add Artpec-6 development board dts
authorLars Persson <lars.persson@axis.com>
Thu, 11 Feb 2016 16:06:18 +0000 (17:06 +0100)
committerOlof Johansson <olof@lixom.net>
Wed, 24 Feb 2016 21:56:55 +0000 (13:56 -0800)
Signed-off-by: Lars Persson <larper@axis.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
arch/arm/boot/dts/Makefile
arch/arm/boot/dts/artpec6-devboard.dts [new file with mode: 0644]

index 30d316d..21d9ed6 100644 (file)
@@ -2,6 +2,8 @@ ifeq ($(CONFIG_OF),y)
 
 dtb-$(CONFIG_ARCH_ALPINE) += \
        alpine-db.dtb
+dtb-$(CONFIG_MACH_ARTPEC6) += \
+       artpec6-devboard.dtb
 dtb-$(CONFIG_MACH_ASM9260) += \
        alphascale-asm9260-devkit.dtb
 # Keep at91 dtb files sorted alphabetically for each SoC
diff --git a/arch/arm/boot/dts/artpec6-devboard.dts b/arch/arm/boot/dts/artpec6-devboard.dts
new file mode 100644 (file)
index 0000000..f823ed3
--- /dev/null
@@ -0,0 +1,64 @@
+/*
+ * Axis ARTPEC-6 development board.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "artpec6.dtsi"
+
+/ {
+       model = "ARTPEC-6 development board";
+       compatible = "axis,artpec6-dev-board", "axis,artpec6";
+
+       aliases {
+               serial0 = &uart0;
+               serial1 = &uart1;
+               serial2 = &uart2;
+               serial3 = &uart3;
+       };
+
+       chosen {
+               stdout-path = "serial3:115200n8";
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x0 0x10000000>;
+       };
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&uart1 {
+       status = "okay";
+};
+
+&uart2 {
+       status = "okay";
+};
+
+&uart3 {
+       status = "okay";
+};
+
+&ethernet {
+       status = "okay";
+
+       phy-handle = <&phy1>;
+       phy-mode = "gmii";
+
+       mdio {
+               #address-cells = <0x1>;
+               #size-cells = <0x0>;
+               phy1: phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       device_type = "ethernet-phy";
+                       reg = <0x0>;
+               };
+       };
+};