arch/arm/boot/dts/imx6qdl-gw52xx.dtsi

   1 /*
   2  * Copyright 2013 Gateworks Corporation
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/gpio/gpio.h>
  13
  14 / {
  15         /* these are used by bootloader for disabling nodes */
  16         aliases {
  17                 led0 = &led0;
  18                 led1 = &led1;
  19                 led2 = &led2;
  20                 nand = &gpmi;
  21                 ssi0 = &ssi1;
  22                 usb0 = &usbh1;
  23                 usb1 = &usbotg;
  24         };
  25
  26         chosen {
  27                 bootargs = "console=ttymxc1,115200";
  28         };
  29
  30         backlight {
  31                 compatible = "pwm-backlight";
  32                 pwms = <&pwm4 0 5000000>;
  33                 brightness-levels = <0 4 8 16 32 64 128 255>;
  34                 default-brightness-level = <7>;
  35         };
  36
  37         leds {
  38                 compatible = "gpio-leds";
  39                 pinctrl-names = "default";
  40                 pinctrl-0 = <&pinctrl_gpio_leds>;
  41
  42                 led0: user1 {
  43                         label = "user1";
  44                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  45                         default-state = "on";
  46                         linux,default-trigger = "heartbeat";
  47                 };
  48
  49                 led1: user2 {
  50                         label = "user2";
  51                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  52                         default-state = "off";
  53                 };
  54
  55                 led2: user3 {
  56                         label = "user3";
  57                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  58                         default-state = "off";
  59                 };
  60         };
  61
  62         memory {
  63                 reg = <0x10000000 0x20000000>;
  64         };
  65
  66         pps {
  67                 compatible = "pps-gpio";
  68                 pinctrl-names = "default";
  69                 pinctrl-0 = <&pinctrl_pps>;
  70                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  71                 status = "okay";
  72         };
  73
  74         regulators {
  75                 compatible = "simple-bus";
  76                 #address-cells = <1>;
  77                 #size-cells = <0>;
  78
  79                 reg_1p0v: regulator@0 {
  80                         compatible = "regulator-fixed";
  81                         reg = <0>;
  82                         regulator-name = "1P0V";
  83                         regulator-min-microvolt = <1000000>;
  84                         regulator-max-microvolt = <1000000>;
  85                         regulator-always-on;
  86                 };
  87
  88                 /* remove this fixed regulator once ltc3676__sw2 driver available */
  89                 reg_1p8v: regulator@1 {
  90                         compatible = "regulator-fixed";
  91                         reg = <1>;
  92                         regulator-name = "1P8V";
  93                         regulator-min-microvolt = <1800000>;
  94                         regulator-max-microvolt = <1800000>;
  95                         regulator-always-on;
  96                 };
  97
  98                 reg_3p3v: regulator@2 {
  99                         compatible = "regulator-fixed";
 100                         reg = <2>;
 101                         regulator-name = "3P3V";
 102                         regulator-min-microvolt = <3300000>;
 103                         regulator-max-microvolt = <3300000>;
 104                         regulator-always-on;
 105                 };
 106
 107                 reg_5p0v: regulator@3 {
 108                         compatible = "regulator-fixed";
 109                         reg = <3>;
 110                         regulator-name = "5P0V";
 111                         regulator-min-microvolt = <5000000>;
 112                         regulator-max-microvolt = <5000000>;
 113                         regulator-always-on;
 114                 };
 115
 116                 reg_usb_otg_vbus: regulator@4 {
 117                         compatible = "regulator-fixed";
 118                         reg = <4>;
 119                         regulator-name = "usb_otg_vbus";
 120                         regulator-min-microvolt = <5000000>;
 121                         regulator-max-microvolt = <5000000>;
 122                         gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 123                         enable-active-high;
 124                 };
 125         };
 126
 127         sound {
 128                 compatible = "fsl,imx6q-ventana-sgtl5000",
 129                              "fsl,imx-audio-sgtl5000";
 130                 model = "sgtl5000-audio";
 131                 ssi-controller = <&ssi1>;
 132                 audio-codec = <&codec>;
 133                 audio-routing =
 134                         "MIC_IN", "Mic Jack",
 135                         "Mic Jack", "Mic Bias",
 136                         "Headphone Jack", "HP_OUT";
 137                 mux-int-port = <1>;
 138                 mux-ext-port = <4>;
 139         };
 140 };
 141
 142 &audmux {
 143         pinctrl-names = "default";
 144         pinctrl-0 = <&pinctrl_audmux>;
 145         status = "okay";
 146 };
 147
 148 &can1 {
 149         pinctrl-names = "default";
 150         pinctrl-0 = <&pinctrl_flexcan1>;
 151         status = "okay";
 152 };
 153
 154 &clks {
 155         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 156                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 157         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 158                           <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 159 };
 160
 161 &ecspi3 {
 162         fsl,spi-num-chipselects = <1>;
 163         cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
 164         pinctrl-names = "default";
 165         pinctrl-0 = <&pinctrl_ecspi3>;
 166         status = "okay";
 167 };
 168
 169 &fec {
 170         pinctrl-names = "default";
 171         pinctrl-0 = <&pinctrl_enet>;
 172         phy-mode = "rgmii-id";
 173         phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 174         status = "okay";
 175 };
 176
 177 &gpmi {
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&pinctrl_gpmi_nand>;
 180         status = "okay";
 181 };
 182
 183 &hdmi {
 184         ddc-i2c-bus = <&i2c3>;
 185         status = "okay";
 186 };
 187
 188 &i2c1 {
 189         clock-frequency = <100000>;
 190         pinctrl-names = "default";
 191         pinctrl-0 = <&pinctrl_i2c1>;
 192         status = "okay";
 193
 194         eeprom1: eeprom@50 {
 195                 compatible = "atmel,24c02";
 196                 reg = <0x50>;
 197                 pagesize = <16>;
 198         };
 199
 200         eeprom2: eeprom@51 {
 201                 compatible = "atmel,24c02";
 202                 reg = <0x51>;
 203                 pagesize = <16>;
 204         };
 205
 206         eeprom3: eeprom@52 {
 207                 compatible = "atmel,24c02";
 208                 reg = <0x52>;
 209                 pagesize = <16>;
 210         };
 211
 212         eeprom4: eeprom@53 {
 213                 compatible = "atmel,24c02";
 214                 reg = <0x53>;
 215                 pagesize = <16>;
 216         };
 217
 218         gpio: pca9555@23 {
 219                 compatible = "nxp,pca9555";
 220                 reg = <0x23>;
 221                 gpio-controller;
 222                 #gpio-cells = <2>;
 223         };
 224
 225         rtc: ds1672@68 {
 226                 compatible = "dallas,ds1672";
 227                 reg = <0x68>;
 228         };
 229 };
 230
 231 &i2c2 {
 232         clock-frequency = <100000>;
 233         pinctrl-names = "default";
 234         pinctrl-0 = <&pinctrl_i2c2>;
 235         status = "okay";
 236 };
 237
 238 &i2c3 {
 239         clock-frequency = <100000>;
 240         pinctrl-names = "default";
 241         pinctrl-0 = <&pinctrl_i2c3>;
 242         status = "okay";
 243
 244         codec: sgtl5000@0a {
 245                 compatible = "fsl,sgtl5000";
 246                 reg = <0x0a>;
 247                 clocks = <&clks IMX6QDL_CLK_CKO>;
 248                 VDDA-supply = <&reg_1p8v>;
 249                 VDDIO-supply = <&reg_3p3v>;
 250         };
 251
 252         touchscreen: egalax_ts@04 {
 253                 compatible = "eeti,egalax_ts";
 254                 reg = <0x04>;
 255                 interrupt-parent = <&gpio7>;
 256                 interrupts = <12 2>;
 257                 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
 258         };
 259 };
 260
 261 &ldb {
 262         status = "okay";
 263
 264         lvds-channel@0 {
 265                 fsl,data-mapping = "spwg";
 266                 fsl,data-width = <18>;
 267                 status = "okay";
 268
 269                 display-timings {
 270                         native-mode = <&timing0>;
 271                         timing0: hsd100pxn1 {
 272                                 clock-frequency = <65000000>;
 273                                 hactive = <1024>;
 274                                 vactive = <768>;
 275                                 hback-porch = <220>;
 276                                 hfront-porch = <40>;
 277                                 vback-porch = <21>;
 278                                 vfront-porch = <7>;
 279                                 hsync-len = <60>;
 280                                 vsync-len = <10>;
 281                         };
 282                 };
 283         };
 284 };
 285
 286 &pcie {
 287         pinctrl-names = "default";
 288         pinctrl-0 = <&pinctrl_pcie>;
 289         reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
 290         status = "okay";
 291 };
 292
 293 &pwm2 {
 294         pinctrl-names = "default";
 295         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 296         status = "disabled";
 297 };
 298
 299 &pwm3 {
 300         pinctrl-names = "default";
 301         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 302         status = "disabled";
 303 };
 304
 305 &pwm4 {
 306         pinctrl-names = "default";
 307         pinctrl-0 = <&pinctrl_pwm4>;
 308         status = "okay";
 309 };
 310
 311 &ssi1 {
 312         status = "okay";
 313 };
 314
 315 &uart1 {
 316         pinctrl-names = "default";
 317         pinctrl-0 = <&pinctrl_uart1>;
 318         status = "okay";
 319 };
 320
 321 &uart2 {
 322         pinctrl-names = "default";
 323         pinctrl-0 = <&pinctrl_uart2>;
 324         status = "okay";
 325 };
 326
 327 &uart5 {
 328         pinctrl-names = "default";
 329         pinctrl-0 = <&pinctrl_uart5>;
 330         status = "okay";
 331 };
 332
 333 &usbotg {
 334         vbus-supply = <&reg_usb_otg_vbus>;
 335         pinctrl-names = "default";
 336         pinctrl-0 = <&pinctrl_usbotg>;
 337         disable-over-current;
 338         status = "okay";
 339 };
 340
 341 &usbh1 {
 342         status = "okay";
 343 };
 344
 345 &usdhc3 {
 346         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 347         pinctrl-0 = <&pinctrl_usdhc3>;
 348         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 349         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 350         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 351         vmmc-supply = <&reg_3p3v>;
 352         no-1-8-v; /* firmware will remove if board revision supports */
 353         status = "okay";
 354 };
 355
 356 &wdog1 {
 357         pinctrl-names = "default";
 358         pinctrl-0 = <&pinctrl_wdog>;
 359         fsl,ext-reset-output;
 360 };
 361
 362 &iomuxc {
 363         imx6qdl-gw52xx {
 364                 pinctrl_audmux: audmuxgrp {
 365                         fsl,pins = <
 366                                 MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
 367                                 MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
 368                                 MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
 369                                 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
 370                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0 /* AUD4_MCK */
 371                         >;
 372                 };
 373
 374                 pinctrl_ecspi3: escpi3grp {
 375                         fsl,pins = <
 376                                 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 377                                 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 378                                 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 379                                 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24       0x100b1
 380                         >;
 381                 };
 382
 383                 pinctrl_enet: enetgrp {
 384                         fsl,pins = <
 385                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 386                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 387                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 388                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 389                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 390                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 391                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 392                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 393                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 394                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 395                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 396                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 397                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 398                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 399                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 400                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 401                                 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0 /* PHY Reset */
 402                         >;
 403                 };
 404
 405                 pinctrl_flexcan1: flexcan1grp {
 406                         fsl,pins = <
 407                                 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
 408                                 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
 409                                 MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x4001b0b0 /* CAN_STBY */
 410                         >;
 411                 };
 412
 413                 pinctrl_gpio_leds: gpioledsgrp {
 414                         fsl,pins = <
 415                                 MX6QDL_PAD_KEY_COL0__GPIO4_IO06  0x1b0b0
 416                                 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07  0x1b0b0
 417                                 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15  0x1b0b0
 418                         >;
 419                 };
 420
 421                 pinctrl_gpmi_nand: gpminandgrp {
 422                         fsl,pins = <
 423                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 424                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 425                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 426                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 427                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 428                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 429                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 430                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 431                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 432                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 433                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 434                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 435                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 436                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 437                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 438                         >;
 439                 };
 440
 441                 pinctrl_i2c1: i2c1grp {
 442                         fsl,pins = <
 443                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 444                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 445                         >;
 446                 };
 447
 448                 pinctrl_i2c2: i2c2grp {
 449                         fsl,pins = <
 450                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 451                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 452                         >;
 453                 };
 454
 455                 pinctrl_i2c3: i2c3grp {
 456                         fsl,pins = <
 457                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 458                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 459                         >;
 460                 };
 461
 462                 pinctrl_pcie: pciegrp {
 463                         fsl,pins = <
 464                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x1b0b0 /* PCIE_RST# */
 465                         >;
 466                 };
 467
 468                 pinctrl_pps: ppsgrp {
 469                         fsl,pins = <
 470                                 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 471                         >;
 472                 };
 473
 474                 pinctrl_pwm2: pwm2grp {
 475                         fsl,pins = <
 476                                 MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 477                         >;
 478                 };
 479
 480                 pinctrl_pwm3: pwm3grp {
 481                         fsl,pins = <
 482                                 MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 483                         >;
 484                 };
 485
 486                 pinctrl_pwm4: pwm4grp {
 487                         fsl,pins = <
 488                                 MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 489                         >;
 490                 };
 491
 492                 pinctrl_uart1: uart1grp {
 493                         fsl,pins = <
 494                                 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 495                                 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 496                         >;
 497                 };
 498
 499                 pinctrl_uart2: uart2grp {
 500                         fsl,pins = <
 501                                 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 502                                 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 503                         >;
 504                 };
 505
 506                 pinctrl_uart5: uart5grp {
 507                         fsl,pins = <
 508                                 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 509                                 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 510                         >;
 511                 };
 512
 513                 pinctrl_usbotg: usbotggrp {
 514                         fsl,pins = <
 515                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 516                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0 /* OTG_PWR_EN */
 517                         >;
 518                 };
 519
 520                 pinctrl_usdhc3: usdhc3grp {
 521                         fsl,pins = <
 522                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 523                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 524                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 525                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 526                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 527                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 528                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 529                                 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 530                         >;
 531                 };
 532
 533                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 534                         fsl,pins = <
 535                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 536                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x170b9
 537                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 538                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 539                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 540                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 541                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 542                                 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 543                         >;
 544                 };
 545
 546                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 547                         fsl,pins = <
 548                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 549                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 550                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 551                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 552                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 553                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 554                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 555                                 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 556                         >;
 557                 };
 558
 559                 pinctrl_wdog: wdoggrp {
 560                         fsl,pins = <
 561                                 MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 562                         >;
 563                 };
 564         };
 565 };