arch/arm/boot/dts/uniphier-common32.dtsi

   1 /*
   2  * Device Tree Source commonly used by UniPhier ARM SoCs
   3  *
   4  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 /include/ "skeleton.dtsi"
  46
  47 / {
  48         psci {
  49                 compatible = "arm,psci-0.2";
  50                 method = "smc";
  51         };
  52
  53         clocks {
  54                 refclk: ref {
  55                         #clock-cells = <0>;
  56                         compatible = "fixed-clock";
  57                 };
  58         };
  59
  60         soc: soc {
  61                 compatible = "simple-bus";
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 ranges;
  65                 interrupt-parent = <&intc>;
  66
  67                 serial0: serial@54006800 {
  68                         compatible = "socionext,uniphier-uart";
  69                         status = "disabled";
  70                         reg = <0x54006800 0x40>;
  71                         interrupts = <0 33 4>;
  72                         pinctrl-names = "default";
  73                         pinctrl-0 = <&pinctrl_uart0>;
  74                         clocks = <&uart_clk>;
  75                 };
  76
  77                 serial1: serial@54006900 {
  78                         compatible = "socionext,uniphier-uart";
  79                         status = "disabled";
  80                         reg = <0x54006900 0x40>;
  81                         interrupts = <0 35 4>;
  82                         pinctrl-names = "default";
  83                         pinctrl-0 = <&pinctrl_uart1>;
  84                         clocks = <&uart_clk>;
  85                 };
  86
  87                 serial2: serial@54006a00 {
  88                         compatible = "socionext,uniphier-uart";
  89                         status = "disabled";
  90                         reg = <0x54006a00 0x40>;
  91                         interrupts = <0 37 4>;
  92                         pinctrl-names = "default";
  93                         pinctrl-0 = <&pinctrl_uart2>;
  94                         clocks = <&uart_clk>;
  95                 };
  96
  97                 serial3: serial@54006b00 {
  98                         compatible = "socionext,uniphier-uart";
  99                         status = "disabled";
 100                         reg = <0x54006b00 0x40>;
 101                         interrupts = <0 177 4>;
 102                         pinctrl-names = "default";
 103                         pinctrl-0 = <&pinctrl_uart3>;
 104                         clocks = <&uart_clk>;
 105                 };
 106
 107                 system_bus: system-bus@58c00000 {
 108                         compatible = "socionext,uniphier-system-bus";
 109                         status = "disabled";
 110                         reg = <0x58c00000 0x400>;
 111                         #address-cells = <2>;
 112                         #size-cells = <1>;
 113                         pinctrl-names = "default";
 114                         pinctrl-0 = <&pinctrl_system_bus>;
 115                 };
 116
 117                 smpctrl@59800000 {
 118                         compatible = "socionext,uniphier-smpctrl";
 119                         reg = <0x59801000 0x400>;
 120                 };
 121
 122                 timer@60000200 {
 123                         compatible = "arm,cortex-a9-global-timer";
 124                         reg = <0x60000200 0x20>;
 125                         interrupts = <1 11 0x104>;
 126                         clocks = <&arm_timer_clk>;
 127                 };
 128
 129                 timer@60000600 {
 130                         compatible = "arm,cortex-a9-twd-timer";
 131                         reg = <0x60000600 0x20>;
 132                         interrupts = <1 13 0x104>;
 133                         clocks = <&arm_timer_clk>;
 134                 };
 135
 136                 intc: interrupt-controller@60001000 {
 137                         compatible = "arm,cortex-a9-gic";
 138                         reg = <0x60001000 0x1000>,
 139                               <0x60000100 0x100>;
 140                         #interrupt-cells = <3>;
 141                         interrupt-controller;
 142                 };
 143
 144                 soc-glue@5f800000 {
 145                         compatible = "simple-mfd", "syscon";
 146                         reg = <0x5f800000 0x2000>;
 147
 148                         pinctrl: pinctrl {
 149                                 /* specify compatible in each SoC DTSI */
 150                         };
 151                 };
 152         };
 153 };
 154
 155 /include/ "uniphier-pinctrl.dtsi"