arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 /*
   2  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
  16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  17
  18 / {
  19         model = "Qualcomm Technologies, Inc. MSM8916";
  20         compatible = "qcom,msm8916";
  21
  22         interrupt-parent = <&intc>;
  23
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         aliases {
  28                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  29                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  30         };
  31
  32         chosen { };
  33
  34         memory {
  35                 device_type = "memory";
  36                 /* We expect the bootloader to fill in the reg */
  37                 reg = <0 0 0 0>;
  38         };
  39
  40         reserved-memory {
  41                 #address-cells = <2>;
  42                 #size-cells = <2>;
  43                 ranges;
  44
  45                 tz-apps@86000000 {
  46                         reg = <0x0 0x86000000 0x0 0x300000>;
  47                         no-map;
  48                 };
  49
  50                 smem_mem: smem_region@86300000 {
  51                         reg = <0x0 0x86300000 0x0 0x100000>;
  52                         no-map;
  53                 };
  54
  55                 hypervisor@86400000 {
  56                         reg = <0x0 0x86400000 0x0 0x100000>;
  57                         no-map;
  58                 };
  59
  60                 tz@86500000 {
  61                         reg = <0x0 0x86500000 0x0 0x180000>;
  62                         no-map;
  63                 };
  64
  65                 reserved@8668000 {
  66                         reg = <0x0 0x86680000 0x0 0x80000>;
  67                         no-map;
  68                 };
  69
  70                 rmtfs@86700000 {
  71                         reg = <0x0 0x86700000 0x0 0xe0000>;
  72                         no-map;
  73                 };
  74
  75                 rfsa@867e00000 {
  76                         reg = <0x0 0x867e0000 0x0 0x20000>;
  77                         no-map;
  78                 };
  79
  80                 mpss@86800000 {
  81                         reg = <0x0 0x86800000 0x0 0x2b00000>;
  82                         no-map;
  83                 };
  84
  85                 wcnss@89300000 {
  86                         reg = <0x0 0x89300000 0x0 0x600000>;
  87                         no-map;
  88                 };
  89
  90                 mba_mem: mba@8ea00000 {
  91                         no-map;
  92                         reg = <0 0x8ea00000 0 0x100000>;
  93                 };
  94         };
  95
  96         cpus {
  97                 #address-cells = <1>;
  98                 #size-cells = <0>;
  99
 100                 CPU0: cpu@0 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a53", "arm,armv8";
 103                         reg = <0x0>;
 104                         next-level-cache = <&L2_0>;
 105                         enable-method = "psci";
 106                         cpu-idle-states = <&CPU_SPC>;
 107                 };
 108
 109                 CPU1: cpu@1 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x1>;
 113                         next-level-cache = <&L2_0>;
 114                         enable-method = "psci";
 115                         cpu-idle-states = <&CPU_SPC>;
 116                 };
 117
 118                 CPU2: cpu@2 {
 119                         device_type = "cpu";
 120                         compatible = "arm,cortex-a53", "arm,armv8";
 121                         reg = <0x2>;
 122                         next-level-cache = <&L2_0>;
 123                         enable-method = "psci";
 124                         cpu-idle-states = <&CPU_SPC>;
 125                 };
 126
 127                 CPU3: cpu@3 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a53", "arm,armv8";
 130                         reg = <0x3>;
 131                         next-level-cache = <&L2_0>;
 132                         enable-method = "psci";
 133                         cpu-idle-states = <&CPU_SPC>;
 134                 };
 135
 136                 L2_0: l2-cache {
 137                       compatible = "cache";
 138                       cache-level = <2>;
 139                 };
 140
 141                 idle-states {
 142                         CPU_SPC: spc {
 143                                 compatible = "arm,idle-state";
 144                                 arm,psci-suspend-param = <0x40000002>;
 145                                 entry-latency-us = <130>;
 146                                 exit-latency-us = <150>;
 147                                 min-residency-us = <2000>;
 148                                 local-timer-stop;
 149                         };
 150                 };
 151         };
 152
 153         psci {
 154                 compatible = "arm,psci-1.0";
 155                 method = "smc";
 156         };
 157
 158         pmu {
 159                 compatible = "arm,armv8-pmuv3";
 160                 interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
 161         };
 162
 163         timer {
 164                 compatible = "arm,armv8-timer";
 165                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 166                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 167                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 168                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 169         };
 170
 171         clocks {
 172                 xo_board: xo_board {
 173                         compatible = "fixed-clock";
 174                         #clock-cells = <0>;
 175                         clock-frequency = <19200000>;
 176                 };
 177
 178                 sleep_clk: sleep_clk {
 179                         compatible = "fixed-clock";
 180                         #clock-cells = <0>;
 181                         clock-frequency = <32768>;
 182                 };
 183         };
 184
 185         smem {
 186                 compatible = "qcom,smem";
 187
 188                 memory-region = <&smem_mem>;
 189                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 190
 191                 hwlocks = <&tcsr_mutex 3>;
 192         };
 193
 194         firmware {
 195                 scm: scm {
 196                         compatible = "qcom,scm";
 197                         clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
 198                         clock-names = "core", "bus", "iface";
 199                         #reset-cells = <1>;
 200                 };
 201         };
 202
 203         soc: soc {
 204                 #address-cells = <1>;
 205                 #size-cells = <1>;
 206                 ranges = <0 0 0 0xffffffff>;
 207                 compatible = "simple-bus";
 208
 209                 restart@4ab000 {
 210                         compatible = "qcom,pshold";
 211                         reg = <0x4ab000 0x4>;
 212                 };
 213
 214                 msmgpio: pinctrl@1000000 {
 215                         compatible = "qcom,msm8916-pinctrl";
 216                         reg = <0x1000000 0x300000>;
 217                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 218                         gpio-controller;
 219                         #gpio-cells = <2>;
 220                         interrupt-controller;
 221                         #interrupt-cells = <2>;
 222                 };
 223
 224                 gcc: clock-controller@1800000 {
 225                         compatible = "qcom,gcc-msm8916";
 226                         #clock-cells = <1>;
 227                         #reset-cells = <1>;
 228                         #power-domain-cells = <1>;
 229                         reg = <0x1800000 0x80000>;
 230                 };
 231
 232                 tcsr_mutex_regs: syscon@1905000 {
 233                         compatible = "syscon";
 234                         reg = <0x1905000 0x20000>;
 235                 };
 236
 237                 tcsr: syscon@1937000 {
 238                         compatible = "qcom,tcsr-msm8916", "syscon";
 239                         reg = <0x1937000 0x30000>;
 240                 };
 241
 242                 tcsr_mutex: hwlock {
 243                         compatible = "qcom,tcsr-mutex";
 244                         syscon = <&tcsr_mutex_regs 0 0x1000>;
 245                         #hwlock-cells = <1>;
 246                 };
 247
 248                 rpm_msg_ram: memory@60000 {
 249                         compatible = "qcom,rpm-msg-ram";
 250                         reg = <0x60000 0x8000>;
 251                 };
 252
 253                 blsp1_uart1: serial@78af000 {
 254                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 255                         reg = <0x78af000 0x200>;
 256                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 257                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 258                         clock-names = "core", "iface";
 259                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 260                         dma-names = "rx", "tx";
 261                         status = "disabled";
 262                 };
 263
 264                 apcs: syscon@b011000 {
 265                         compatible = "syscon";
 266                         reg = <0x0b011000 0x1000>;
 267                 };
 268
 269                 blsp1_uart2: serial@78b0000 {
 270                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 271                         reg = <0x78b0000 0x200>;
 272                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 273                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 274                         clock-names = "core", "iface";
 275                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 276                         dma-names = "rx", "tx";
 277                         status = "disabled";
 278                 };
 279
 280                 blsp_dma: dma@7884000 {
 281                         compatible = "qcom,bam-v1.7.0";
 282                         reg = <0x07884000 0x23000>;
 283                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 284                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 285                         clock-names = "bam_clk";
 286                         #dma-cells = <1>;
 287                         qcom,ee = <0>;
 288                         status = "disabled";
 289                 };
 290
 291                 blsp_spi1: spi@78b5000 {
 292                         compatible = "qcom,spi-qup-v2.2.1";
 293                         reg = <0x078b5000 0x600>;
 294                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 295                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 296                                  <&gcc GCC_BLSP1_AHB_CLK>;
 297                         clock-names = "core", "iface";
 298                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 299                         dma-names = "rx", "tx";
 300                         pinctrl-names = "default", "sleep";
 301                         pinctrl-0 = <&spi1_default>;
 302                         pinctrl-1 = <&spi1_sleep>;
 303                         #address-cells = <1>;
 304                         #size-cells = <0>;
 305                         status = "disabled";
 306                 };
 307
 308                 blsp_spi2: spi@78b6000 {
 309                         compatible = "qcom,spi-qup-v2.2.1";
 310                         reg = <0x078b6000 0x600>;
 311                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 312                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 313                                  <&gcc GCC_BLSP1_AHB_CLK>;
 314                         clock-names = "core", "iface";
 315                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 316                         dma-names = "rx", "tx";
 317                         pinctrl-names = "default", "sleep";
 318                         pinctrl-0 = <&spi2_default>;
 319                         pinctrl-1 = <&spi2_sleep>;
 320                         #address-cells = <1>;
 321                         #size-cells = <0>;
 322                         status = "disabled";
 323                 };
 324
 325                 blsp_spi3: spi@78b7000 {
 326                         compatible = "qcom,spi-qup-v2.2.1";
 327                         reg = <0x078b7000 0x600>;
 328                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 329                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 330                                  <&gcc GCC_BLSP1_AHB_CLK>;
 331                         clock-names = "core", "iface";
 332                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 333                         dma-names = "rx", "tx";
 334                         pinctrl-names = "default", "sleep";
 335                         pinctrl-0 = <&spi3_default>;
 336                         pinctrl-1 = <&spi3_sleep>;
 337                         #address-cells = <1>;
 338                         #size-cells = <0>;
 339                         status = "disabled";
 340                 };
 341
 342                 blsp_spi4: spi@78b8000 {
 343                         compatible = "qcom,spi-qup-v2.2.1";
 344                         reg = <0x078b8000 0x600>;
 345                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 346                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 347                                  <&gcc GCC_BLSP1_AHB_CLK>;
 348                         clock-names = "core", "iface";
 349                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 350                         dma-names = "rx", "tx";
 351                         pinctrl-names = "default", "sleep";
 352                         pinctrl-0 = <&spi4_default>;
 353                         pinctrl-1 = <&spi4_sleep>;
 354                         #address-cells = <1>;
 355                         #size-cells = <0>;
 356                         status = "disabled";
 357                 };
 358
 359                 blsp_spi5: spi@78b9000 {
 360                         compatible = "qcom,spi-qup-v2.2.1";
 361                         reg = <0x078b9000 0x600>;
 362                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 363                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 364                                  <&gcc GCC_BLSP1_AHB_CLK>;
 365                         clock-names = "core", "iface";
 366                         dmas = <&blsp_dma 13>, <&blsp_dma 12>;
 367                         dma-names = "rx", "tx";
 368                         pinctrl-names = "default", "sleep";
 369                         pinctrl-0 = <&spi5_default>;
 370                         pinctrl-1 = <&spi5_sleep>;
 371                         #address-cells = <1>;
 372                         #size-cells = <0>;
 373                         status = "disabled";
 374                 };
 375
 376                 blsp_spi6: spi@78ba000 {
 377                         compatible = "qcom,spi-qup-v2.2.1";
 378                         reg = <0x078ba000 0x600>;
 379                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 380                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
 381                                  <&gcc GCC_BLSP1_AHB_CLK>;
 382                         clock-names = "core", "iface";
 383                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 384                         dma-names = "rx", "tx";
 385                         pinctrl-names = "default", "sleep";
 386                         pinctrl-0 = <&spi6_default>;
 387                         pinctrl-1 = <&spi6_sleep>;
 388                         #address-cells = <1>;
 389                         #size-cells = <0>;
 390                         status = "disabled";
 391                 };
 392
 393                 blsp_i2c2: i2c@78b6000 {
 394                         compatible = "qcom,i2c-qup-v2.2.1";
 395                         reg = <0x78b6000 0x1000>;
 396                         interrupts = <GIC_SPI 96 0>;
 397                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 398                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 399                         clock-names = "iface", "core";
 400                         pinctrl-names = "default", "sleep";
 401                         pinctrl-0 = <&i2c2_default>;
 402                         pinctrl-1 = <&i2c2_sleep>;
 403                         #address-cells = <1>;
 404                         #size-cells = <0>;
 405                         status = "disabled";
 406                 };
 407
 408                 blsp_i2c4: i2c@78b8000 {
 409                         compatible = "qcom,i2c-qup-v2.2.1";
 410                         reg = <0x78b8000 0x1000>;
 411                         interrupts = <GIC_SPI 98 0>;
 412                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 413                                 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 414                         clock-names = "iface", "core";
 415                         pinctrl-names = "default", "sleep";
 416                         pinctrl-0 = <&i2c4_default>;
 417                         pinctrl-1 = <&i2c4_sleep>;
 418                         #address-cells = <1>;
 419                         #size-cells = <0>;
 420                         status = "disabled";
 421                 };
 422
 423                 blsp_i2c6: i2c@78ba000 {
 424                         compatible = "qcom,i2c-qup-v2.2.1";
 425                         reg = <0x78ba000 0x1000>;
 426                         interrupts = <GIC_SPI 100 0>;
 427                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 428                                 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
 429                         clock-names = "iface", "core";
 430                         pinctrl-names = "default", "sleep";
 431                         pinctrl-0 = <&i2c6_default>;
 432                         pinctrl-1 = <&i2c6_sleep>;
 433                         #address-cells = <1>;
 434                         #size-cells = <0>;
 435                         status = "disabled";
 436                 };
 437
 438                 lpass: lpass@07708000 {
 439                         status = "disabled";
 440                         compatible = "qcom,lpass-cpu-apq8016";
 441                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
 442                                  <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
 443                                  <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
 444                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
 445                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 446                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 447                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
 448
 449                         clock-names = "ahbix-clk",
 450                                         "pcnoc-mport-clk",
 451                                         "pcnoc-sway-clk",
 452                                         "mi2s-bit-clk0",
 453                                         "mi2s-bit-clk1",
 454                                         "mi2s-bit-clk2",
 455                                         "mi2s-bit-clk3";
 456                         #sound-dai-cells = <1>;
 457
 458                         interrupts = <0 160 0>;
 459                         interrupt-names = "lpass-irq-lpaif";
 460                         reg = <0x07708000 0x10000>;
 461                         reg-names = "lpass-lpaif";
 462                 };
 463
 464                 sdhc_1: sdhci@07824000 {
 465                         compatible = "qcom,sdhci-msm-v4";
 466                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
 467                         reg-names = "hc_mem", "core_mem";
 468
 469                         interrupts = <0 123 0>, <0 138 0>;
 470                         interrupt-names = "hc_irq", "pwr_irq";
 471                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 472                                  <&gcc GCC_SDCC1_AHB_CLK>;
 473                         clock-names = "core", "iface";
 474                         bus-width = <8>;
 475                         non-removable;
 476                         status = "disabled";
 477                 };
 478
 479                 sdhc_2: sdhci@07864000 {
 480                         compatible = "qcom,sdhci-msm-v4";
 481                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
 482                         reg-names = "hc_mem", "core_mem";
 483
 484                         interrupts = <0 125 0>, <0 221 0>;
 485                         interrupt-names = "hc_irq", "pwr_irq";
 486                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 487                                  <&gcc GCC_SDCC2_AHB_CLK>;
 488                         clock-names = "core", "iface";
 489                         bus-width = <4>;
 490                         status = "disabled";
 491                 };
 492
 493                 usb_dev: usb@78d9000 {
 494                         compatible = "qcom,ci-hdrc";
 495                         reg = <0x78d9000 0x400>;
 496                         dr_mode = "peripheral";
 497                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 498                         usb-phy = <&usb_otg>;
 499                         status = "disabled";
 500                 };
 501
 502                 usb_host: ehci@78d9000 {
 503                         compatible = "qcom,ehci-host";
 504                         reg = <0x78d9000 0x400>;
 505                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 506                         usb-phy = <&usb_otg>;
 507                         status = "disabled";
 508                 };
 509
 510                 usb_otg: phy@78d9000 {
 511                         compatible = "qcom,usb-otg-snps";
 512                         reg = <0x78d9000 0x400>;
 513                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 514                                      <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 515
 516                         qcom,vdd-levels = <500000 1000000 1320000>;
 517                         qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
 518                         dr_mode = "peripheral";
 519                         qcom,otg-control = <2>; // PMIC
 520                         qcom,manual-pullup;
 521
 522                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 523                                  <&gcc GCC_USB_HS_SYSTEM_CLK>,
 524                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 525                         clock-names = "iface", "core", "sleep";
 526
 527                         resets = <&gcc GCC_USB2A_PHY_BCR>,
 528                                  <&gcc GCC_USB_HS_BCR>;
 529                         reset-names = "phy", "link";
 530                         status = "disabled";
 531                 };
 532
 533                 intc: interrupt-controller@b000000 {
 534                         compatible = "qcom,msm-qgic2";
 535                         interrupt-controller;
 536                         #interrupt-cells = <3>;
 537                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 538                 };
 539
 540                 timer@b020000 {
 541                         #address-cells = <1>;
 542                         #size-cells = <1>;
 543                         ranges;
 544                         compatible = "arm,armv7-timer-mem";
 545                         reg = <0xb020000 0x1000>;
 546                         clock-frequency = <19200000>;
 547
 548                         frame@b021000 {
 549                                 frame-number = <0>;
 550                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 551                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 552                                 reg = <0xb021000 0x1000>,
 553                                       <0xb022000 0x1000>;
 554                         };
 555
 556                         frame@b023000 {
 557                                 frame-number = <1>;
 558                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 559                                 reg = <0xb023000 0x1000>;
 560                                 status = "disabled";
 561                         };
 562
 563                         frame@b024000 {
 564                                 frame-number = <2>;
 565                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 566                                 reg = <0xb024000 0x1000>;
 567                                 status = "disabled";
 568                         };
 569
 570                         frame@b025000 {
 571                                 frame-number = <3>;
 572                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 573                                 reg = <0xb025000 0x1000>;
 574                                 status = "disabled";
 575                         };
 576
 577                         frame@b026000 {
 578                                 frame-number = <4>;
 579                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 580                                 reg = <0xb026000 0x1000>;
 581                                 status = "disabled";
 582                         };
 583
 584                         frame@b027000 {
 585                                 frame-number = <5>;
 586                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 587                                 reg = <0xb027000 0x1000>;
 588                                 status = "disabled";
 589                         };
 590
 591                         frame@b028000 {
 592                                 frame-number = <6>;
 593                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 594                                 reg = <0xb028000 0x1000>;
 595                                 status = "disabled";
 596                         };
 597                 };
 598
 599                 spmi_bus: spmi@200f000 {
 600                         compatible = "qcom,spmi-pmic-arb";
 601                         reg = <0x200f000 0x001000>,
 602                               <0x2400000 0x400000>,
 603                               <0x2c00000 0x400000>,
 604                               <0x3800000 0x200000>,
 605                               <0x200a000 0x002100>;
 606                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 607                         interrupt-names = "periph_irq";
 608                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 609                         qcom,ee = <0>;
 610                         qcom,channel = <0>;
 611                         #address-cells = <2>;
 612                         #size-cells = <0>;
 613                         interrupt-controller;
 614                         #interrupt-cells = <4>;
 615                 };
 616
 617                 rng@22000 {
 618                         compatible = "qcom,prng";
 619                         reg = <0x00022000 0x200>;
 620                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 621                         clock-names = "core";
 622                 };
 623         };
 624
 625         smd {
 626                 compatible = "qcom,smd";
 627
 628                 rpm {
 629                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 630                         qcom,ipc = <&apcs 8 0>;
 631                         qcom,smd-edge = <15>;
 632
 633                         rpm_requests {
 634                                 compatible = "qcom,rpm-msm8916";
 635                                 qcom,smd-channels = "rpm_requests";
 636
 637                                 rpmcc: qcom,rpmcc {
 638                                         compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
 639                                         #clock-cells = <1>;
 640                                 };
 641
 642                                 smd_rpm_regulators: pm8916-regulators {
 643                                         compatible = "qcom,rpm-pm8916-regulators";
 644
 645                                         pm8916_s1: s1 {};
 646                                         pm8916_s3: s3 {};
 647                                         pm8916_s4: s4 {};
 648
 649                                         pm8916_l1: l1 {};
 650                                         pm8916_l2: l2 {};
 651                                         pm8916_l3: l3 {};
 652                                         pm8916_l4: l4 {};
 653                                         pm8916_l5: l5 {};
 654                                         pm8916_l6: l6 {};
 655                                         pm8916_l7: l7 {};
 656                                         pm8916_l8: l8 {};
 657                                         pm8916_l9: l9 {};
 658                                         pm8916_l10: l10 {};
 659                                         pm8916_l11: l11 {};
 660                                         pm8916_l12: l12 {};
 661                                         pm8916_l13: l13 {};
 662                                         pm8916_l14: l14 {};
 663                                         pm8916_l15: l15 {};
 664                                         pm8916_l16: l16 {};
 665                                         pm8916_l17: l17 {};
 666                                         pm8916_l18: l18 {};
 667                                 };
 668                         };
 669                 };
 670         };
 671
 672         hexagon-smp2p {
 673                 compatible = "qcom,smp2p";
 674                 qcom,smem = <435>, <428>;
 675
 676                 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
 677
 678                 qcom,ipc = <&apcs 8 14>;
 679
 680                 qcom,local-pid = <0>;
 681                 qcom,remote-pid = <1>;
 682
 683                 hexagon_smp2p_out: master-kernel {
 684                         qcom,entry-name = "master-kernel";
 685
 686                         #qcom,smem-state-cells = <1>;
 687                 };
 688
 689                 hexagon_smp2p_in: slave-kernel {
 690                         qcom,entry-name = "slave-kernel";
 691
 692                         interrupt-controller;
 693                         #interrupt-cells = <2>;
 694                 };
 695         };
 696
 697         wcnss-smp2p {
 698                 compatible = "qcom,smp2p";
 699                 qcom,smem = <451>, <431>;
 700
 701                 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
 702
 703                 qcom,ipc = <&apcs 8 18>;
 704
 705                 qcom,local-pid = <0>;
 706                 qcom,remote-pid = <4>;
 707
 708                 wcnss_smp2p_out: master-kernel {
 709                         qcom,entry-name = "master-kernel";
 710
 711                         #qcom,smem-state-cells = <1>;
 712                 };
 713
 714                 wcnss_smp2p_in: slave-kernel {
 715                         qcom,entry-name = "slave-kernel";
 716
 717                         interrupt-controller;
 718                         #interrupt-cells = <2>;
 719                 };
 720         };
 721
 722         smsm {
 723                 compatible = "qcom,smsm";
 724
 725                 #address-cells = <1>;
 726                 #size-cells = <0>;
 727
 728                 qcom,ipc-1 = <&apcs 0 13>;
 729                 qcom,ipc-6 = <&apcs 0 19>;
 730
 731                 apps_smsm: apps@0 {
 732                         reg = <0>;
 733
 734                         #qcom,smem-state-cells = <1>;
 735                 };
 736
 737                 hexagon_smsm: hexagon@1 {
 738                         reg = <1>;
 739                         interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
 740
 741                         interrupt-controller;
 742                         #interrupt-cells = <2>;
 743                 };
 744
 745                 wcnss_smsm: wcnss@6 {
 746                         reg = <6>;
 747                         interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
 748
 749                         interrupt-controller;
 750                         #interrupt-cells = <2>;
 751                 };
 752         };
 753 };
 754
 755 #include "msm8916-pins.dtsi"