arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/sort.h>
  23 #include <linux/types.h>
  24 #include <asm/cpu.h>
  25 #include <asm/cpufeature.h>
  26 #include <asm/cpu_ops.h>
  27 #include <asm/mmu_context.h>
  28 #include <asm/processor.h>
  29 #include <asm/sysreg.h>
  30
  31 unsigned long elf_hwcap __read_mostly;
  32 EXPORT_SYMBOL_GPL(elf_hwcap);
  33
  34 #ifdef CONFIG_COMPAT
  35 #define COMPAT_ELF_HWCAP_DEFAULT        \
  36                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  37                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  38                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  39                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  40                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  41                                  COMPAT_HWCAP_LPAE)
  42 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  43 unsigned int compat_elf_hwcap2 __read_mostly;
  44 #endif
  45
  46 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  47
  48 #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  49         {                                               \
  50                 .sign = SIGNED,                         \
  51                 .strict = STRICT,                       \
  52                 .type = TYPE,                           \
  53                 .shift = SHIFT,                         \
  54                 .width = WIDTH,                         \
  55                 .safe_val = SAFE_VAL,                   \
  56         }
  57
  58 /* Define a feature with unsigned values */
  59 #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  60         __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  61
  62 /* Define a feature with a signed value */
  63 #define S_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  64         __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  65
  66 #define ARM64_FTR_END                                   \
  67         {                                               \
  68                 .width = 0,                             \
  69         }
  70
  71 /* meta feature for alternatives */
  72 static bool __maybe_unused
  73 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry);
  74
  75 static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
  76         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  77         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
  78         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
  79         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
  80         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
  81         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
  82         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
  83         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
  84         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
  85         ARM64_FTR_END,
  86 };
  87
  88 static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
  89         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  90         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
  91         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
  92         S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
  93         S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
  94         /* Linux doesn't care about the EL3 */
  95         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
  96         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
  97         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
  98         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
  99         ARM64_FTR_END,
 100 };
 101
 102 static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 103         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 104         S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 105         S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 106         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 107         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 108         /* Linux shouldn't care about secure memory */
 109         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 110         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 111         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 112         /*
 113          * Differing PARange is fine as long as all peripherals and memory are mapped
 114          * within the minimum PARange of all CPUs
 115          */
 116         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 117         ARM64_FTR_END,
 118 };
 119
 120 static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 121         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 122         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 123         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 124         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 125         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 126         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 127         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 128         ARM64_FTR_END,
 129 };
 130
 131 static struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 132         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 133         ARM64_FTR_END,
 134 };
 135
 136 static struct arm64_ftr_bits ftr_ctr[] = {
 137         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1),        /* RAO */
 138         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
 139         ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0),  /* CWG */
 140         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),   /* ERG */
 141         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1),   /* DminLine */
 142         /*
 143          * Linux can handle differing I-cache policies. Userspace JITs will
 144          * make use of *minLine
 145          */
 146         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0),     /* L1Ip */
 147         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0),        /* RAZ */
 148         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),    /* IminLine */
 149         ARM64_FTR_END,
 150 };
 151
 152 static struct arm64_ftr_bits ftr_id_mmfr0[] = {
 153         S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0xf),    /* InnerShr */
 154         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),        /* FCSE */
 155         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),        /* AuxReg */
 156         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0),        /* TCM */
 157         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* ShareLvl */
 158         S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0xf),     /* OuterShr */
 159         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
 160         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
 161         ARM64_FTR_END,
 162 };
 163
 164 static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 165         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 166         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 167         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 168         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 169         S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 170         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 171         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 172         ARM64_FTR_END,
 173 };
 174
 175 static struct arm64_ftr_bits ftr_mvfr2[] = {
 176         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 177         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* FPMisc */
 178         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* SIMDMisc */
 179         ARM64_FTR_END,
 180 };
 181
 182 static struct arm64_ftr_bits ftr_dczid[] = {
 183         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0),        /* RAZ */
 184         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1),         /* DZP */
 185         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),    /* BS */
 186         ARM64_FTR_END,
 187 };
 188
 189
 190 static struct arm64_ftr_bits ftr_id_isar5[] = {
 191         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
 192         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0),        /* RAZ */
 193         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
 194         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
 195         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
 196         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
 197         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
 198         ARM64_FTR_END,
 199 };
 200
 201 static struct arm64_ftr_bits ftr_id_mmfr4[] = {
 202         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 203         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* ac2 */
 204         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* RAZ */
 205         ARM64_FTR_END,
 206 };
 207
 208 static struct arm64_ftr_bits ftr_id_pfr0[] = {
 209         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0),       /* RAZ */
 210         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* State3 */
 211         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0),         /* State2 */
 212         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* State1 */
 213         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* State0 */
 214         ARM64_FTR_END,
 215 };
 216
 217 static struct arm64_ftr_bits ftr_id_dfr0[] = {
 218         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 219         S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),       /* PerfMon */
 220         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 221         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 222         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 223         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 224         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 225         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 226         ARM64_FTR_END,
 227 };
 228
 229 /*
 230  * Common ftr bits for a 32bit register with all hidden, strict
 231  * attributes, with 4bit feature fields and a default safe value of
 232  * 0. Covers the following 32bit registers:
 233  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 234  */
 235 static struct arm64_ftr_bits ftr_generic_32bits[] = {
 236         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 237         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 238         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 239         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 240         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 241         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 242         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 243         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 244         ARM64_FTR_END,
 245 };
 246
 247 static struct arm64_ftr_bits ftr_generic[] = {
 248         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 249         ARM64_FTR_END,
 250 };
 251
 252 static struct arm64_ftr_bits ftr_generic32[] = {
 253         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
 254         ARM64_FTR_END,
 255 };
 256
 257 static struct arm64_ftr_bits ftr_aa64raz[] = {
 258         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 259         ARM64_FTR_END,
 260 };
 261
 262 #define ARM64_FTR_REG(id, table)                \
 263         {                                       \
 264                 .sys_id = id,                   \
 265                 .name = #id,                    \
 266                 .ftr_bits = &((table)[0]),      \
 267         }
 268
 269 static struct arm64_ftr_reg arm64_ftr_regs[] = {
 270
 271         /* Op1 = 0, CRn = 0, CRm = 1 */
 272         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 273         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 274         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 275         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 276         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 277         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 278         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 279
 280         /* Op1 = 0, CRn = 0, CRm = 2 */
 281         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 282         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 283         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 284         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 285         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 286         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 287         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 288
 289         /* Op1 = 0, CRn = 0, CRm = 3 */
 290         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 291         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 292         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 293
 294         /* Op1 = 0, CRn = 0, CRm = 4 */
 295         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 296         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
 297
 298         /* Op1 = 0, CRn = 0, CRm = 5 */
 299         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 300         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
 301
 302         /* Op1 = 0, CRn = 0, CRm = 6 */
 303         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 304         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
 305
 306         /* Op1 = 0, CRn = 0, CRm = 7 */
 307         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 308         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 309         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 310
 311         /* Op1 = 3, CRn = 0, CRm = 0 */
 312         ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
 313         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 314
 315         /* Op1 = 3, CRn = 14, CRm = 0 */
 316         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
 317 };
 318
 319 static int search_cmp_ftr_reg(const void *id, const void *regp)
 320 {
 321         return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
 322 }
 323
 324 /*
 325  * get_arm64_ftr_reg - Lookup a feature register entry using its
 326  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 327  * ascending order of sys_id , we use binary search to find a matching
 328  * entry.
 329  *
 330  * returns - Upon success,  matching ftr_reg entry for id.
 331  *         - NULL on failure. It is upto the caller to decide
 332  *           the impact of a failure.
 333  */
 334 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 335 {
 336         return bsearch((const void *)(unsigned long)sys_id,
 337                         arm64_ftr_regs,
 338                         ARRAY_SIZE(arm64_ftr_regs),
 339                         sizeof(arm64_ftr_regs[0]),
 340                         search_cmp_ftr_reg);
 341 }
 342
 343 static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
 344 {
 345         u64 mask = arm64_ftr_mask(ftrp);
 346
 347         reg &= ~mask;
 348         reg |= (ftr_val << ftrp->shift) & mask;
 349         return reg;
 350 }
 351
 352 static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
 353 {
 354         s64 ret = 0;
 355
 356         switch (ftrp->type) {
 357         case FTR_EXACT:
 358                 ret = ftrp->safe_val;
 359                 break;
 360         case FTR_LOWER_SAFE:
 361                 ret = new < cur ? new : cur;
 362                 break;
 363         case FTR_HIGHER_SAFE:
 364                 ret = new > cur ? new : cur;
 365                 break;
 366         default:
 367                 BUG();
 368         }
 369
 370         return ret;
 371 }
 372
 373 static int __init sort_cmp_ftr_regs(const void *a, const void *b)
 374 {
 375         return ((const struct arm64_ftr_reg *)a)->sys_id -
 376                  ((const struct arm64_ftr_reg *)b)->sys_id;
 377 }
 378
 379 static void __init swap_ftr_regs(void *a, void *b, int size)
 380 {
 381         struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
 382         *(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
 383         *(struct arm64_ftr_reg *)b = tmp;
 384 }
 385
 386 static void __init sort_ftr_regs(void)
 387 {
 388         /* Keep the array sorted so that we can do the binary search */
 389         sort(arm64_ftr_regs,
 390                 ARRAY_SIZE(arm64_ftr_regs),
 391                 sizeof(arm64_ftr_regs[0]),
 392                 sort_cmp_ftr_regs,
 393                 swap_ftr_regs);
 394 }
 395
 396 /*
 397  * Initialise the CPU feature register from Boot CPU values.
 398  * Also initiliases the strict_mask for the register.
 399  */
 400 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 401 {
 402         u64 val = 0;
 403         u64 strict_mask = ~0x0ULL;
 404         struct arm64_ftr_bits *ftrp;
 405         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 406
 407         BUG_ON(!reg);
 408
 409         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 410                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 411
 412                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 413                 if (!ftrp->strict)
 414                         strict_mask &= ~arm64_ftr_mask(ftrp);
 415         }
 416         reg->sys_val = val;
 417         reg->strict_mask = strict_mask;
 418 }
 419
 420 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 421 {
 422         /* Before we start using the tables, make sure it is sorted */
 423         sort_ftr_regs();
 424
 425         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 426         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 427         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 428         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 429         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 430         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 431         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 432         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 433         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 434         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 435         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 436         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 437         init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 438         init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 439         init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 440         init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 441         init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 442         init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 443         init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 444         init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 445         init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 446         init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 447         init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 448         init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 449         init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 450         init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 451         init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 452         init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 453 }
 454
 455 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 456 {
 457         struct arm64_ftr_bits *ftrp;
 458
 459         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 460                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 461                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 462
 463                 if (ftr_cur == ftr_new)
 464                         continue;
 465                 /* Find a safe value */
 466                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 467                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 468         }
 469
 470 }
 471
 472 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 473 {
 474         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 475
 476         BUG_ON(!regp);
 477         update_cpu_ftr_reg(regp, val);
 478         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 479                 return 0;
 480         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 481                         regp->name, boot, cpu, val);
 482         return 1;
 483 }
 484
 485 /*
 486  * Update system wide CPU feature registers with the values from a
 487  * non-boot CPU. Also performs SANITY checks to make sure that there
 488  * aren't any insane variations from that of the boot CPU.
 489  */
 490 void update_cpu_features(int cpu,
 491                          struct cpuinfo_arm64 *info,
 492                          struct cpuinfo_arm64 *boot)
 493 {
 494         int taint = 0;
 495
 496         /*
 497          * The kernel can handle differing I-cache policies, but otherwise
 498          * caches should look identical. Userspace JITs will make use of
 499          * *minLine.
 500          */
 501         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 502                                       info->reg_ctr, boot->reg_ctr);
 503
 504         /*
 505          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 506          * could result in too much or too little memory being zeroed if a
 507          * process is preempted and migrated between CPUs.
 508          */
 509         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 510                                       info->reg_dczid, boot->reg_dczid);
 511
 512         /* If different, timekeeping will be broken (especially with KVM) */
 513         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 514                                       info->reg_cntfrq, boot->reg_cntfrq);
 515
 516         /*
 517          * The kernel uses self-hosted debug features and expects CPUs to
 518          * support identical debug features. We presently need CTX_CMPs, WRPs,
 519          * and BRPs to be identical.
 520          * ID_AA64DFR1 is currently RES0.
 521          */
 522         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 523                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 524         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 525                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 526         /*
 527          * Even in big.LITTLE, processors should be identical instruction-set
 528          * wise.
 529          */
 530         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 531                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 532         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 533                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 534
 535         /*
 536          * Differing PARange support is fine as long as all peripherals and
 537          * memory are mapped within the minimum PARange of all CPUs.
 538          * Linux should not care about secure memory.
 539          */
 540         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 541                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 542         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 543                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 544         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 545                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 546
 547         /*
 548          * EL3 is not our concern.
 549          * ID_AA64PFR1 is currently RES0.
 550          */
 551         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 552                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 553         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 554                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 555
 556         /*
 557          * If we have AArch32, we care about 32-bit features for compat. These
 558          * registers should be RES0 otherwise.
 559          */
 560         taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 561                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 562         taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 563                                         info->reg_id_isar0, boot->reg_id_isar0);
 564         taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 565                                         info->reg_id_isar1, boot->reg_id_isar1);
 566         taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 567                                         info->reg_id_isar2, boot->reg_id_isar2);
 568         taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 569                                         info->reg_id_isar3, boot->reg_id_isar3);
 570         taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 571                                         info->reg_id_isar4, boot->reg_id_isar4);
 572         taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 573                                         info->reg_id_isar5, boot->reg_id_isar5);
 574
 575         /*
 576          * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 577          * ACTLR formats could differ across CPUs and therefore would have to
 578          * be trapped for virtualization anyway.
 579          */
 580         taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 581                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 582         taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 583                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 584         taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 585                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 586         taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 587                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 588         taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 589                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 590         taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 591                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 592         taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 593                                         info->reg_mvfr0, boot->reg_mvfr0);
 594         taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 595                                         info->reg_mvfr1, boot->reg_mvfr1);
 596         taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 597                                         info->reg_mvfr2, boot->reg_mvfr2);
 598
 599         /*
 600          * Mismatched CPU features are a recipe for disaster. Don't even
 601          * pretend to support them.
 602          */
 603         WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
 604                         "Unsupported CPU feature variation.\n");
 605 }
 606
 607 u64 read_system_reg(u32 id)
 608 {
 609         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 610
 611         /* We shouldn't get a request for an unsupported register */
 612         BUG_ON(!regp);
 613         return regp->sys_val;
 614 }
 615
 616 #include <linux/irqchip/arm-gic-v3.h>
 617
 618 static bool
 619 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 620 {
 621         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 622
 623         return val >= entry->min_field_value;
 624 }
 625
 626 static bool
 627 has_cpuid_feature(const struct arm64_cpu_capabilities *entry)
 628 {
 629         u64 val;
 630
 631         val = read_system_reg(entry->sys_reg);
 632         return feature_matches(val, entry);
 633 }
 634
 635 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
 636 {
 637         bool has_sre;
 638
 639         if (!has_cpuid_feature(entry))
 640                 return false;
 641
 642         has_sre = gic_enable_sre();
 643         if (!has_sre)
 644                 pr_warn_once("%s present but disabled by higher exception level\n",
 645                              entry->desc);
 646
 647         return has_sre;
 648 }
 649
 650 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry)
 651 {
 652         u32 midr = read_cpuid_id();
 653         u32 rv_min, rv_max;
 654
 655         /* Cavium ThunderX pass 1.x and 2.x */
 656         rv_min = 0;
 657         rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK;
 658
 659         return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
 660 }
 661
 662 static const struct arm64_cpu_capabilities arm64_features[] = {
 663         {
 664                 .desc = "GIC system register CPU interface",
 665                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
 666                 .matches = has_useable_gicv3_cpuif,
 667                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 668                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
 669                 .sign = FTR_UNSIGNED,
 670                 .min_field_value = 1,
 671         },
 672 #ifdef CONFIG_ARM64_PAN
 673         {
 674                 .desc = "Privileged Access Never",
 675                 .capability = ARM64_HAS_PAN,
 676                 .matches = has_cpuid_feature,
 677                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
 678                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
 679                 .sign = FTR_UNSIGNED,
 680                 .min_field_value = 1,
 681                 .enable = cpu_enable_pan,
 682         },
 683 #endif /* CONFIG_ARM64_PAN */
 684 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
 685         {
 686                 .desc = "LSE atomic instructions",
 687                 .capability = ARM64_HAS_LSE_ATOMICS,
 688                 .matches = has_cpuid_feature,
 689                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
 690                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
 691                 .sign = FTR_UNSIGNED,
 692                 .min_field_value = 2,
 693         },
 694 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
 695         {
 696                 .desc = "Software prefetching using PRFM",
 697                 .capability = ARM64_HAS_NO_HW_PREFETCH,
 698                 .matches = has_no_hw_prefetch,
 699         },
 700 #ifdef CONFIG_ARM64_UAO
 701         {
 702                 .desc = "User Access Override",
 703                 .capability = ARM64_HAS_UAO,
 704                 .matches = has_cpuid_feature,
 705                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
 706                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
 707                 .min_field_value = 1,
 708                 .enable = cpu_enable_uao,
 709         },
 710 #endif /* CONFIG_ARM64_UAO */
 711 #ifdef CONFIG_ARM64_PAN
 712         {
 713                 .capability = ARM64_ALT_PAN_NOT_UAO,
 714                 .matches = cpufeature_pan_not_uao,
 715         },
 716 #endif /* CONFIG_ARM64_PAN */
 717         {},
 718 };
 719
 720 #define HWCAP_CAP(reg, field, s, min_value, type, cap)  \
 721         {                                                       \
 722                 .desc = #cap,                                   \
 723                 .matches = has_cpuid_feature,                   \
 724                 .sys_reg = reg,                                 \
 725                 .field_pos = field,                             \
 726                 .sign = s,                                      \
 727                 .min_field_value = min_value,                   \
 728                 .hwcap_type = type,                             \
 729                 .hwcap = cap,                                   \
 730         }
 731
 732 static const struct arm64_cpu_capabilities arm64_hwcaps[] = {
 733         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
 734         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
 735         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
 736         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
 737         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
 738         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
 739         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
 740         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
 741         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
 742         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
 743 #ifdef CONFIG_COMPAT
 744         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
 745         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
 746         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
 747         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
 748         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
 749 #endif
 750         {},
 751 };
 752
 753 static void __init cap_set_hwcap(const struct arm64_cpu_capabilities *cap)
 754 {
 755         switch (cap->hwcap_type) {
 756         case CAP_HWCAP:
 757                 elf_hwcap |= cap->hwcap;
 758                 break;
 759 #ifdef CONFIG_COMPAT
 760         case CAP_COMPAT_HWCAP:
 761                 compat_elf_hwcap |= (u32)cap->hwcap;
 762                 break;
 763         case CAP_COMPAT_HWCAP2:
 764                 compat_elf_hwcap2 |= (u32)cap->hwcap;
 765                 break;
 766 #endif
 767         default:
 768                 WARN_ON(1);
 769                 break;
 770         }
 771 }
 772
 773 /* Check if we have a particular HWCAP enabled */
 774 static bool __maybe_unused cpus_have_hwcap(const struct arm64_cpu_capabilities *cap)
 775 {
 776         bool rc;
 777
 778         switch (cap->hwcap_type) {
 779         case CAP_HWCAP:
 780                 rc = (elf_hwcap & cap->hwcap) != 0;
 781                 break;
 782 #ifdef CONFIG_COMPAT
 783         case CAP_COMPAT_HWCAP:
 784                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
 785                 break;
 786         case CAP_COMPAT_HWCAP2:
 787                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
 788                 break;
 789 #endif
 790         default:
 791                 WARN_ON(1);
 792                 rc = false;
 793         }
 794
 795         return rc;
 796 }
 797
 798 static void __init setup_cpu_hwcaps(void)
 799 {
 800         int i;
 801         const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps;
 802
 803         for (i = 0; hwcaps[i].matches; i++)
 804                 if (hwcaps[i].matches(&hwcaps[i]))
 805                         cap_set_hwcap(&hwcaps[i]);
 806 }
 807
 808 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
 809                             const char *info)
 810 {
 811         int i;
 812
 813         for (i = 0; caps[i].matches; i++) {
 814                 if (!caps[i].matches(&caps[i]))
 815                         continue;
 816
 817                 if (!cpus_have_cap(caps[i].capability) && caps[i].desc)
 818                         pr_info("%s %s\n", info, caps[i].desc);
 819                 cpus_set_cap(caps[i].capability);
 820         }
 821 }
 822
 823 /*
 824  * Run through the enabled capabilities and enable() it on all active
 825  * CPUs
 826  */
 827 static void __init
 828 enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
 829 {
 830         int i;
 831
 832         for (i = 0; caps[i].matches; i++)
 833                 if (caps[i].enable && cpus_have_cap(caps[i].capability))
 834                         on_each_cpu(caps[i].enable, NULL, true);
 835 }
 836
 837 /*
 838  * Flag to indicate if we have computed the system wide
 839  * capabilities based on the boot time active CPUs. This
 840  * will be used to determine if a new booting CPU should
 841  * go through the verification process to make sure that it
 842  * supports the system capabilities, without using a hotplug
 843  * notifier.
 844  */
 845 static bool sys_caps_initialised;
 846
 847 static inline void set_sys_caps_initialised(void)
 848 {
 849         sys_caps_initialised = true;
 850 }
 851
 852 /*
 853  * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
 854  */
 855 static u64 __raw_read_system_reg(u32 sys_id)
 856 {
 857         switch (sys_id) {
 858         case SYS_ID_PFR0_EL1:           return read_cpuid(ID_PFR0_EL1);
 859         case SYS_ID_PFR1_EL1:           return read_cpuid(ID_PFR1_EL1);
 860         case SYS_ID_DFR0_EL1:           return read_cpuid(ID_DFR0_EL1);
 861         case SYS_ID_MMFR0_EL1:          return read_cpuid(ID_MMFR0_EL1);
 862         case SYS_ID_MMFR1_EL1:          return read_cpuid(ID_MMFR1_EL1);
 863         case SYS_ID_MMFR2_EL1:          return read_cpuid(ID_MMFR2_EL1);
 864         case SYS_ID_MMFR3_EL1:          return read_cpuid(ID_MMFR3_EL1);
 865         case SYS_ID_ISAR0_EL1:          return read_cpuid(ID_ISAR0_EL1);
 866         case SYS_ID_ISAR1_EL1:          return read_cpuid(ID_ISAR1_EL1);
 867         case SYS_ID_ISAR2_EL1:          return read_cpuid(ID_ISAR2_EL1);
 868         case SYS_ID_ISAR3_EL1:          return read_cpuid(ID_ISAR3_EL1);
 869         case SYS_ID_ISAR4_EL1:          return read_cpuid(ID_ISAR4_EL1);
 870         case SYS_ID_ISAR5_EL1:          return read_cpuid(ID_ISAR4_EL1);
 871         case SYS_MVFR0_EL1:             return read_cpuid(MVFR0_EL1);
 872         case SYS_MVFR1_EL1:             return read_cpuid(MVFR1_EL1);
 873         case SYS_MVFR2_EL1:             return read_cpuid(MVFR2_EL1);
 874
 875         case SYS_ID_AA64PFR0_EL1:       return read_cpuid(ID_AA64PFR0_EL1);
 876         case SYS_ID_AA64PFR1_EL1:       return read_cpuid(ID_AA64PFR0_EL1);
 877         case SYS_ID_AA64DFR0_EL1:       return read_cpuid(ID_AA64DFR0_EL1);
 878         case SYS_ID_AA64DFR1_EL1:       return read_cpuid(ID_AA64DFR0_EL1);
 879         case SYS_ID_AA64MMFR0_EL1:      return read_cpuid(ID_AA64MMFR0_EL1);
 880         case SYS_ID_AA64MMFR1_EL1:      return read_cpuid(ID_AA64MMFR1_EL1);
 881         case SYS_ID_AA64MMFR2_EL1:      return read_cpuid(ID_AA64MMFR2_EL1);
 882         case SYS_ID_AA64ISAR0_EL1:      return read_cpuid(ID_AA64ISAR0_EL1);
 883         case SYS_ID_AA64ISAR1_EL1:      return read_cpuid(ID_AA64ISAR1_EL1);
 884
 885         case SYS_CNTFRQ_EL0:            return read_cpuid(CNTFRQ_EL0);
 886         case SYS_CTR_EL0:               return read_cpuid(CTR_EL0);
 887         case SYS_DCZID_EL0:             return read_cpuid(DCZID_EL0);
 888         default:
 889                 BUG();
 890                 return 0;
 891         }
 892 }
 893
 894 /*
 895  * Check for CPU features that are used in early boot
 896  * based on the Boot CPU value.
 897  */
 898 static void check_early_cpu_features(void)
 899 {
 900         verify_cpu_asid_bits();
 901 }
 902
 903 /*
 904  * Run through the enabled system capabilities and enable() it on this CPU.
 905  * The capabilities were decided based on the available CPUs at the boot time.
 906  * Any new CPU should match the system wide status of the capability. If the
 907  * new CPU doesn't have a capability which the system now has enabled, we
 908  * cannot do anything to fix it up and could cause unexpected failures. So
 909  * we park the CPU.
 910  */
 911 void verify_local_cpu_capabilities(void)
 912 {
 913         int i;
 914         const struct arm64_cpu_capabilities *caps;
 915
 916         check_early_cpu_features();
 917
 918         /*
 919          * If we haven't computed the system capabilities, there is nothing
 920          * to verify.
 921          */
 922         if (!sys_caps_initialised)
 923                 return;
 924
 925         caps = arm64_features;
 926         for (i = 0; caps[i].matches; i++) {
 927                 if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg)
 928                         continue;
 929                 /*
 930                  * If the new CPU misses an advertised feature, we cannot proceed
 931                  * further, park the cpu.
 932                  */
 933                 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i])) {
 934                         pr_crit("CPU%d: missing feature: %s\n",
 935                                         smp_processor_id(), caps[i].desc);
 936                         cpu_die_early();
 937                 }
 938                 if (caps[i].enable)
 939                         caps[i].enable(NULL);
 940         }
 941
 942         for (i = 0, caps = arm64_hwcaps; caps[i].matches; i++) {
 943                 if (!cpus_have_hwcap(&caps[i]))
 944                         continue;
 945                 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i])) {
 946                         pr_crit("CPU%d: missing HWCAP: %s\n",
 947                                         smp_processor_id(), caps[i].desc);
 948                         cpu_die_early();
 949                 }
 950         }
 951 }
 952
 953 static void __init setup_feature_capabilities(void)
 954 {
 955         update_cpu_capabilities(arm64_features, "detected feature:");
 956         enable_cpu_capabilities(arm64_features);
 957 }
 958
 959 void __init setup_cpu_features(void)
 960 {
 961         u32 cwg;
 962         int cls;
 963
 964         /* Set the CPU feature capabilies */
 965         setup_feature_capabilities();
 966         setup_cpu_hwcaps();
 967
 968         /* Advertise that we have computed the system capabilities */
 969         set_sys_caps_initialised();
 970
 971         /*
 972          * Check for sane CTR_EL0.CWG value.
 973          */
 974         cwg = cache_type_cwg();
 975         cls = cache_line_size();
 976         if (!cwg)
 977                 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
 978                         cls);
 979         if (L1_CACHE_BYTES < cls)
 980                 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
 981                         L1_CACHE_BYTES, cls);
 982 }
 983
 984 static bool __maybe_unused
 985 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry)
 986 {
 987         return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO));
 988 }