arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/sort.h>
  23 #include <linux/types.h>
  24 #include <asm/cpu.h>
  25 #include <asm/cpufeature.h>
  26 #include <asm/cpu_ops.h>
  27 #include <asm/processor.h>
  28 #include <asm/sysreg.h>
  29 #include <asm/virt.h>
  30
  31 unsigned long elf_hwcap __read_mostly;
  32 EXPORT_SYMBOL_GPL(elf_hwcap);
  33
  34 #ifdef CONFIG_COMPAT
  35 #define COMPAT_ELF_HWCAP_DEFAULT        \
  36                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  37                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  38                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  39                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  40                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  41                                  COMPAT_HWCAP_LPAE)
  42 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  43 unsigned int compat_elf_hwcap2 __read_mostly;
  44 #endif
  45
  46 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  47
  48 #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  49         {                                               \
  50                 .sign = SIGNED,                         \
  51                 .strict = STRICT,                       \
  52                 .type = TYPE,                           \
  53                 .shift = SHIFT,                         \
  54                 .width = WIDTH,                         \
  55                 .safe_val = SAFE_VAL,                   \
  56         }
  57
  58 /* Define a feature with signed values */
  59 #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  60         __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  61
  62 /* Define a feature with unsigned value */
  63 #define U_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  64         __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  65
  66 #define ARM64_FTR_END                                   \
  67         {                                               \
  68                 .width = 0,                             \
  69         }
  70
  71 static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
  72         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  73         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
  74         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
  75         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
  76         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
  77         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
  78         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
  79         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
  80         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
  81         ARM64_FTR_END,
  82 };
  83
  84 static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
  85         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  86         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
  87         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
  88         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
  89         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
  90         /* Linux doesn't care about the EL3 */
  91         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
  92         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
  93         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
  94         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
  95         ARM64_FTR_END,
  96 };
  97
  98 static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
  99         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 100         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 101         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 102         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 103         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 104         /* Linux shouldn't care about secure memory */
 105         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 106         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 107         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 108         /*
 109          * Differing PARange is fine as long as all peripherals and memory are mapped
 110          * within the minimum PARange of all CPUs
 111          */
 112         U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 113         ARM64_FTR_END,
 114 };
 115
 116 static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 117         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 118         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 119         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 120         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 121         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 122         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 123         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 124         ARM64_FTR_END,
 125 };
 126
 127 static struct arm64_ftr_bits ftr_ctr[] = {
 128         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1),      /* RAO */
 129         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
 130         U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0),        /* CWG */
 131         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
 132         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
 133         /*
 134          * Linux can handle differing I-cache policies. Userspace JITs will
 135          * make use of *minLine
 136          */
 137         U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0),   /* L1Ip */
 138         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0),        /* RAZ */
 139         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),  /* IminLine */
 140         ARM64_FTR_END,
 141 };
 142
 143 static struct arm64_ftr_bits ftr_id_mmfr0[] = {
 144         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),        /* InnerShr */
 145         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),        /* FCSE */
 146         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),        /* AuxReg */
 147         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0),        /* TCM */
 148         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* ShareLvl */
 149         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* OuterShr */
 150         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
 151         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
 152         ARM64_FTR_END,
 153 };
 154
 155 static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 156         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 157         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 158         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 159         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 160         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 161         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 162         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 163         ARM64_FTR_END,
 164 };
 165
 166 static struct arm64_ftr_bits ftr_mvfr2[] = {
 167         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 168         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* FPMisc */
 169         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* SIMDMisc */
 170         ARM64_FTR_END,
 171 };
 172
 173 static struct arm64_ftr_bits ftr_dczid[] = {
 174         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0),        /* RAZ */
 175         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1),         /* DZP */
 176         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),    /* BS */
 177         ARM64_FTR_END,
 178 };
 179
 180
 181 static struct arm64_ftr_bits ftr_id_isar5[] = {
 182         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
 183         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0),        /* RAZ */
 184         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
 185         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
 186         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
 187         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
 188         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
 189         ARM64_FTR_END,
 190 };
 191
 192 static struct arm64_ftr_bits ftr_id_mmfr4[] = {
 193         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 194         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* ac2 */
 195         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* RAZ */
 196         ARM64_FTR_END,
 197 };
 198
 199 static struct arm64_ftr_bits ftr_id_pfr0[] = {
 200         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0),       /* RAZ */
 201         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* State3 */
 202         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0),         /* State2 */
 203         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* State1 */
 204         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* State0 */
 205         ARM64_FTR_END,
 206 };
 207
 208 /*
 209  * Common ftr bits for a 32bit register with all hidden, strict
 210  * attributes, with 4bit feature fields and a default safe value of
 211  * 0. Covers the following 32bit registers:
 212  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 213  */
 214 static struct arm64_ftr_bits ftr_generic_32bits[] = {
 215         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 216         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 217         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 218         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 219         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 220         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 221         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 222         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 223         ARM64_FTR_END,
 224 };
 225
 226 static struct arm64_ftr_bits ftr_generic[] = {
 227         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 228         ARM64_FTR_END,
 229 };
 230
 231 static struct arm64_ftr_bits ftr_generic32[] = {
 232         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
 233         ARM64_FTR_END,
 234 };
 235
 236 static struct arm64_ftr_bits ftr_aa64raz[] = {
 237         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 238         ARM64_FTR_END,
 239 };
 240
 241 #define ARM64_FTR_REG(id, table)                \
 242         {                                       \
 243                 .sys_id = id,                   \
 244                 .name = #id,                    \
 245                 .ftr_bits = &((table)[0]),      \
 246         }
 247
 248 static struct arm64_ftr_reg arm64_ftr_regs[] = {
 249
 250         /* Op1 = 0, CRn = 0, CRm = 1 */
 251         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 252         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 253         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_generic_32bits),
 254         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 255         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 256         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 257         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 258
 259         /* Op1 = 0, CRn = 0, CRm = 2 */
 260         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 261         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 262         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 263         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 264         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 265         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 266         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 267
 268         /* Op1 = 0, CRn = 0, CRm = 3 */
 269         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 270         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 271         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 272
 273         /* Op1 = 0, CRn = 0, CRm = 4 */
 274         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 275         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
 276
 277         /* Op1 = 0, CRn = 0, CRm = 5 */
 278         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 279         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
 280
 281         /* Op1 = 0, CRn = 0, CRm = 6 */
 282         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 283         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
 284
 285         /* Op1 = 0, CRn = 0, CRm = 7 */
 286         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 287         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 288
 289         /* Op1 = 3, CRn = 0, CRm = 0 */
 290         ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
 291         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 292
 293         /* Op1 = 3, CRn = 14, CRm = 0 */
 294         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
 295 };
 296
 297 static int search_cmp_ftr_reg(const void *id, const void *regp)
 298 {
 299         return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
 300 }
 301
 302 /*
 303  * get_arm64_ftr_reg - Lookup a feature register entry using its
 304  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 305  * ascending order of sys_id , we use binary search to find a matching
 306  * entry.
 307  *
 308  * returns - Upon success,  matching ftr_reg entry for id.
 309  *         - NULL on failure. It is upto the caller to decide
 310  *           the impact of a failure.
 311  */
 312 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 313 {
 314         return bsearch((const void *)(unsigned long)sys_id,
 315                         arm64_ftr_regs,
 316                         ARRAY_SIZE(arm64_ftr_regs),
 317                         sizeof(arm64_ftr_regs[0]),
 318                         search_cmp_ftr_reg);
 319 }
 320
 321 static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
 322 {
 323         u64 mask = arm64_ftr_mask(ftrp);
 324
 325         reg &= ~mask;
 326         reg |= (ftr_val << ftrp->shift) & mask;
 327         return reg;
 328 }
 329
 330 static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
 331 {
 332         s64 ret = 0;
 333
 334         switch (ftrp->type) {
 335         case FTR_EXACT:
 336                 ret = ftrp->safe_val;
 337                 break;
 338         case FTR_LOWER_SAFE:
 339                 ret = new < cur ? new : cur;
 340                 break;
 341         case FTR_HIGHER_SAFE:
 342                 ret = new > cur ? new : cur;
 343                 break;
 344         default:
 345                 BUG();
 346         }
 347
 348         return ret;
 349 }
 350
 351 static int __init sort_cmp_ftr_regs(const void *a, const void *b)
 352 {
 353         return ((const struct arm64_ftr_reg *)a)->sys_id -
 354                  ((const struct arm64_ftr_reg *)b)->sys_id;
 355 }
 356
 357 static void __init swap_ftr_regs(void *a, void *b, int size)
 358 {
 359         struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
 360         *(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
 361         *(struct arm64_ftr_reg *)b = tmp;
 362 }
 363
 364 static void __init sort_ftr_regs(void)
 365 {
 366         /* Keep the array sorted so that we can do the binary search */
 367         sort(arm64_ftr_regs,
 368                 ARRAY_SIZE(arm64_ftr_regs),
 369                 sizeof(arm64_ftr_regs[0]),
 370                 sort_cmp_ftr_regs,
 371                 swap_ftr_regs);
 372 }
 373
 374 /*
 375  * Initialise the CPU feature register from Boot CPU values.
 376  * Also initiliases the strict_mask for the register.
 377  */
 378 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 379 {
 380         u64 val = 0;
 381         u64 strict_mask = ~0x0ULL;
 382         struct arm64_ftr_bits *ftrp;
 383         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 384
 385         BUG_ON(!reg);
 386
 387         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 388                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 389
 390                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 391                 if (!ftrp->strict)
 392                         strict_mask &= ~arm64_ftr_mask(ftrp);
 393         }
 394         reg->sys_val = val;
 395         reg->strict_mask = strict_mask;
 396 }
 397
 398 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 399 {
 400         /* Before we start using the tables, make sure it is sorted */
 401         sort_ftr_regs();
 402
 403         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 404         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 405         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 406         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 407         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 408         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 409         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 410         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 411         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 412         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 413         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 414         init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 415         init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 416         init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 417         init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 418         init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 419         init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 420         init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 421         init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 422         init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 423         init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 424         init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 425         init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 426         init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 427         init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 428         init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 429         init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 430 }
 431
 432 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 433 {
 434         struct arm64_ftr_bits *ftrp;
 435
 436         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 437                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 438                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 439
 440                 if (ftr_cur == ftr_new)
 441                         continue;
 442                 /* Find a safe value */
 443                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 444                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 445         }
 446
 447 }
 448
 449 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 450 {
 451         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 452
 453         BUG_ON(!regp);
 454         update_cpu_ftr_reg(regp, val);
 455         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 456                 return 0;
 457         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 458                         regp->name, boot, cpu, val);
 459         return 1;
 460 }
 461
 462 /*
 463  * Update system wide CPU feature registers with the values from a
 464  * non-boot CPU. Also performs SANITY checks to make sure that there
 465  * aren't any insane variations from that of the boot CPU.
 466  */
 467 void update_cpu_features(int cpu,
 468                          struct cpuinfo_arm64 *info,
 469                          struct cpuinfo_arm64 *boot)
 470 {
 471         int taint = 0;
 472
 473         /*
 474          * The kernel can handle differing I-cache policies, but otherwise
 475          * caches should look identical. Userspace JITs will make use of
 476          * *minLine.
 477          */
 478         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 479                                       info->reg_ctr, boot->reg_ctr);
 480
 481         /*
 482          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 483          * could result in too much or too little memory being zeroed if a
 484          * process is preempted and migrated between CPUs.
 485          */
 486         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 487                                       info->reg_dczid, boot->reg_dczid);
 488
 489         /* If different, timekeeping will be broken (especially with KVM) */
 490         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 491                                       info->reg_cntfrq, boot->reg_cntfrq);
 492
 493         /*
 494          * The kernel uses self-hosted debug features and expects CPUs to
 495          * support identical debug features. We presently need CTX_CMPs, WRPs,
 496          * and BRPs to be identical.
 497          * ID_AA64DFR1 is currently RES0.
 498          */
 499         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 500                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 501         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 502                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 503         /*
 504          * Even in big.LITTLE, processors should be identical instruction-set
 505          * wise.
 506          */
 507         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 508                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 509         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 510                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 511
 512         /*
 513          * Differing PARange support is fine as long as all peripherals and
 514          * memory are mapped within the minimum PARange of all CPUs.
 515          * Linux should not care about secure memory.
 516          */
 517         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 518                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 519         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 520                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 521
 522         /*
 523          * EL3 is not our concern.
 524          * ID_AA64PFR1 is currently RES0.
 525          */
 526         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 527                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 528         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 529                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 530
 531         /*
 532          * If we have AArch32, we care about 32-bit features for compat. These
 533          * registers should be RES0 otherwise.
 534          */
 535         taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 536                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 537         taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 538                                         info->reg_id_isar0, boot->reg_id_isar0);
 539         taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 540                                         info->reg_id_isar1, boot->reg_id_isar1);
 541         taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 542                                         info->reg_id_isar2, boot->reg_id_isar2);
 543         taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 544                                         info->reg_id_isar3, boot->reg_id_isar3);
 545         taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 546                                         info->reg_id_isar4, boot->reg_id_isar4);
 547         taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 548                                         info->reg_id_isar5, boot->reg_id_isar5);
 549
 550         /*
 551          * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 552          * ACTLR formats could differ across CPUs and therefore would have to
 553          * be trapped for virtualization anyway.
 554          */
 555         taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 556                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 557         taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 558                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 559         taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 560                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 561         taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 562                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 563         taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 564                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 565         taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 566                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 567         taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 568                                         info->reg_mvfr0, boot->reg_mvfr0);
 569         taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 570                                         info->reg_mvfr1, boot->reg_mvfr1);
 571         taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 572                                         info->reg_mvfr2, boot->reg_mvfr2);
 573
 574         /*
 575          * Mismatched CPU features are a recipe for disaster. Don't even
 576          * pretend to support them.
 577          */
 578         WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
 579                         "Unsupported CPU feature variation.\n");
 580 }
 581
 582 u64 read_system_reg(u32 id)
 583 {
 584         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 585
 586         /* We shouldn't get a request for an unsupported register */
 587         BUG_ON(!regp);
 588         return regp->sys_val;
 589 }
 590
 591 #include <linux/irqchip/arm-gic-v3.h>
 592
 593 static bool
 594 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 595 {
 596         int val = cpuid_feature_extract_field(reg, entry->field_pos);
 597
 598         return val >= entry->min_field_value;
 599 }
 600
 601 static bool
 602 has_cpuid_feature(const struct arm64_cpu_capabilities *entry)
 603 {
 604         u64 val;
 605
 606         val = read_system_reg(entry->sys_reg);
 607         return feature_matches(val, entry);
 608 }
 609
 610 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
 611 {
 612         bool has_sre;
 613
 614         if (!has_cpuid_feature(entry))
 615                 return false;
 616
 617         has_sre = gic_enable_sre();
 618         if (!has_sre)
 619                 pr_warn_once("%s present but disabled by higher exception level\n",
 620                              entry->desc);
 621
 622         return has_sre;
 623 }
 624
 625 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry)
 626 {
 627         return is_kernel_in_hyp_mode();
 628 }
 629
 630 static const struct arm64_cpu_capabilities arm64_features[] = {
 631         {
 632                 .desc = "GIC system register CPU interface",
 633                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
 634                 .matches = has_useable_gicv3_cpuif,
 635                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 636                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
 637                 .min_field_value = 1,
 638         },
 639 #ifdef CONFIG_ARM64_PAN
 640         {
 641                 .desc = "Privileged Access Never",
 642                 .capability = ARM64_HAS_PAN,
 643                 .matches = has_cpuid_feature,
 644                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
 645                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
 646                 .min_field_value = 1,
 647                 .enable = cpu_enable_pan,
 648         },
 649 #endif /* CONFIG_ARM64_PAN */
 650 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
 651         {
 652                 .desc = "LSE atomic instructions",
 653                 .capability = ARM64_HAS_LSE_ATOMICS,
 654                 .matches = has_cpuid_feature,
 655                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
 656                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
 657                 .min_field_value = 2,
 658         },
 659 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
 660         {
 661                 .desc = "Virtualization Host Extensions",
 662                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
 663                 .matches = runs_at_el2,
 664         },
 665         {},
 666 };
 667
 668 #define HWCAP_CAP(reg, field, min_value, type, cap)             \
 669         {                                                       \
 670                 .desc = #cap,                                   \
 671                 .matches = has_cpuid_feature,                   \
 672                 .sys_reg = reg,                                 \
 673                 .field_pos = field,                             \
 674                 .min_field_value = min_value,                   \
 675                 .hwcap_type = type,                             \
 676                 .hwcap = cap,                                   \
 677         }
 678
 679 static const struct arm64_cpu_capabilities arm64_hwcaps[] = {
 680         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 2, CAP_HWCAP, HWCAP_PMULL),
 681         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 1, CAP_HWCAP, HWCAP_AES),
 682         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, 1, CAP_HWCAP, HWCAP_SHA1),
 683         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 1, CAP_HWCAP, HWCAP_SHA2),
 684         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, 1, CAP_HWCAP, HWCAP_CRC32),
 685         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, 2, CAP_HWCAP, HWCAP_ATOMICS),
 686         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 0, CAP_HWCAP, HWCAP_FP),
 687         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 0, CAP_HWCAP, HWCAP_ASIMD),
 688 #ifdef CONFIG_COMPAT
 689         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
 690         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
 691         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
 692         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
 693         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
 694 #endif
 695         {},
 696 };
 697
 698 static void __init cap_set_hwcap(const struct arm64_cpu_capabilities *cap)
 699 {
 700         switch (cap->hwcap_type) {
 701         case CAP_HWCAP:
 702                 elf_hwcap |= cap->hwcap;
 703                 break;
 704 #ifdef CONFIG_COMPAT
 705         case CAP_COMPAT_HWCAP:
 706                 compat_elf_hwcap |= (u32)cap->hwcap;
 707                 break;
 708         case CAP_COMPAT_HWCAP2:
 709                 compat_elf_hwcap2 |= (u32)cap->hwcap;
 710                 break;
 711 #endif
 712         default:
 713                 WARN_ON(1);
 714                 break;
 715         }
 716 }
 717
 718 /* Check if we have a particular HWCAP enabled */
 719 static bool __maybe_unused cpus_have_hwcap(const struct arm64_cpu_capabilities *cap)
 720 {
 721         bool rc;
 722
 723         switch (cap->hwcap_type) {
 724         case CAP_HWCAP:
 725                 rc = (elf_hwcap & cap->hwcap) != 0;
 726                 break;
 727 #ifdef CONFIG_COMPAT
 728         case CAP_COMPAT_HWCAP:
 729                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
 730                 break;
 731         case CAP_COMPAT_HWCAP2:
 732                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
 733                 break;
 734 #endif
 735         default:
 736                 WARN_ON(1);
 737                 rc = false;
 738         }
 739
 740         return rc;
 741 }
 742
 743 static void __init setup_cpu_hwcaps(void)
 744 {
 745         int i;
 746         const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps;
 747
 748         for (i = 0; hwcaps[i].desc; i++)
 749                 if (hwcaps[i].matches(&hwcaps[i]))
 750                         cap_set_hwcap(&hwcaps[i]);
 751 }
 752
 753 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
 754                             const char *info)
 755 {
 756         int i;
 757
 758         for (i = 0; caps[i].desc; i++) {
 759                 if (!caps[i].matches(&caps[i]))
 760                         continue;
 761
 762                 if (!cpus_have_cap(caps[i].capability))
 763                         pr_info("%s %s\n", info, caps[i].desc);
 764                 cpus_set_cap(caps[i].capability);
 765         }
 766 }
 767
 768 /*
 769  * Run through the enabled capabilities and enable() it on all active
 770  * CPUs
 771  */
 772 static void __init
 773 enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
 774 {
 775         int i;
 776
 777         for (i = 0; caps[i].desc; i++)
 778                 if (caps[i].enable && cpus_have_cap(caps[i].capability))
 779                         on_each_cpu(caps[i].enable, NULL, true);
 780 }
 781
 782 #ifdef CONFIG_HOTPLUG_CPU
 783
 784 /*
 785  * Flag to indicate if we have computed the system wide
 786  * capabilities based on the boot time active CPUs. This
 787  * will be used to determine if a new booting CPU should
 788  * go through the verification process to make sure that it
 789  * supports the system capabilities, without using a hotplug
 790  * notifier.
 791  */
 792 static bool sys_caps_initialised;
 793
 794 static inline void set_sys_caps_initialised(void)
 795 {
 796         sys_caps_initialised = true;
 797 }
 798
 799 /*
 800  * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
 801  */
 802 static u64 __raw_read_system_reg(u32 sys_id)
 803 {
 804         switch (sys_id) {
 805         case SYS_ID_PFR0_EL1:           return (u64)read_cpuid(ID_PFR0_EL1);
 806         case SYS_ID_PFR1_EL1:           return (u64)read_cpuid(ID_PFR1_EL1);
 807         case SYS_ID_DFR0_EL1:           return (u64)read_cpuid(ID_DFR0_EL1);
 808         case SYS_ID_MMFR0_EL1:          return (u64)read_cpuid(ID_MMFR0_EL1);
 809         case SYS_ID_MMFR1_EL1:          return (u64)read_cpuid(ID_MMFR1_EL1);
 810         case SYS_ID_MMFR2_EL1:          return (u64)read_cpuid(ID_MMFR2_EL1);
 811         case SYS_ID_MMFR3_EL1:          return (u64)read_cpuid(ID_MMFR3_EL1);
 812         case SYS_ID_ISAR0_EL1:          return (u64)read_cpuid(ID_ISAR0_EL1);
 813         case SYS_ID_ISAR1_EL1:          return (u64)read_cpuid(ID_ISAR1_EL1);
 814         case SYS_ID_ISAR2_EL1:          return (u64)read_cpuid(ID_ISAR2_EL1);
 815         case SYS_ID_ISAR3_EL1:          return (u64)read_cpuid(ID_ISAR3_EL1);
 816         case SYS_ID_ISAR4_EL1:          return (u64)read_cpuid(ID_ISAR4_EL1);
 817         case SYS_ID_ISAR5_EL1:          return (u64)read_cpuid(ID_ISAR4_EL1);
 818         case SYS_MVFR0_EL1:             return (u64)read_cpuid(MVFR0_EL1);
 819         case SYS_MVFR1_EL1:             return (u64)read_cpuid(MVFR1_EL1);
 820         case SYS_MVFR2_EL1:             return (u64)read_cpuid(MVFR2_EL1);
 821
 822         case SYS_ID_AA64PFR0_EL1:       return (u64)read_cpuid(ID_AA64PFR0_EL1);
 823         case SYS_ID_AA64PFR1_EL1:       return (u64)read_cpuid(ID_AA64PFR0_EL1);
 824         case SYS_ID_AA64DFR0_EL1:       return (u64)read_cpuid(ID_AA64DFR0_EL1);
 825         case SYS_ID_AA64DFR1_EL1:       return (u64)read_cpuid(ID_AA64DFR0_EL1);
 826         case SYS_ID_AA64MMFR0_EL1:      return (u64)read_cpuid(ID_AA64MMFR0_EL1);
 827         case SYS_ID_AA64MMFR1_EL1:      return (u64)read_cpuid(ID_AA64MMFR1_EL1);
 828         case SYS_ID_AA64ISAR0_EL1:      return (u64)read_cpuid(ID_AA64ISAR0_EL1);
 829         case SYS_ID_AA64ISAR1_EL1:      return (u64)read_cpuid(ID_AA64ISAR1_EL1);
 830
 831         case SYS_CNTFRQ_EL0:            return (u64)read_cpuid(CNTFRQ_EL0);
 832         case SYS_CTR_EL0:               return (u64)read_cpuid(CTR_EL0);
 833         case SYS_DCZID_EL0:             return (u64)read_cpuid(DCZID_EL0);
 834         default:
 835                 BUG();
 836                 return 0;
 837         }
 838 }
 839
 840 /*
 841  * Park the CPU which doesn't have the capability as advertised
 842  * by the system.
 843  */
 844 static void fail_incapable_cpu(char *cap_type,
 845                                  const struct arm64_cpu_capabilities *cap)
 846 {
 847         int cpu = smp_processor_id();
 848
 849         pr_crit("CPU%d: missing %s : %s\n", cpu, cap_type, cap->desc);
 850         /* Mark this CPU absent */
 851         set_cpu_present(cpu, 0);
 852
 853         /* Check if we can park ourselves */
 854         if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die)
 855                 cpu_ops[cpu]->cpu_die(cpu);
 856         asm(
 857         "1:     wfe\n"
 858         "       wfi\n"
 859         "       b       1b");
 860 }
 861
 862 /*
 863  * Run through the enabled system capabilities and enable() it on this CPU.
 864  * The capabilities were decided based on the available CPUs at the boot time.
 865  * Any new CPU should match the system wide status of the capability. If the
 866  * new CPU doesn't have a capability which the system now has enabled, we
 867  * cannot do anything to fix it up and could cause unexpected failures. So
 868  * we park the CPU.
 869  */
 870 void verify_local_cpu_capabilities(void)
 871 {
 872         int i;
 873         const struct arm64_cpu_capabilities *caps;
 874
 875         /*
 876          * If we haven't computed the system capabilities, there is nothing
 877          * to verify.
 878          */
 879         if (!sys_caps_initialised)
 880                 return;
 881
 882         caps = arm64_features;
 883         for (i = 0; caps[i].desc; i++) {
 884                 if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg)
 885                         continue;
 886                 /*
 887                  * If the new CPU misses an advertised feature, we cannot proceed
 888                  * further, park the cpu.
 889                  */
 890                 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
 891                         fail_incapable_cpu("arm64_features", &caps[i]);
 892                 if (caps[i].enable)
 893                         caps[i].enable(NULL);
 894         }
 895
 896         for (i = 0, caps = arm64_hwcaps; caps[i].desc; i++) {
 897                 if (!cpus_have_hwcap(&caps[i]))
 898                         continue;
 899                 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
 900                         fail_incapable_cpu("arm64_hwcaps", &caps[i]);
 901         }
 902 }
 903
 904 #else   /* !CONFIG_HOTPLUG_CPU */
 905
 906 static inline void set_sys_caps_initialised(void)
 907 {
 908 }
 909
 910 #endif  /* CONFIG_HOTPLUG_CPU */
 911
 912 static void __init setup_feature_capabilities(void)
 913 {
 914         update_cpu_capabilities(arm64_features, "detected feature:");
 915         enable_cpu_capabilities(arm64_features);
 916 }
 917
 918 void __init setup_cpu_features(void)
 919 {
 920         u32 cwg;
 921         int cls;
 922
 923         /* Set the CPU feature capabilies */
 924         setup_feature_capabilities();
 925         setup_cpu_hwcaps();
 926
 927         /* Advertise that we have computed the system capabilities */
 928         set_sys_caps_initialised();
 929
 930         /*
 931          * Check for sane CTR_EL0.CWG value.
 932          */
 933         cwg = cache_type_cwg();
 934         cls = cache_line_size();
 935         if (!cwg)
 936                 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
 937                         cls);
 938         if (L1_CACHE_BYTES < cls)
 939                 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
 940                         L1_CACHE_BYTES, cls);
 941 }