arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/sort.h>
  23 #include <linux/types.h>
  24 #include <asm/cpu.h>
  25 #include <asm/cpufeature.h>
  26 #include <asm/cpu_ops.h>
  27 #include <asm/mmu_context.h>
  28 #include <asm/processor.h>
  29 #include <asm/sysreg.h>
  30 #include <asm/virt.h>
  31
  32 unsigned long elf_hwcap __read_mostly;
  33 EXPORT_SYMBOL_GPL(elf_hwcap);
  34
  35 #ifdef CONFIG_COMPAT
  36 #define COMPAT_ELF_HWCAP_DEFAULT        \
  37                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  38                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  39                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  40                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  41                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  42                                  COMPAT_HWCAP_LPAE)
  43 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  44 unsigned int compat_elf_hwcap2 __read_mostly;
  45 #endif
  46
  47 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  48
  49 #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  50         {                                               \
  51                 .sign = SIGNED,                         \
  52                 .strict = STRICT,                       \
  53                 .type = TYPE,                           \
  54                 .shift = SHIFT,                         \
  55                 .width = WIDTH,                         \
  56                 .safe_val = SAFE_VAL,                   \
  57         }
  58
  59 /* Define a feature with unsigned values */
  60 #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  61         __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  62
  63 /* Define a feature with a signed value */
  64 #define S_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  65         __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  66
  67 #define ARM64_FTR_END                                   \
  68         {                                               \
  69                 .width = 0,                             \
  70         }
  71
  72 /* meta feature for alternatives */
  73 static bool __maybe_unused
  74 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
  75
  76
  77 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
  78         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  79         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
  80         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
  81         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
  82         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
  83         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
  84         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
  85         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
  86         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
  87         ARM64_FTR_END,
  88 };
  89
  90 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
  91         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  92         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
  93         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
  94         S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
  95         S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
  96         /* Linux doesn't care about the EL3 */
  97         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
  98         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
  99         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 100         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 101         ARM64_FTR_END,
 102 };
 103
 104 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 105         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 106         S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 107         S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 108         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 109         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 110         /* Linux shouldn't care about secure memory */
 111         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 112         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 113         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 114         /*
 115          * Differing PARange is fine as long as all peripherals and memory are mapped
 116          * within the minimum PARange of all CPUs
 117          */
 118         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 119         ARM64_FTR_END,
 120 };
 121
 122 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 123         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 124         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 125         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 126         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 127         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 128         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 129         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 130         ARM64_FTR_END,
 131 };
 132
 133 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 134         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 135         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 136         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 137         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 138         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 139         ARM64_FTR_END,
 140 };
 141
 142 static const struct arm64_ftr_bits ftr_ctr[] = {
 143         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1),        /* RAO */
 144         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
 145         ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0),  /* CWG */
 146         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),   /* ERG */
 147         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1),   /* DminLine */
 148         /*
 149          * Linux can handle differing I-cache policies. Userspace JITs will
 150          * make use of *minLine
 151          */
 152         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0),     /* L1Ip */
 153         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0),        /* RAZ */
 154         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),    /* IminLine */
 155         ARM64_FTR_END,
 156 };
 157
 158 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 159         S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0xf),    /* InnerShr */
 160         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),        /* FCSE */
 161         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),        /* AuxReg */
 162         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0),        /* TCM */
 163         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* ShareLvl */
 164         S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0xf),     /* OuterShr */
 165         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
 166         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
 167         ARM64_FTR_END,
 168 };
 169
 170 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 171         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 172         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 173         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 174         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 175         S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 176         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 177         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 178         ARM64_FTR_END,
 179 };
 180
 181 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 182         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 183         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* FPMisc */
 184         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* SIMDMisc */
 185         ARM64_FTR_END,
 186 };
 187
 188 static const struct arm64_ftr_bits ftr_dczid[] = {
 189         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0),        /* RAZ */
 190         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1),         /* DZP */
 191         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),    /* BS */
 192         ARM64_FTR_END,
 193 };
 194
 195
 196 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 197         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
 198         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0),        /* RAZ */
 199         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
 200         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
 201         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
 202         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
 203         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
 204         ARM64_FTR_END,
 205 };
 206
 207 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 208         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 209         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* ac2 */
 210         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* RAZ */
 211         ARM64_FTR_END,
 212 };
 213
 214 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 215         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0),       /* RAZ */
 216         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* State3 */
 217         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0),         /* State2 */
 218         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* State1 */
 219         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* State0 */
 220         ARM64_FTR_END,
 221 };
 222
 223 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 224         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 225         S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),       /* PerfMon */
 226         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 227         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 228         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 229         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 230         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 231         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 232         ARM64_FTR_END,
 233 };
 234
 235 /*
 236  * Common ftr bits for a 32bit register with all hidden, strict
 237  * attributes, with 4bit feature fields and a default safe value of
 238  * 0. Covers the following 32bit registers:
 239  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 240  */
 241 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 242         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 243         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 244         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 245         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 246         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 247         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 248         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 249         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 250         ARM64_FTR_END,
 251 };
 252
 253 static const struct arm64_ftr_bits ftr_generic[] = {
 254         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 255         ARM64_FTR_END,
 256 };
 257
 258 static const struct arm64_ftr_bits ftr_generic32[] = {
 259         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
 260         ARM64_FTR_END,
 261 };
 262
 263 static const struct arm64_ftr_bits ftr_aa64raz[] = {
 264         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 265         ARM64_FTR_END,
 266 };
 267
 268 #define ARM64_FTR_REG(id, table) {              \
 269         .sys_id = id,                           \
 270         .reg =  &(struct arm64_ftr_reg){        \
 271                 .name = #id,                    \
 272                 .ftr_bits = &((table)[0]),      \
 273         }}
 274
 275 static const struct __ftr_reg_entry {
 276         u32                     sys_id;
 277         struct arm64_ftr_reg    *reg;
 278 } arm64_ftr_regs[] = {
 279
 280         /* Op1 = 0, CRn = 0, CRm = 1 */
 281         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 282         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 283         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 284         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 285         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 286         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 287         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 288
 289         /* Op1 = 0, CRn = 0, CRm = 2 */
 290         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 291         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 292         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 293         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 294         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 295         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 296         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 297
 298         /* Op1 = 0, CRn = 0, CRm = 3 */
 299         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 300         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 301         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 302
 303         /* Op1 = 0, CRn = 0, CRm = 4 */
 304         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 305         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
 306
 307         /* Op1 = 0, CRn = 0, CRm = 5 */
 308         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 309         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
 310
 311         /* Op1 = 0, CRn = 0, CRm = 6 */
 312         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 313         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
 314
 315         /* Op1 = 0, CRn = 0, CRm = 7 */
 316         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 317         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 318         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 319
 320         /* Op1 = 3, CRn = 0, CRm = 0 */
 321         ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
 322         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 323
 324         /* Op1 = 3, CRn = 14, CRm = 0 */
 325         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
 326 };
 327
 328 static int search_cmp_ftr_reg(const void *id, const void *regp)
 329 {
 330         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 331 }
 332
 333 /*
 334  * get_arm64_ftr_reg - Lookup a feature register entry using its
 335  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 336  * ascending order of sys_id , we use binary search to find a matching
 337  * entry.
 338  *
 339  * returns - Upon success,  matching ftr_reg entry for id.
 340  *         - NULL on failure. It is upto the caller to decide
 341  *           the impact of a failure.
 342  */
 343 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 344 {
 345         const struct __ftr_reg_entry *ret;
 346
 347         ret = bsearch((const void *)(unsigned long)sys_id,
 348                         arm64_ftr_regs,
 349                         ARRAY_SIZE(arm64_ftr_regs),
 350                         sizeof(arm64_ftr_regs[0]),
 351                         search_cmp_ftr_reg);
 352         if (ret)
 353                 return ret->reg;
 354         return NULL;
 355 }
 356
 357 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 358                                s64 ftr_val)
 359 {
 360         u64 mask = arm64_ftr_mask(ftrp);
 361
 362         reg &= ~mask;
 363         reg |= (ftr_val << ftrp->shift) & mask;
 364         return reg;
 365 }
 366
 367 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 368                                 s64 cur)
 369 {
 370         s64 ret = 0;
 371
 372         switch (ftrp->type) {
 373         case FTR_EXACT:
 374                 ret = ftrp->safe_val;
 375                 break;
 376         case FTR_LOWER_SAFE:
 377                 ret = new < cur ? new : cur;
 378                 break;
 379         case FTR_HIGHER_SAFE:
 380                 ret = new > cur ? new : cur;
 381                 break;
 382         default:
 383                 BUG();
 384         }
 385
 386         return ret;
 387 }
 388
 389 static void __init sort_ftr_regs(void)
 390 {
 391         int i;
 392
 393         /* Check that the array is sorted so that we can do the binary search */
 394         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 395                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 396 }
 397
 398 /*
 399  * Initialise the CPU feature register from Boot CPU values.
 400  * Also initiliases the strict_mask for the register.
 401  */
 402 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 403 {
 404         u64 val = 0;
 405         u64 strict_mask = ~0x0ULL;
 406         const struct arm64_ftr_bits *ftrp;
 407         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 408
 409         BUG_ON(!reg);
 410
 411         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 412                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 413
 414                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 415                 if (!ftrp->strict)
 416                         strict_mask &= ~arm64_ftr_mask(ftrp);
 417         }
 418         reg->sys_val = val;
 419         reg->strict_mask = strict_mask;
 420 }
 421
 422 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 423 {
 424         /* Before we start using the tables, make sure it is sorted */
 425         sort_ftr_regs();
 426
 427         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 428         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 429         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 430         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 431         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 432         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 433         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 434         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 435         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 436         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 437         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 438         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 439
 440         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 441                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 442                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 443                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 444                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 445                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 446                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 447                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 448                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 449                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 450                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 451                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 452                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 453                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 454                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 455                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 456                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 457         }
 458
 459 }
 460
 461 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 462 {
 463         const struct arm64_ftr_bits *ftrp;
 464
 465         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 466                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 467                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 468
 469                 if (ftr_cur == ftr_new)
 470                         continue;
 471                 /* Find a safe value */
 472                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 473                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 474         }
 475
 476 }
 477
 478 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 479 {
 480         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 481
 482         BUG_ON(!regp);
 483         update_cpu_ftr_reg(regp, val);
 484         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 485                 return 0;
 486         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 487                         regp->name, boot, cpu, val);
 488         return 1;
 489 }
 490
 491 /*
 492  * Update system wide CPU feature registers with the values from a
 493  * non-boot CPU. Also performs SANITY checks to make sure that there
 494  * aren't any insane variations from that of the boot CPU.
 495  */
 496 void update_cpu_features(int cpu,
 497                          struct cpuinfo_arm64 *info,
 498                          struct cpuinfo_arm64 *boot)
 499 {
 500         int taint = 0;
 501
 502         /*
 503          * The kernel can handle differing I-cache policies, but otherwise
 504          * caches should look identical. Userspace JITs will make use of
 505          * *minLine.
 506          */
 507         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 508                                       info->reg_ctr, boot->reg_ctr);
 509
 510         /*
 511          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 512          * could result in too much or too little memory being zeroed if a
 513          * process is preempted and migrated between CPUs.
 514          */
 515         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 516                                       info->reg_dczid, boot->reg_dczid);
 517
 518         /* If different, timekeeping will be broken (especially with KVM) */
 519         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 520                                       info->reg_cntfrq, boot->reg_cntfrq);
 521
 522         /*
 523          * The kernel uses self-hosted debug features and expects CPUs to
 524          * support identical debug features. We presently need CTX_CMPs, WRPs,
 525          * and BRPs to be identical.
 526          * ID_AA64DFR1 is currently RES0.
 527          */
 528         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 529                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 530         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 531                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 532         /*
 533          * Even in big.LITTLE, processors should be identical instruction-set
 534          * wise.
 535          */
 536         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 537                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 538         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 539                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 540
 541         /*
 542          * Differing PARange support is fine as long as all peripherals and
 543          * memory are mapped within the minimum PARange of all CPUs.
 544          * Linux should not care about secure memory.
 545          */
 546         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 547                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 548         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 549                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 550         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 551                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 552
 553         /*
 554          * EL3 is not our concern.
 555          * ID_AA64PFR1 is currently RES0.
 556          */
 557         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 558                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 559         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 560                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 561
 562         /*
 563          * If we have AArch32, we care about 32-bit features for compat.
 564          * If the system doesn't support AArch32, don't update them.
 565          */
 566         if (id_aa64pfr0_32bit_el0(read_system_reg(SYS_ID_AA64PFR0_EL1)) &&
 567                 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 568
 569                 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 570                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 571                 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 572                                         info->reg_id_isar0, boot->reg_id_isar0);
 573                 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 574                                         info->reg_id_isar1, boot->reg_id_isar1);
 575                 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 576                                         info->reg_id_isar2, boot->reg_id_isar2);
 577                 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 578                                         info->reg_id_isar3, boot->reg_id_isar3);
 579                 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 580                                         info->reg_id_isar4, boot->reg_id_isar4);
 581                 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 582                                         info->reg_id_isar5, boot->reg_id_isar5);
 583
 584                 /*
 585                  * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 586                  * ACTLR formats could differ across CPUs and therefore would have to
 587                  * be trapped for virtualization anyway.
 588                  */
 589                 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 590                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 591                 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 592                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 593                 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 594                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 595                 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 596                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 597                 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 598                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 599                 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 600                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 601                 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 602                                         info->reg_mvfr0, boot->reg_mvfr0);
 603                 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 604                                         info->reg_mvfr1, boot->reg_mvfr1);
 605                 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 606                                         info->reg_mvfr2, boot->reg_mvfr2);
 607         }
 608
 609         /*
 610          * Mismatched CPU features are a recipe for disaster. Don't even
 611          * pretend to support them.
 612          */
 613         WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
 614                         "Unsupported CPU feature variation.\n");
 615 }
 616
 617 u64 read_system_reg(u32 id)
 618 {
 619         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 620
 621         /* We shouldn't get a request for an unsupported register */
 622         BUG_ON(!regp);
 623         return regp->sys_val;
 624 }
 625
 626 /*
 627  * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
 628  * Read the system register on the current CPU
 629  */
 630 static u64 __raw_read_system_reg(u32 sys_id)
 631 {
 632         switch (sys_id) {
 633         case SYS_ID_PFR0_EL1:           return read_cpuid(ID_PFR0_EL1);
 634         case SYS_ID_PFR1_EL1:           return read_cpuid(ID_PFR1_EL1);
 635         case SYS_ID_DFR0_EL1:           return read_cpuid(ID_DFR0_EL1);
 636         case SYS_ID_MMFR0_EL1:          return read_cpuid(ID_MMFR0_EL1);
 637         case SYS_ID_MMFR1_EL1:          return read_cpuid(ID_MMFR1_EL1);
 638         case SYS_ID_MMFR2_EL1:          return read_cpuid(ID_MMFR2_EL1);
 639         case SYS_ID_MMFR3_EL1:          return read_cpuid(ID_MMFR3_EL1);
 640         case SYS_ID_ISAR0_EL1:          return read_cpuid(ID_ISAR0_EL1);
 641         case SYS_ID_ISAR1_EL1:          return read_cpuid(ID_ISAR1_EL1);
 642         case SYS_ID_ISAR2_EL1:          return read_cpuid(ID_ISAR2_EL1);
 643         case SYS_ID_ISAR3_EL1:          return read_cpuid(ID_ISAR3_EL1);
 644         case SYS_ID_ISAR4_EL1:          return read_cpuid(ID_ISAR4_EL1);
 645         case SYS_ID_ISAR5_EL1:          return read_cpuid(ID_ISAR4_EL1);
 646         case SYS_MVFR0_EL1:             return read_cpuid(MVFR0_EL1);
 647         case SYS_MVFR1_EL1:             return read_cpuid(MVFR1_EL1);
 648         case SYS_MVFR2_EL1:             return read_cpuid(MVFR2_EL1);
 649
 650         case SYS_ID_AA64PFR0_EL1:       return read_cpuid(ID_AA64PFR0_EL1);
 651         case SYS_ID_AA64PFR1_EL1:       return read_cpuid(ID_AA64PFR0_EL1);
 652         case SYS_ID_AA64DFR0_EL1:       return read_cpuid(ID_AA64DFR0_EL1);
 653         case SYS_ID_AA64DFR1_EL1:       return read_cpuid(ID_AA64DFR0_EL1);
 654         case SYS_ID_AA64MMFR0_EL1:      return read_cpuid(ID_AA64MMFR0_EL1);
 655         case SYS_ID_AA64MMFR1_EL1:      return read_cpuid(ID_AA64MMFR1_EL1);
 656         case SYS_ID_AA64MMFR2_EL1:      return read_cpuid(ID_AA64MMFR2_EL1);
 657         case SYS_ID_AA64ISAR0_EL1:      return read_cpuid(ID_AA64ISAR0_EL1);
 658         case SYS_ID_AA64ISAR1_EL1:      return read_cpuid(ID_AA64ISAR1_EL1);
 659
 660         case SYS_CNTFRQ_EL0:            return read_cpuid(CNTFRQ_EL0);
 661         case SYS_CTR_EL0:               return read_cpuid(CTR_EL0);
 662         case SYS_DCZID_EL0:             return read_cpuid(DCZID_EL0);
 663         default:
 664                 BUG();
 665                 return 0;
 666         }
 667 }
 668
 669 #include <linux/irqchip/arm-gic-v3.h>
 670
 671 static bool
 672 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 673 {
 674         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 675
 676         return val >= entry->min_field_value;
 677 }
 678
 679 static bool
 680 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
 681 {
 682         u64 val;
 683
 684         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
 685         if (scope == SCOPE_SYSTEM)
 686                 val = read_system_reg(entry->sys_reg);
 687         else
 688                 val = __raw_read_system_reg(entry->sys_reg);
 689
 690         return feature_matches(val, entry);
 691 }
 692
 693 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
 694 {
 695         bool has_sre;
 696
 697         if (!has_cpuid_feature(entry, scope))
 698                 return false;
 699
 700         has_sre = gic_enable_sre();
 701         if (!has_sre)
 702                 pr_warn_once("%s present but disabled by higher exception level\n",
 703                              entry->desc);
 704
 705         return has_sre;
 706 }
 707
 708 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
 709 {
 710         u32 midr = read_cpuid_id();
 711         u32 rv_min, rv_max;
 712
 713         /* Cavium ThunderX pass 1.x and 2.x */
 714         rv_min = 0;
 715         rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK;
 716
 717         return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
 718 }
 719
 720 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
 721 {
 722         return is_kernel_in_hyp_mode();
 723 }
 724
 725 static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
 726                            int __unused)
 727 {
 728         phys_addr_t idmap_addr = virt_to_phys(__hyp_idmap_text_start);
 729
 730         /*
 731          * Activate the lower HYP offset only if:
 732          * - the idmap doesn't clash with it,
 733          * - the kernel is not running at EL2.
 734          */
 735         return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode();
 736 }
 737
 738 static const struct arm64_cpu_capabilities arm64_features[] = {
 739         {
 740                 .desc = "GIC system register CPU interface",
 741                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
 742                 .def_scope = SCOPE_SYSTEM,
 743                 .matches = has_useable_gicv3_cpuif,
 744                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 745                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
 746                 .sign = FTR_UNSIGNED,
 747                 .min_field_value = 1,
 748         },
 749 #ifdef CONFIG_ARM64_PAN
 750         {
 751                 .desc = "Privileged Access Never",
 752                 .capability = ARM64_HAS_PAN,
 753                 .def_scope = SCOPE_SYSTEM,
 754                 .matches = has_cpuid_feature,
 755                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
 756                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
 757                 .sign = FTR_UNSIGNED,
 758                 .min_field_value = 1,
 759                 .enable = cpu_enable_pan,
 760         },
 761 #endif /* CONFIG_ARM64_PAN */
 762 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
 763         {
 764                 .desc = "LSE atomic instructions",
 765                 .capability = ARM64_HAS_LSE_ATOMICS,
 766                 .def_scope = SCOPE_SYSTEM,
 767                 .matches = has_cpuid_feature,
 768                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
 769                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
 770                 .sign = FTR_UNSIGNED,
 771                 .min_field_value = 2,
 772         },
 773 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
 774         {
 775                 .desc = "Software prefetching using PRFM",
 776                 .capability = ARM64_HAS_NO_HW_PREFETCH,
 777                 .def_scope = SCOPE_SYSTEM,
 778                 .matches = has_no_hw_prefetch,
 779         },
 780 #ifdef CONFIG_ARM64_UAO
 781         {
 782                 .desc = "User Access Override",
 783                 .capability = ARM64_HAS_UAO,
 784                 .def_scope = SCOPE_SYSTEM,
 785                 .matches = has_cpuid_feature,
 786                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
 787                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
 788                 .min_field_value = 1,
 789                 .enable = cpu_enable_uao,
 790         },
 791 #endif /* CONFIG_ARM64_UAO */
 792 #ifdef CONFIG_ARM64_PAN
 793         {
 794                 .capability = ARM64_ALT_PAN_NOT_UAO,
 795                 .def_scope = SCOPE_SYSTEM,
 796                 .matches = cpufeature_pan_not_uao,
 797         },
 798 #endif /* CONFIG_ARM64_PAN */
 799         {
 800                 .desc = "Virtualization Host Extensions",
 801                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
 802                 .def_scope = SCOPE_SYSTEM,
 803                 .matches = runs_at_el2,
 804         },
 805         {
 806                 .desc = "32-bit EL0 Support",
 807                 .capability = ARM64_HAS_32BIT_EL0,
 808                 .def_scope = SCOPE_SYSTEM,
 809                 .matches = has_cpuid_feature,
 810                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 811                 .sign = FTR_UNSIGNED,
 812                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
 813                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
 814         },
 815         {
 816                 .desc = "Reduced HYP mapping offset",
 817                 .capability = ARM64_HYP_OFFSET_LOW,
 818                 .def_scope = SCOPE_SYSTEM,
 819                 .matches = hyp_offset_low,
 820         },
 821         {},
 822 };
 823
 824 #define HWCAP_CAP(reg, field, s, min_value, type, cap)  \
 825         {                                                       \
 826                 .desc = #cap,                                   \
 827                 .def_scope = SCOPE_SYSTEM,                      \
 828                 .matches = has_cpuid_feature,                   \
 829                 .sys_reg = reg,                                 \
 830                 .field_pos = field,                             \
 831                 .sign = s,                                      \
 832                 .min_field_value = min_value,                   \
 833                 .hwcap_type = type,                             \
 834                 .hwcap = cap,                                   \
 835         }
 836
 837 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
 838         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
 839         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
 840         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
 841         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
 842         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
 843         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
 844         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
 845         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
 846         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
 847         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
 848         {},
 849 };
 850
 851 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
 852 #ifdef CONFIG_COMPAT
 853         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
 854         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
 855         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
 856         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
 857         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
 858 #endif
 859         {},
 860 };
 861
 862 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
 863 {
 864         switch (cap->hwcap_type) {
 865         case CAP_HWCAP:
 866                 elf_hwcap |= cap->hwcap;
 867                 break;
 868 #ifdef CONFIG_COMPAT
 869         case CAP_COMPAT_HWCAP:
 870                 compat_elf_hwcap |= (u32)cap->hwcap;
 871                 break;
 872         case CAP_COMPAT_HWCAP2:
 873                 compat_elf_hwcap2 |= (u32)cap->hwcap;
 874                 break;
 875 #endif
 876         default:
 877                 WARN_ON(1);
 878                 break;
 879         }
 880 }
 881
 882 /* Check if we have a particular HWCAP enabled */
 883 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
 884 {
 885         bool rc;
 886
 887         switch (cap->hwcap_type) {
 888         case CAP_HWCAP:
 889                 rc = (elf_hwcap & cap->hwcap) != 0;
 890                 break;
 891 #ifdef CONFIG_COMPAT
 892         case CAP_COMPAT_HWCAP:
 893                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
 894                 break;
 895         case CAP_COMPAT_HWCAP2:
 896                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
 897                 break;
 898 #endif
 899         default:
 900                 WARN_ON(1);
 901                 rc = false;
 902         }
 903
 904         return rc;
 905 }
 906
 907 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
 908 {
 909         for (; hwcaps->matches; hwcaps++)
 910                 if (hwcaps->matches(hwcaps, hwcaps->def_scope))
 911                         cap_set_elf_hwcap(hwcaps);
 912 }
 913
 914 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
 915                             const char *info)
 916 {
 917         for (; caps->matches; caps++) {
 918                 if (!caps->matches(caps, caps->def_scope))
 919                         continue;
 920
 921                 if (!cpus_have_cap(caps->capability) && caps->desc)
 922                         pr_info("%s %s\n", info, caps->desc);
 923                 cpus_set_cap(caps->capability);
 924         }
 925 }
 926
 927 /*
 928  * Run through the enabled capabilities and enable() it on all active
 929  * CPUs
 930  */
 931 void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
 932 {
 933         for (; caps->matches; caps++)
 934                 if (caps->enable && cpus_have_cap(caps->capability))
 935                         on_each_cpu(caps->enable, NULL, true);
 936 }
 937
 938 /*
 939  * Flag to indicate if we have computed the system wide
 940  * capabilities based on the boot time active CPUs. This
 941  * will be used to determine if a new booting CPU should
 942  * go through the verification process to make sure that it
 943  * supports the system capabilities, without using a hotplug
 944  * notifier.
 945  */
 946 static bool sys_caps_initialised;
 947
 948 static inline void set_sys_caps_initialised(void)
 949 {
 950         sys_caps_initialised = true;
 951 }
 952
 953 /*
 954  * Check for CPU features that are used in early boot
 955  * based on the Boot CPU value.
 956  */
 957 static void check_early_cpu_features(void)
 958 {
 959         verify_cpu_run_el();
 960         verify_cpu_asid_bits();
 961 }
 962
 963 static void
 964 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
 965 {
 966
 967         for (; caps->matches; caps++)
 968                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
 969                         pr_crit("CPU%d: missing HWCAP: %s\n",
 970                                         smp_processor_id(), caps->desc);
 971                         cpu_die_early();
 972                 }
 973 }
 974
 975 static void
 976 verify_local_cpu_features(const struct arm64_cpu_capabilities *caps)
 977 {
 978         for (; caps->matches; caps++) {
 979                 if (!cpus_have_cap(caps->capability))
 980                         continue;
 981                 /*
 982                  * If the new CPU misses an advertised feature, we cannot proceed
 983                  * further, park the cpu.
 984                  */
 985                 if (!caps->matches(caps, SCOPE_LOCAL_CPU)) {
 986                         pr_crit("CPU%d: missing feature: %s\n",
 987                                         smp_processor_id(), caps->desc);
 988                         cpu_die_early();
 989                 }
 990                 if (caps->enable)
 991                         caps->enable(NULL);
 992         }
 993 }
 994
 995 /*
 996  * Run through the enabled system capabilities and enable() it on this CPU.
 997  * The capabilities were decided based on the available CPUs at the boot time.
 998  * Any new CPU should match the system wide status of the capability. If the
 999  * new CPU doesn't have a capability which the system now has enabled, we
1000  * cannot do anything to fix it up and could cause unexpected failures. So
1001  * we park the CPU.
1002  */
1003 void verify_local_cpu_capabilities(void)
1004 {
1005
1006         check_early_cpu_features();
1007
1008         /*
1009          * If we haven't computed the system capabilities, there is nothing
1010          * to verify.
1011          */
1012         if (!sys_caps_initialised)
1013                 return;
1014
1015         verify_local_cpu_errata();
1016         verify_local_cpu_features(arm64_features);
1017         verify_local_elf_hwcaps(arm64_elf_hwcaps);
1018         if (system_supports_32bit_el0())
1019                 verify_local_elf_hwcaps(compat_elf_hwcaps);
1020 }
1021
1022 static void __init setup_feature_capabilities(void)
1023 {
1024         update_cpu_capabilities(arm64_features, "detected feature:");
1025         enable_cpu_capabilities(arm64_features);
1026 }
1027
1028 /*
1029  * Check if the current CPU has a given feature capability.
1030  * Should be called from non-preemptible context.
1031  */
1032 bool this_cpu_has_cap(unsigned int cap)
1033 {
1034         const struct arm64_cpu_capabilities *caps;
1035
1036         if (WARN_ON(preemptible()))
1037                 return false;
1038
1039         for (caps = arm64_features; caps->desc; caps++)
1040                 if (caps->capability == cap && caps->matches)
1041                         return caps->matches(caps, SCOPE_LOCAL_CPU);
1042
1043         return false;
1044 }
1045
1046 void __init setup_cpu_features(void)
1047 {
1048         u32 cwg;
1049         int cls;
1050
1051         /* Set the CPU feature capabilies */
1052         setup_feature_capabilities();
1053         enable_errata_workarounds();
1054         setup_elf_hwcaps(arm64_elf_hwcaps);
1055
1056         if (system_supports_32bit_el0())
1057                 setup_elf_hwcaps(compat_elf_hwcaps);
1058
1059         /* Advertise that we have computed the system capabilities */
1060         set_sys_caps_initialised();
1061
1062         /*
1063          * Check for sane CTR_EL0.CWG value.
1064          */
1065         cwg = cache_type_cwg();
1066         cls = cache_line_size();
1067         if (!cwg)
1068                 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1069                         cls);
1070         if (L1_CACHE_BYTES < cls)
1071                 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1072                         L1_CACHE_BYTES, cls);
1073 }
1074
1075 static bool __maybe_unused
1076 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
1077 {
1078         return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO));
1079 }