arch/x86/kvm/x86.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * derived from drivers/kvm/kvm_main.c
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright (C) 2008 Qumranet, Inc.
   8  * Copyright IBM Corporation, 2008
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  *   Amit Shah    <amit.shah@qumranet.com>
  15  *   Ben-Ami Yassour <benami@il.ibm.com>
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  *
  20  */
  21
  22 #include <linux/kvm_host.h>
  23 #include "irq.h"
  24 #include "mmu.h"
  25 #include "i8254.h"
  26 #include "tss.h"
  27 #include "kvm_cache_regs.h"
  28 #include "x86.h"
  29 #include "cpuid.h"
  30
  31 #include <linux/clocksource.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/kvm.h>
  34 #include <linux/fs.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/module.h>
  37 #include <linux/mman.h>
  38 #include <linux/highmem.h>
  39 #include <linux/iommu.h>
  40 #include <linux/intel-iommu.h>
  41 #include <linux/cpufreq.h>
  42 #include <linux/user-return-notifier.h>
  43 #include <linux/srcu.h>
  44 #include <linux/slab.h>
  45 #include <linux/perf_event.h>
  46 #include <linux/uaccess.h>
  47 #include <linux/hash.h>
  48 #include <linux/pci.h>
  49 #include <linux/timekeeper_internal.h>
  50 #include <linux/pvclock_gtod.h>
  51 #include <trace/events/kvm.h>
  52
  53 #define CREATE_TRACE_POINTS
  54 #include "trace.h"
  55
  56 #include <asm/debugreg.h>
  57 #include <asm/msr.h>
  58 #include <asm/desc.h>
  59 #include <asm/mtrr.h>
  60 #include <asm/mce.h>
  61 #include <asm/i387.h>
  62 #include <asm/fpu-internal.h> /* Ugh! */
  63 #include <asm/xcr.h>
  64 #include <asm/pvclock.h>
  65 #include <asm/div64.h>
  66
  67 #define MAX_IO_MSRS 256
  68 #define KVM_MAX_MCE_BANKS 32
  69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
  70
  71 #define emul_to_vcpu(ctxt) \
  72         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
  73
  74 /* EFER defaults:
  75  * - enable syscall per default because its emulated by KVM
  76  * - enable LME and LMA per default on 64 bit KVM
  77  */
  78 #ifdef CONFIG_X86_64
  79 static
  80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
  81 #else
  82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
  83 #endif
  84
  85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
  86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
  87
  88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
  89 static void process_nmi(struct kvm_vcpu *vcpu);
  90 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
  91
  92 struct kvm_x86_ops *kvm_x86_ops;
  93 EXPORT_SYMBOL_GPL(kvm_x86_ops);
  94
  95 static bool ignore_msrs = 0;
  96 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
  97
  98 unsigned int min_timer_period_us = 500;
  99 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
 100
 101 bool kvm_has_tsc_control;
 102 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
 103 u32  kvm_max_guest_tsc_khz;
 104 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
 105
 106 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
 107 static u32 tsc_tolerance_ppm = 250;
 108 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
 109
 110 static bool backwards_tsc_observed = false;
 111
 112 #define KVM_NR_SHARED_MSRS 16
 113
 114 struct kvm_shared_msrs_global {
 115         int nr;
 116         u32 msrs[KVM_NR_SHARED_MSRS];
 117 };
 118
 119 struct kvm_shared_msrs {
 120         struct user_return_notifier urn;
 121         bool registered;
 122         struct kvm_shared_msr_values {
 123                 u64 host;
 124                 u64 curr;
 125         } values[KVM_NR_SHARED_MSRS];
 126 };
 127
 128 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
 129 static struct kvm_shared_msrs __percpu *shared_msrs;
 130
 131 struct kvm_stats_debugfs_item debugfs_entries[] = {
 132         { "pf_fixed", VCPU_STAT(pf_fixed) },
 133         { "pf_guest", VCPU_STAT(pf_guest) },
 134         { "tlb_flush", VCPU_STAT(tlb_flush) },
 135         { "invlpg", VCPU_STAT(invlpg) },
 136         { "exits", VCPU_STAT(exits) },
 137         { "io_exits", VCPU_STAT(io_exits) },
 138         { "mmio_exits", VCPU_STAT(mmio_exits) },
 139         { "signal_exits", VCPU_STAT(signal_exits) },
 140         { "irq_window", VCPU_STAT(irq_window_exits) },
 141         { "nmi_window", VCPU_STAT(nmi_window_exits) },
 142         { "halt_exits", VCPU_STAT(halt_exits) },
 143         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
 144         { "hypercalls", VCPU_STAT(hypercalls) },
 145         { "request_irq", VCPU_STAT(request_irq_exits) },
 146         { "irq_exits", VCPU_STAT(irq_exits) },
 147         { "host_state_reload", VCPU_STAT(host_state_reload) },
 148         { "efer_reload", VCPU_STAT(efer_reload) },
 149         { "fpu_reload", VCPU_STAT(fpu_reload) },
 150         { "insn_emulation", VCPU_STAT(insn_emulation) },
 151         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
 152         { "irq_injections", VCPU_STAT(irq_injections) },
 153         { "nmi_injections", VCPU_STAT(nmi_injections) },
 154         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
 155         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
 156         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
 157         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
 158         { "mmu_flooded", VM_STAT(mmu_flooded) },
 159         { "mmu_recycled", VM_STAT(mmu_recycled) },
 160         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
 161         { "mmu_unsync", VM_STAT(mmu_unsync) },
 162         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
 163         { "largepages", VM_STAT(lpages) },
 164         { NULL }
 165 };
 166
 167 u64 __read_mostly host_xcr0;
 168
 169 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
 170
 171 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
 172 {
 173         int i;
 174         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
 175                 vcpu->arch.apf.gfns[i] = ~0;
 176 }
 177
 178 static void kvm_on_user_return(struct user_return_notifier *urn)
 179 {
 180         unsigned slot;
 181         struct kvm_shared_msrs *locals
 182                 = container_of(urn, struct kvm_shared_msrs, urn);
 183         struct kvm_shared_msr_values *values;
 184
 185         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
 186                 values = &locals->values[slot];
 187                 if (values->host != values->curr) {
 188                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
 189                         values->curr = values->host;
 190                 }
 191         }
 192         locals->registered = false;
 193         user_return_notifier_unregister(urn);
 194 }
 195
 196 static void shared_msr_update(unsigned slot, u32 msr)
 197 {
 198         u64 value;
 199         unsigned int cpu = smp_processor_id();
 200         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 201
 202         /* only read, and nobody should modify it at this time,
 203          * so don't need lock */
 204         if (slot >= shared_msrs_global.nr) {
 205                 printk(KERN_ERR "kvm: invalid MSR slot!");
 206                 return;
 207         }
 208         rdmsrl_safe(msr, &value);
 209         smsr->values[slot].host = value;
 210         smsr->values[slot].curr = value;
 211 }
 212
 213 void kvm_define_shared_msr(unsigned slot, u32 msr)
 214 {
 215         BUG_ON(slot >= KVM_NR_SHARED_MSRS);
 216         if (slot >= shared_msrs_global.nr)
 217                 shared_msrs_global.nr = slot + 1;
 218         shared_msrs_global.msrs[slot] = msr;
 219         /* we need ensured the shared_msr_global have been updated */
 220         smp_wmb();
 221 }
 222 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
 223
 224 static void kvm_shared_msr_cpu_online(void)
 225 {
 226         unsigned i;
 227
 228         for (i = 0; i < shared_msrs_global.nr; ++i)
 229                 shared_msr_update(i, shared_msrs_global.msrs[i]);
 230 }
 231
 232 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
 233 {
 234         unsigned int cpu = smp_processor_id();
 235         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 236
 237         if (((value ^ smsr->values[slot].curr) & mask) == 0)
 238                 return;
 239         smsr->values[slot].curr = value;
 240         wrmsrl(shared_msrs_global.msrs[slot], value);
 241         if (!smsr->registered) {
 242                 smsr->urn.on_user_return = kvm_on_user_return;
 243                 user_return_notifier_register(&smsr->urn);
 244                 smsr->registered = true;
 245         }
 246 }
 247 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
 248
 249 static void drop_user_return_notifiers(void)
 250 {
 251         unsigned int cpu = smp_processor_id();
 252         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 253
 254         if (smsr->registered)
 255                 kvm_on_user_return(&smsr->urn);
 256 }
 257
 258 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
 259 {
 260         return vcpu->arch.apic_base;
 261 }
 262 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
 263
 264 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 265 {
 266         u64 old_state = vcpu->arch.apic_base &
 267                 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
 268         u64 new_state = msr_info->data &
 269                 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
 270         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
 271                 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
 272
 273         if (!msr_info->host_initiated &&
 274             ((msr_info->data & reserved_bits) != 0 ||
 275              new_state == X2APIC_ENABLE ||
 276              (new_state == MSR_IA32_APICBASE_ENABLE &&
 277               old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
 278              (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
 279               old_state == 0)))
 280                 return 1;
 281
 282         kvm_lapic_set_base(vcpu, msr_info->data);
 283         return 0;
 284 }
 285 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
 286
 287 asmlinkage __visible void kvm_spurious_fault(void)
 288 {
 289         /* Fault while not rebooting.  We want the trace. */
 290         BUG();
 291 }
 292 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
 293
 294 #define EXCPT_BENIGN            0
 295 #define EXCPT_CONTRIBUTORY      1
 296 #define EXCPT_PF                2
 297
 298 static int exception_class(int vector)
 299 {
 300         switch (vector) {
 301         case PF_VECTOR:
 302                 return EXCPT_PF;
 303         case DE_VECTOR:
 304         case TS_VECTOR:
 305         case NP_VECTOR:
 306         case SS_VECTOR:
 307         case GP_VECTOR:
 308                 return EXCPT_CONTRIBUTORY;
 309         default:
 310                 break;
 311         }
 312         return EXCPT_BENIGN;
 313 }
 314
 315 #define EXCPT_FAULT             0
 316 #define EXCPT_TRAP              1
 317 #define EXCPT_ABORT             2
 318 #define EXCPT_INTERRUPT         3
 319
 320 static int exception_type(int vector)
 321 {
 322         unsigned int mask;
 323
 324         if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
 325                 return EXCPT_INTERRUPT;
 326
 327         mask = 1 << vector;
 328
 329         /* #DB is trap, as instruction watchpoints are handled elsewhere */
 330         if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
 331                 return EXCPT_TRAP;
 332
 333         if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
 334                 return EXCPT_ABORT;
 335
 336         /* Reserved exceptions will result in fault */
 337         return EXCPT_FAULT;
 338 }
 339
 340 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
 341                 unsigned nr, bool has_error, u32 error_code,
 342                 bool reinject)
 343 {
 344         u32 prev_nr;
 345         int class1, class2;
 346
 347         kvm_make_request(KVM_REQ_EVENT, vcpu);
 348
 349         if (!vcpu->arch.exception.pending) {
 350         queue:
 351                 vcpu->arch.exception.pending = true;
 352                 vcpu->arch.exception.has_error_code = has_error;
 353                 vcpu->arch.exception.nr = nr;
 354                 vcpu->arch.exception.error_code = error_code;
 355                 vcpu->arch.exception.reinject = reinject;
 356                 return;
 357         }
 358
 359         /* to check exception */
 360         prev_nr = vcpu->arch.exception.nr;
 361         if (prev_nr == DF_VECTOR) {
 362                 /* triple fault -> shutdown */
 363                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
 364                 return;
 365         }
 366         class1 = exception_class(prev_nr);
 367         class2 = exception_class(nr);
 368         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
 369                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
 370                 /* generate double fault per SDM Table 5-5 */
 371                 vcpu->arch.exception.pending = true;
 372                 vcpu->arch.exception.has_error_code = true;
 373                 vcpu->arch.exception.nr = DF_VECTOR;
 374                 vcpu->arch.exception.error_code = 0;
 375         } else
 376                 /* replace previous exception with a new one in a hope
 377                    that instruction re-execution will regenerate lost
 378                    exception */
 379                 goto queue;
 380 }
 381
 382 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 383 {
 384         kvm_multiple_exception(vcpu, nr, false, 0, false);
 385 }
 386 EXPORT_SYMBOL_GPL(kvm_queue_exception);
 387
 388 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 389 {
 390         kvm_multiple_exception(vcpu, nr, false, 0, true);
 391 }
 392 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
 393
 394 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
 395 {
 396         if (err)
 397                 kvm_inject_gp(vcpu, 0);
 398         else
 399                 kvm_x86_ops->skip_emulated_instruction(vcpu);
 400 }
 401 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
 402
 403 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 404 {
 405         ++vcpu->stat.pf_guest;
 406         vcpu->arch.cr2 = fault->address;
 407         kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
 408 }
 409 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
 410
 411 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 412 {
 413         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
 414                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
 415         else
 416                 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
 417
 418         return fault->nested_page_fault;
 419 }
 420
 421 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
 422 {
 423         atomic_inc(&vcpu->arch.nmi_queued);
 424         kvm_make_request(KVM_REQ_NMI, vcpu);
 425 }
 426 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
 427
 428 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 429 {
 430         kvm_multiple_exception(vcpu, nr, true, error_code, false);
 431 }
 432 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
 433
 434 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 435 {
 436         kvm_multiple_exception(vcpu, nr, true, error_code, true);
 437 }
 438 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
 439
 440 /*
 441  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
 442  * a #GP and return false.
 443  */
 444 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
 445 {
 446         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
 447                 return true;
 448         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
 449         return false;
 450 }
 451 EXPORT_SYMBOL_GPL(kvm_require_cpl);
 452
 453 /*
 454  * This function will be used to read from the physical memory of the currently
 455  * running guest. The difference to kvm_read_guest_page is that this function
 456  * can read from guest physical or from the guest's guest physical memory.
 457  */
 458 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 459                             gfn_t ngfn, void *data, int offset, int len,
 460                             u32 access)
 461 {
 462         struct x86_exception exception;
 463         gfn_t real_gfn;
 464         gpa_t ngpa;
 465
 466         ngpa     = gfn_to_gpa(ngfn);
 467         real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
 468         if (real_gfn == UNMAPPED_GVA)
 469                 return -EFAULT;
 470
 471         real_gfn = gpa_to_gfn(real_gfn);
 472
 473         return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
 474 }
 475 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
 476
 477 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
 478                                void *data, int offset, int len, u32 access)
 479 {
 480         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
 481                                        data, offset, len, access);
 482 }
 483
 484 /*
 485  * Load the pae pdptrs.  Return true is they are all valid.
 486  */
 487 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
 488 {
 489         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
 490         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
 491         int i;
 492         int ret;
 493         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
 494
 495         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
 496                                       offset * sizeof(u64), sizeof(pdpte),
 497                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
 498         if (ret < 0) {
 499                 ret = 0;
 500                 goto out;
 501         }
 502         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
 503                 if (is_present_gpte(pdpte[i]) &&
 504                     (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
 505                         ret = 0;
 506                         goto out;
 507                 }
 508         }
 509         ret = 1;
 510
 511         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
 512         __set_bit(VCPU_EXREG_PDPTR,
 513                   (unsigned long *)&vcpu->arch.regs_avail);
 514         __set_bit(VCPU_EXREG_PDPTR,
 515                   (unsigned long *)&vcpu->arch.regs_dirty);
 516 out:
 517
 518         return ret;
 519 }
 520 EXPORT_SYMBOL_GPL(load_pdptrs);
 521
 522 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
 523 {
 524         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
 525         bool changed = true;
 526         int offset;
 527         gfn_t gfn;
 528         int r;
 529
 530         if (is_long_mode(vcpu) || !is_pae(vcpu))
 531                 return false;
 532
 533         if (!test_bit(VCPU_EXREG_PDPTR,
 534                       (unsigned long *)&vcpu->arch.regs_avail))
 535                 return true;
 536
 537         gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
 538         offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
 539         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
 540                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
 541         if (r < 0)
 542                 goto out;
 543         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
 544 out:
 545
 546         return changed;
 547 }
 548
 549 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 550 {
 551         unsigned long old_cr0 = kvm_read_cr0(vcpu);
 552         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
 553                                     X86_CR0_CD | X86_CR0_NW;
 554
 555         cr0 |= X86_CR0_ET;
 556
 557 #ifdef CONFIG_X86_64
 558         if (cr0 & 0xffffffff00000000UL)
 559                 return 1;
 560 #endif
 561
 562         cr0 &= ~CR0_RESERVED_BITS;
 563
 564         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
 565                 return 1;
 566
 567         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
 568                 return 1;
 569
 570         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 571 #ifdef CONFIG_X86_64
 572                 if ((vcpu->arch.efer & EFER_LME)) {
 573                         int cs_db, cs_l;
 574
 575                         if (!is_pae(vcpu))
 576                                 return 1;
 577                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
 578                         if (cs_l)
 579                                 return 1;
 580                 } else
 581 #endif
 582                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 583                                                  kvm_read_cr3(vcpu)))
 584                         return 1;
 585         }
 586
 587         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
 588                 return 1;
 589
 590         kvm_x86_ops->set_cr0(vcpu, cr0);
 591
 592         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
 593                 kvm_clear_async_pf_completion_queue(vcpu);
 594                 kvm_async_pf_hash_reset(vcpu);
 595         }
 596
 597         if ((cr0 ^ old_cr0) & update_bits)
 598                 kvm_mmu_reset_context(vcpu);
 599         return 0;
 600 }
 601 EXPORT_SYMBOL_GPL(kvm_set_cr0);
 602
 603 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
 604 {
 605         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
 606 }
 607 EXPORT_SYMBOL_GPL(kvm_lmsw);
 608
 609 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
 610 {
 611         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
 612                         !vcpu->guest_xcr0_loaded) {
 613                 /* kvm_set_xcr() also depends on this */
 614                 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
 615                 vcpu->guest_xcr0_loaded = 1;
 616         }
 617 }
 618
 619 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
 620 {
 621         if (vcpu->guest_xcr0_loaded) {
 622                 if (vcpu->arch.xcr0 != host_xcr0)
 623                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
 624                 vcpu->guest_xcr0_loaded = 0;
 625         }
 626 }
 627
 628 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 629 {
 630         u64 xcr0 = xcr;
 631         u64 old_xcr0 = vcpu->arch.xcr0;
 632         u64 valid_bits;
 633
 634         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
 635         if (index != XCR_XFEATURE_ENABLED_MASK)
 636                 return 1;
 637         if (!(xcr0 & XSTATE_FP))
 638                 return 1;
 639         if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
 640                 return 1;
 641
 642         /*
 643          * Do not allow the guest to set bits that we do not support
 644          * saving.  However, xcr0 bit 0 is always set, even if the
 645          * emulated CPU does not support XSAVE (see fx_init).
 646          */
 647         valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
 648         if (xcr0 & ~valid_bits)
 649                 return 1;
 650
 651         if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
 652                 return 1;
 653
 654         kvm_put_guest_xcr0(vcpu);
 655         vcpu->arch.xcr0 = xcr0;
 656
 657         if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
 658                 kvm_update_cpuid(vcpu);
 659         return 0;
 660 }
 661
 662 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 663 {
 664         if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
 665             __kvm_set_xcr(vcpu, index, xcr)) {
 666                 kvm_inject_gp(vcpu, 0);
 667                 return 1;
 668         }
 669         return 0;
 670 }
 671 EXPORT_SYMBOL_GPL(kvm_set_xcr);
 672
 673 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 674 {
 675         unsigned long old_cr4 = kvm_read_cr4(vcpu);
 676         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
 677                                    X86_CR4_PAE | X86_CR4_SMEP;
 678         if (cr4 & CR4_RESERVED_BITS)
 679                 return 1;
 680
 681         if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
 682                 return 1;
 683
 684         if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
 685                 return 1;
 686
 687         if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
 688                 return 1;
 689
 690         if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
 691                 return 1;
 692
 693         if (is_long_mode(vcpu)) {
 694                 if (!(cr4 & X86_CR4_PAE))
 695                         return 1;
 696         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
 697                    && ((cr4 ^ old_cr4) & pdptr_bits)
 698                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 699                                    kvm_read_cr3(vcpu)))
 700                 return 1;
 701
 702         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
 703                 if (!guest_cpuid_has_pcid(vcpu))
 704                         return 1;
 705
 706                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
 707                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
 708                         return 1;
 709         }
 710
 711         if (kvm_x86_ops->set_cr4(vcpu, cr4))
 712                 return 1;
 713
 714         if (((cr4 ^ old_cr4) & pdptr_bits) ||
 715             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
 716                 kvm_mmu_reset_context(vcpu);
 717
 718         if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
 719                 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
 720
 721         if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
 722                 kvm_update_cpuid(vcpu);
 723
 724         return 0;
 725 }
 726 EXPORT_SYMBOL_GPL(kvm_set_cr4);
 727
 728 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
 729 {
 730         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
 731                 kvm_mmu_sync_roots(vcpu);
 732                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
 733                 return 0;
 734         }
 735
 736         if (is_long_mode(vcpu)) {
 737                 if (cr3 & CR3_L_MODE_RESERVED_BITS)
 738                         return 1;
 739         } else if (is_pae(vcpu) && is_paging(vcpu) &&
 740                    !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
 741                 return 1;
 742
 743         vcpu->arch.cr3 = cr3;
 744         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
 745         kvm_mmu_new_cr3(vcpu);
 746         return 0;
 747 }
 748 EXPORT_SYMBOL_GPL(kvm_set_cr3);
 749
 750 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
 751 {
 752         if (cr8 & CR8_RESERVED_BITS)
 753                 return 1;
 754         if (irqchip_in_kernel(vcpu->kvm))
 755                 kvm_lapic_set_tpr(vcpu, cr8);
 756         else
 757                 vcpu->arch.cr8 = cr8;
 758         return 0;
 759 }
 760 EXPORT_SYMBOL_GPL(kvm_set_cr8);
 761
 762 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
 763 {
 764         if (irqchip_in_kernel(vcpu->kvm))
 765                 return kvm_lapic_get_cr8(vcpu);
 766         else
 767                 return vcpu->arch.cr8;
 768 }
 769 EXPORT_SYMBOL_GPL(kvm_get_cr8);
 770
 771 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
 772 {
 773         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
 774                 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
 775 }
 776
 777 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
 778 {
 779         unsigned long dr7;
 780
 781         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
 782                 dr7 = vcpu->arch.guest_debug_dr7;
 783         else
 784                 dr7 = vcpu->arch.dr7;
 785         kvm_x86_ops->set_dr7(vcpu, dr7);
 786         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
 787         if (dr7 & DR7_BP_EN_MASK)
 788                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
 789 }
 790
 791 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
 792 {
 793         u64 fixed = DR6_FIXED_1;
 794
 795         if (!guest_cpuid_has_rtm(vcpu))
 796                 fixed |= DR6_RTM;
 797         return fixed;
 798 }
 799
 800 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
 801 {
 802         switch (dr) {
 803         case 0 ... 3:
 804                 vcpu->arch.db[dr] = val;
 805                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
 806                         vcpu->arch.eff_db[dr] = val;
 807                 break;
 808         case 4:
 809                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 810                         return 1; /* #UD */
 811                 /* fall through */
 812         case 6:
 813                 if (val & 0xffffffff00000000ULL)
 814                         return -1; /* #GP */
 815                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
 816                 kvm_update_dr6(vcpu);
 817                 break;
 818         case 5:
 819                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 820                         return 1; /* #UD */
 821                 /* fall through */
 822         default: /* 7 */
 823                 if (val & 0xffffffff00000000ULL)
 824                         return -1; /* #GP */
 825                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
 826                 kvm_update_dr7(vcpu);
 827                 break;
 828         }
 829
 830         return 0;
 831 }
 832
 833 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
 834 {
 835         int res;
 836
 837         res = __kvm_set_dr(vcpu, dr, val);
 838         if (res > 0)
 839                 kvm_queue_exception(vcpu, UD_VECTOR);
 840         else if (res < 0)
 841                 kvm_inject_gp(vcpu, 0);
 842
 843         return res;
 844 }
 845 EXPORT_SYMBOL_GPL(kvm_set_dr);
 846
 847 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
 848 {
 849         switch (dr) {
 850         case 0 ... 3:
 851                 *val = vcpu->arch.db[dr];
 852                 break;
 853         case 4:
 854                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 855                         return 1;
 856                 /* fall through */
 857         case 6:
 858                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
 859                         *val = vcpu->arch.dr6;
 860                 else
 861                         *val = kvm_x86_ops->get_dr6(vcpu);
 862                 break;
 863         case 5:
 864                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 865                         return 1;
 866                 /* fall through */
 867         default: /* 7 */
 868                 *val = vcpu->arch.dr7;
 869                 break;
 870         }
 871
 872         return 0;
 873 }
 874
 875 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
 876 {
 877         if (_kvm_get_dr(vcpu, dr, val)) {
 878                 kvm_queue_exception(vcpu, UD_VECTOR);
 879                 return 1;
 880         }
 881         return 0;
 882 }
 883 EXPORT_SYMBOL_GPL(kvm_get_dr);
 884
 885 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
 886 {
 887         u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
 888         u64 data;
 889         int err;
 890
 891         err = kvm_pmu_read_pmc(vcpu, ecx, &data);
 892         if (err)
 893                 return err;
 894         kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
 895         kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
 896         return err;
 897 }
 898 EXPORT_SYMBOL_GPL(kvm_rdpmc);
 899
 900 /*
 901  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
 902  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
 903  *
 904  * This list is modified at module load time to reflect the
 905  * capabilities of the host cpu. This capabilities test skips MSRs that are
 906  * kvm-specific. Those are put in the beginning of the list.
 907  */
 908
 909 #define KVM_SAVE_MSRS_BEGIN     12
 910 static u32 msrs_to_save[] = {
 911         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
 912         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
 913         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
 914         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
 915         HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
 916         MSR_KVM_PV_EOI_EN,
 917         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 918         MSR_STAR,
 919 #ifdef CONFIG_X86_64
 920         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
 921 #endif
 922         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
 923         MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
 924 };
 925
 926 static unsigned num_msrs_to_save;
 927
 928 static const u32 emulated_msrs[] = {
 929         MSR_IA32_TSC_ADJUST,
 930         MSR_IA32_TSCDEADLINE,
 931         MSR_IA32_MISC_ENABLE,
 932         MSR_IA32_MCG_STATUS,
 933         MSR_IA32_MCG_CTL,
 934 };
 935
 936 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
 937 {
 938         if (efer & efer_reserved_bits)
 939                 return false;
 940
 941         if (efer & EFER_FFXSR) {
 942                 struct kvm_cpuid_entry2 *feat;
 943
 944                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
 945                 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
 946                         return false;
 947         }
 948
 949         if (efer & EFER_SVME) {
 950                 struct kvm_cpuid_entry2 *feat;
 951
 952                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
 953                 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
 954                         return false;
 955         }
 956
 957         return true;
 958 }
 959 EXPORT_SYMBOL_GPL(kvm_valid_efer);
 960
 961 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
 962 {
 963         u64 old_efer = vcpu->arch.efer;
 964
 965         if (!kvm_valid_efer(vcpu, efer))
 966                 return 1;
 967
 968         if (is_paging(vcpu)
 969             && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
 970                 return 1;
 971
 972         efer &= ~EFER_LMA;
 973         efer |= vcpu->arch.efer & EFER_LMA;
 974
 975         kvm_x86_ops->set_efer(vcpu, efer);
 976
 977         /* Update reserved bits */
 978         if ((efer ^ old_efer) & EFER_NX)
 979                 kvm_mmu_reset_context(vcpu);
 980
 981         return 0;
 982 }
 983
 984 void kvm_enable_efer_bits(u64 mask)
 985 {
 986        efer_reserved_bits &= ~mask;
 987 }
 988 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
 989
 990
 991 /*
 992  * Writes msr value into into the appropriate "register".
 993  * Returns 0 on success, non-0 otherwise.
 994  * Assumes vcpu_load() was already called.
 995  */
 996 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
 997 {
 998         return kvm_x86_ops->set_msr(vcpu, msr);
 999 }
1000
1001 /*
1002  * Adapt set_msr() to msr_io()'s calling convention
1003  */
1004 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1005 {
1006         struct msr_data msr;
1007
1008         msr.data = *data;
1009         msr.index = index;
1010         msr.host_initiated = true;
1011         return kvm_set_msr(vcpu, &msr);
1012 }
1013
1014 #ifdef CONFIG_X86_64
1015 struct pvclock_gtod_data {
1016         seqcount_t      seq;
1017
1018         struct { /* extract of a clocksource struct */
1019                 int vclock_mode;
1020                 cycle_t cycle_last;
1021                 cycle_t mask;
1022                 u32     mult;
1023                 u32     shift;
1024         } clock;
1025
1026         u64             boot_ns;
1027         u64             nsec_base;
1028 };
1029
1030 static struct pvclock_gtod_data pvclock_gtod_data;
1031
1032 static void update_pvclock_gtod(struct timekeeper *tk)
1033 {
1034         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1035         u64 boot_ns;
1036
1037         boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
1038
1039         write_seqcount_begin(&vdata->seq);
1040
1041         /* copy pvclock gtod data */
1042         vdata->clock.vclock_mode        = tk->tkr.clock->archdata.vclock_mode;
1043         vdata->clock.cycle_last         = tk->tkr.cycle_last;
1044         vdata->clock.mask               = tk->tkr.mask;
1045         vdata->clock.mult               = tk->tkr.mult;
1046         vdata->clock.shift              = tk->tkr.shift;
1047
1048         vdata->boot_ns                  = boot_ns;
1049         vdata->nsec_base                = tk->tkr.xtime_nsec;
1050
1051         write_seqcount_end(&vdata->seq);
1052 }
1053 #endif
1054
1055
1056 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1057 {
1058         int version;
1059         int r;
1060         struct pvclock_wall_clock wc;
1061         struct timespec boot;
1062
1063         if (!wall_clock)
1064                 return;
1065
1066         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1067         if (r)
1068                 return;
1069
1070         if (version & 1)
1071                 ++version;  /* first time write, random junk */
1072
1073         ++version;
1074
1075         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1076
1077         /*
1078          * The guest calculates current wall clock time by adding
1079          * system time (updated by kvm_guest_time_update below) to the
1080          * wall clock specified here.  guest system time equals host
1081          * system time for us, thus we must fill in host boot time here.
1082          */
1083         getboottime(&boot);
1084
1085         if (kvm->arch.kvmclock_offset) {
1086                 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1087                 boot = timespec_sub(boot, ts);
1088         }
1089         wc.sec = boot.tv_sec;
1090         wc.nsec = boot.tv_nsec;
1091         wc.version = version;
1092
1093         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1094
1095         version++;
1096         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1097 }
1098
1099 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1100 {
1101         uint32_t quotient, remainder;
1102
1103         /* Don't try to replace with do_div(), this one calculates
1104          * "(dividend << 32) / divisor" */
1105         __asm__ ( "divl %4"
1106                   : "=a" (quotient), "=d" (remainder)
1107                   : "0" (0), "1" (dividend), "r" (divisor) );
1108         return quotient;
1109 }
1110
1111 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1112                                s8 *pshift, u32 *pmultiplier)
1113 {
1114         uint64_t scaled64;
1115         int32_t  shift = 0;
1116         uint64_t tps64;
1117         uint32_t tps32;
1118
1119         tps64 = base_khz * 1000LL;
1120         scaled64 = scaled_khz * 1000LL;
1121         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1122                 tps64 >>= 1;
1123                 shift--;
1124         }
1125
1126         tps32 = (uint32_t)tps64;
1127         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1128                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1129                         scaled64 >>= 1;
1130                 else
1131                         tps32 <<= 1;
1132                 shift++;
1133         }
1134
1135         *pshift = shift;
1136         *pmultiplier = div_frac(scaled64, tps32);
1137
1138         pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1139                  __func__, base_khz, scaled_khz, shift, *pmultiplier);
1140 }
1141
1142 static inline u64 get_kernel_ns(void)
1143 {
1144         return ktime_get_boot_ns();
1145 }
1146
1147 #ifdef CONFIG_X86_64
1148 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1149 #endif
1150
1151 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1152 unsigned long max_tsc_khz;
1153
1154 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1155 {
1156         return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1157                                    vcpu->arch.virtual_tsc_shift);
1158 }
1159
1160 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1161 {
1162         u64 v = (u64)khz * (1000000 + ppm);
1163         do_div(v, 1000000);
1164         return v;
1165 }
1166
1167 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1168 {
1169         u32 thresh_lo, thresh_hi;
1170         int use_scaling = 0;
1171
1172         /* tsc_khz can be zero if TSC calibration fails */
1173         if (this_tsc_khz == 0)
1174                 return;
1175
1176         /* Compute a scale to convert nanoseconds in TSC cycles */
1177         kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1178                            &vcpu->arch.virtual_tsc_shift,
1179                            &vcpu->arch.virtual_tsc_mult);
1180         vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1181
1182         /*
1183          * Compute the variation in TSC rate which is acceptable
1184          * within the range of tolerance and decide if the
1185          * rate being applied is within that bounds of the hardware
1186          * rate.  If so, no scaling or compensation need be done.
1187          */
1188         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1189         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1190         if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1191                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1192                 use_scaling = 1;
1193         }
1194         kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1195 }
1196
1197 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1198 {
1199         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1200                                       vcpu->arch.virtual_tsc_mult,
1201                                       vcpu->arch.virtual_tsc_shift);
1202         tsc += vcpu->arch.this_tsc_write;
1203         return tsc;
1204 }
1205
1206 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1207 {
1208 #ifdef CONFIG_X86_64
1209         bool vcpus_matched;
1210         bool do_request = false;
1211         struct kvm_arch *ka = &vcpu->kvm->arch;
1212         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1213
1214         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1215                          atomic_read(&vcpu->kvm->online_vcpus));
1216
1217         if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1218                 if (!ka->use_master_clock)
1219                         do_request = 1;
1220
1221         if (!vcpus_matched && ka->use_master_clock)
1222                         do_request = 1;
1223
1224         if (do_request)
1225                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1226
1227         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1228                             atomic_read(&vcpu->kvm->online_vcpus),
1229                             ka->use_master_clock, gtod->clock.vclock_mode);
1230 #endif
1231 }
1232
1233 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1234 {
1235         u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1236         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1237 }
1238
1239 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1240 {
1241         struct kvm *kvm = vcpu->kvm;
1242         u64 offset, ns, elapsed;
1243         unsigned long flags;
1244         s64 usdiff;
1245         bool matched;
1246         bool already_matched;
1247         u64 data = msr->data;
1248
1249         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1250         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1251         ns = get_kernel_ns();
1252         elapsed = ns - kvm->arch.last_tsc_nsec;
1253
1254         if (vcpu->arch.virtual_tsc_khz) {
1255                 int faulted = 0;
1256
1257                 /* n.b - signed multiplication and division required */
1258                 usdiff = data - kvm->arch.last_tsc_write;
1259 #ifdef CONFIG_X86_64
1260                 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1261 #else
1262                 /* do_div() only does unsigned */
1263                 asm("1: idivl %[divisor]\n"
1264                     "2: xor %%edx, %%edx\n"
1265                     "   movl $0, %[faulted]\n"
1266                     "3:\n"
1267                     ".section .fixup,\"ax\"\n"
1268                     "4: movl $1, %[faulted]\n"
1269                     "   jmp  3b\n"
1270                     ".previous\n"
1271
1272                 _ASM_EXTABLE(1b, 4b)
1273
1274                 : "=A"(usdiff), [faulted] "=r" (faulted)
1275                 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1276
1277 #endif
1278                 do_div(elapsed, 1000);
1279                 usdiff -= elapsed;
1280                 if (usdiff < 0)
1281                         usdiff = -usdiff;
1282
1283                 /* idivl overflow => difference is larger than USEC_PER_SEC */
1284                 if (faulted)
1285                         usdiff = USEC_PER_SEC;
1286         } else
1287                 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1288
1289         /*
1290          * Special case: TSC write with a small delta (1 second) of virtual
1291          * cycle time against real time is interpreted as an attempt to
1292          * synchronize the CPU.
1293          *
1294          * For a reliable TSC, we can match TSC offsets, and for an unstable
1295          * TSC, we add elapsed time in this computation.  We could let the
1296          * compensation code attempt to catch up if we fall behind, but
1297          * it's better to try to match offsets from the beginning.
1298          */
1299         if (usdiff < USEC_PER_SEC &&
1300             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1301                 if (!check_tsc_unstable()) {
1302                         offset = kvm->arch.cur_tsc_offset;
1303                         pr_debug("kvm: matched tsc offset for %llu\n", data);
1304                 } else {
1305                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1306                         data += delta;
1307                         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1308                         pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1309                 }
1310                 matched = true;
1311                 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1312         } else {
1313                 /*
1314                  * We split periods of matched TSC writes into generations.
1315                  * For each generation, we track the original measured
1316                  * nanosecond time, offset, and write, so if TSCs are in
1317                  * sync, we can match exact offset, and if not, we can match
1318                  * exact software computation in compute_guest_tsc()
1319                  *
1320                  * These values are tracked in kvm->arch.cur_xxx variables.
1321                  */
1322                 kvm->arch.cur_tsc_generation++;
1323                 kvm->arch.cur_tsc_nsec = ns;
1324                 kvm->arch.cur_tsc_write = data;
1325                 kvm->arch.cur_tsc_offset = offset;
1326                 matched = false;
1327                 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1328                          kvm->arch.cur_tsc_generation, data);
1329         }
1330
1331         /*
1332          * We also track th most recent recorded KHZ, write and time to
1333          * allow the matching interval to be extended at each write.
1334          */
1335         kvm->arch.last_tsc_nsec = ns;
1336         kvm->arch.last_tsc_write = data;
1337         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1338
1339         vcpu->arch.last_guest_tsc = data;
1340
1341         /* Keep track of which generation this VCPU has synchronized to */
1342         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1343         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1344         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1345
1346         if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1347                 update_ia32_tsc_adjust_msr(vcpu, offset);
1348         kvm_x86_ops->write_tsc_offset(vcpu, offset);
1349         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1350
1351         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1352         if (!matched) {
1353                 kvm->arch.nr_vcpus_matched_tsc = 0;
1354         } else if (!already_matched) {
1355                 kvm->arch.nr_vcpus_matched_tsc++;
1356         }
1357
1358         kvm_track_tsc_matching(vcpu);
1359         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1360 }
1361
1362 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1363
1364 #ifdef CONFIG_X86_64
1365
1366 static cycle_t read_tsc(void)
1367 {
1368         cycle_t ret;
1369         u64 last;
1370
1371         /*
1372          * Empirically, a fence (of type that depends on the CPU)
1373          * before rdtsc is enough to ensure that rdtsc is ordered
1374          * with respect to loads.  The various CPU manuals are unclear
1375          * as to whether rdtsc can be reordered with later loads,
1376          * but no one has ever seen it happen.
1377          */
1378         rdtsc_barrier();
1379         ret = (cycle_t)vget_cycles();
1380
1381         last = pvclock_gtod_data.clock.cycle_last;
1382
1383         if (likely(ret >= last))
1384                 return ret;
1385
1386         /*
1387          * GCC likes to generate cmov here, but this branch is extremely
1388          * predictable (it's just a funciton of time and the likely is
1389          * very likely) and there's a data dependence, so force GCC
1390          * to generate a branch instead.  I don't barrier() because
1391          * we don't actually need a barrier, and if this function
1392          * ever gets inlined it will generate worse code.
1393          */
1394         asm volatile ("");
1395         return last;
1396 }
1397
1398 static inline u64 vgettsc(cycle_t *cycle_now)
1399 {
1400         long v;
1401         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1402
1403         *cycle_now = read_tsc();
1404
1405         v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1406         return v * gtod->clock.mult;
1407 }
1408
1409 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1410 {
1411         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1412         unsigned long seq;
1413         int mode;
1414         u64 ns;
1415
1416         do {
1417                 seq = read_seqcount_begin(&gtod->seq);
1418                 mode = gtod->clock.vclock_mode;
1419                 ns = gtod->nsec_base;
1420                 ns += vgettsc(cycle_now);
1421                 ns >>= gtod->clock.shift;
1422                 ns += gtod->boot_ns;
1423         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1424         *t = ns;
1425
1426         return mode;
1427 }
1428
1429 /* returns true if host is using tsc clocksource */
1430 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1431 {
1432         /* checked again under seqlock below */
1433         if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1434                 return false;
1435
1436         return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1437 }
1438 #endif
1439
1440 /*
1441  *
1442  * Assuming a stable TSC across physical CPUS, and a stable TSC
1443  * across virtual CPUs, the following condition is possible.
1444  * Each numbered line represents an event visible to both
1445  * CPUs at the next numbered event.
1446  *
1447  * "timespecX" represents host monotonic time. "tscX" represents
1448  * RDTSC value.
1449  *
1450  *              VCPU0 on CPU0           |       VCPU1 on CPU1
1451  *
1452  * 1.  read timespec0,tsc0
1453  * 2.                                   | timespec1 = timespec0 + N
1454  *                                      | tsc1 = tsc0 + M
1455  * 3. transition to guest               | transition to guest
1456  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1457  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
1458  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1459  *
1460  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1461  *
1462  *      - ret0 < ret1
1463  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1464  *              ...
1465  *      - 0 < N - M => M < N
1466  *
1467  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1468  * always the case (the difference between two distinct xtime instances
1469  * might be smaller then the difference between corresponding TSC reads,
1470  * when updating guest vcpus pvclock areas).
1471  *
1472  * To avoid that problem, do not allow visibility of distinct
1473  * system_timestamp/tsc_timestamp values simultaneously: use a master
1474  * copy of host monotonic time values. Update that master copy
1475  * in lockstep.
1476  *
1477  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1478  *
1479  */
1480
1481 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1482 {
1483 #ifdef CONFIG_X86_64
1484         struct kvm_arch *ka = &kvm->arch;
1485         int vclock_mode;
1486         bool host_tsc_clocksource, vcpus_matched;
1487
1488         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1489                         atomic_read(&kvm->online_vcpus));
1490
1491         /*
1492          * If the host uses TSC clock, then passthrough TSC as stable
1493          * to the guest.
1494          */
1495         host_tsc_clocksource = kvm_get_time_and_clockread(
1496                                         &ka->master_kernel_ns,
1497                                         &ka->master_cycle_now);
1498
1499         ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1500                                 && !backwards_tsc_observed;
1501
1502         if (ka->use_master_clock)
1503                 atomic_set(&kvm_guest_has_master_clock, 1);
1504
1505         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1506         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1507                                         vcpus_matched);
1508 #endif
1509 }
1510
1511 static void kvm_gen_update_masterclock(struct kvm *kvm)
1512 {
1513 #ifdef CONFIG_X86_64
1514         int i;
1515         struct kvm_vcpu *vcpu;
1516         struct kvm_arch *ka = &kvm->arch;
1517
1518         spin_lock(&ka->pvclock_gtod_sync_lock);
1519         kvm_make_mclock_inprogress_request(kvm);
1520         /* no guest entries from this point */
1521         pvclock_update_vm_gtod_copy(kvm);
1522
1523         kvm_for_each_vcpu(i, vcpu, kvm)
1524                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1525
1526         /* guest entries allowed */
1527         kvm_for_each_vcpu(i, vcpu, kvm)
1528                 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1529
1530         spin_unlock(&ka->pvclock_gtod_sync_lock);
1531 #endif
1532 }
1533
1534 static int kvm_guest_time_update(struct kvm_vcpu *v)
1535 {
1536         unsigned long flags, this_tsc_khz;
1537         struct kvm_vcpu_arch *vcpu = &v->arch;
1538         struct kvm_arch *ka = &v->kvm->arch;
1539         s64 kernel_ns;
1540         u64 tsc_timestamp, host_tsc;
1541         struct pvclock_vcpu_time_info guest_hv_clock;
1542         u8 pvclock_flags;
1543         bool use_master_clock;
1544
1545         kernel_ns = 0;
1546         host_tsc = 0;
1547
1548         /*
1549          * If the host uses TSC clock, then passthrough TSC as stable
1550          * to the guest.
1551          */
1552         spin_lock(&ka->pvclock_gtod_sync_lock);
1553         use_master_clock = ka->use_master_clock;
1554         if (use_master_clock) {
1555                 host_tsc = ka->master_cycle_now;
1556                 kernel_ns = ka->master_kernel_ns;
1557         }
1558         spin_unlock(&ka->pvclock_gtod_sync_lock);
1559
1560         /* Keep irq disabled to prevent changes to the clock */
1561         local_irq_save(flags);
1562         this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1563         if (unlikely(this_tsc_khz == 0)) {
1564                 local_irq_restore(flags);
1565                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1566                 return 1;
1567         }
1568         if (!use_master_clock) {
1569                 host_tsc = native_read_tsc();
1570                 kernel_ns = get_kernel_ns();
1571         }
1572
1573         tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1574
1575         /*
1576          * We may have to catch up the TSC to match elapsed wall clock
1577          * time for two reasons, even if kvmclock is used.
1578          *   1) CPU could have been running below the maximum TSC rate
1579          *   2) Broken TSC compensation resets the base at each VCPU
1580          *      entry to avoid unknown leaps of TSC even when running
1581          *      again on the same CPU.  This may cause apparent elapsed
1582          *      time to disappear, and the guest to stand still or run
1583          *      very slowly.
1584          */
1585         if (vcpu->tsc_catchup) {
1586                 u64 tsc = compute_guest_tsc(v, kernel_ns);
1587                 if (tsc > tsc_timestamp) {
1588                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1589                         tsc_timestamp = tsc;
1590                 }
1591         }
1592
1593         local_irq_restore(flags);
1594
1595         if (!vcpu->pv_time_enabled)
1596                 return 0;
1597
1598         if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1599                 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1600                                    &vcpu->hv_clock.tsc_shift,
1601                                    &vcpu->hv_clock.tsc_to_system_mul);
1602                 vcpu->hw_tsc_khz = this_tsc_khz;
1603         }
1604
1605         /* With all the info we got, fill in the values */
1606         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1607         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1608         vcpu->last_guest_tsc = tsc_timestamp;
1609
1610         /*
1611          * The interface expects us to write an even number signaling that the
1612          * update is finished. Since the guest won't see the intermediate
1613          * state, we just increase by 2 at the end.
1614          */
1615         vcpu->hv_clock.version += 2;
1616
1617         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1618                 &guest_hv_clock, sizeof(guest_hv_clock))))
1619                 return 0;
1620
1621         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1622         pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1623
1624         if (vcpu->pvclock_set_guest_stopped_request) {
1625                 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1626                 vcpu->pvclock_set_guest_stopped_request = false;
1627         }
1628
1629         /* If the host uses TSC clocksource, then it is stable */
1630         if (use_master_clock)
1631                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1632
1633         vcpu->hv_clock.flags = pvclock_flags;
1634
1635         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1636                                 &vcpu->hv_clock,
1637                                 sizeof(vcpu->hv_clock));
1638         return 0;
1639 }
1640
1641 /*
1642  * kvmclock updates which are isolated to a given vcpu, such as
1643  * vcpu->cpu migration, should not allow system_timestamp from
1644  * the rest of the vcpus to remain static. Otherwise ntp frequency
1645  * correction applies to one vcpu's system_timestamp but not
1646  * the others.
1647  *
1648  * So in those cases, request a kvmclock update for all vcpus.
1649  * We need to rate-limit these requests though, as they can
1650  * considerably slow guests that have a large number of vcpus.
1651  * The time for a remote vcpu to update its kvmclock is bound
1652  * by the delay we use to rate-limit the updates.
1653  */
1654
1655 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1656
1657 static void kvmclock_update_fn(struct work_struct *work)
1658 {
1659         int i;
1660         struct delayed_work *dwork = to_delayed_work(work);
1661         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1662                                            kvmclock_update_work);
1663         struct kvm *kvm = container_of(ka, struct kvm, arch);
1664         struct kvm_vcpu *vcpu;
1665
1666         kvm_for_each_vcpu(i, vcpu, kvm) {
1667                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1668                 kvm_vcpu_kick(vcpu);
1669         }
1670 }
1671
1672 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1673 {
1674         struct kvm *kvm = v->kvm;
1675
1676         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1677         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1678                                         KVMCLOCK_UPDATE_DELAY);
1679 }
1680
1681 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1682
1683 static void kvmclock_sync_fn(struct work_struct *work)
1684 {
1685         struct delayed_work *dwork = to_delayed_work(work);
1686         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1687                                            kvmclock_sync_work);
1688         struct kvm *kvm = container_of(ka, struct kvm, arch);
1689
1690         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1691         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1692                                         KVMCLOCK_SYNC_PERIOD);
1693 }
1694
1695 static bool msr_mtrr_valid(unsigned msr)
1696 {
1697         switch (msr) {
1698         case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1699         case MSR_MTRRfix64K_00000:
1700         case MSR_MTRRfix16K_80000:
1701         case MSR_MTRRfix16K_A0000:
1702         case MSR_MTRRfix4K_C0000:
1703         case MSR_MTRRfix4K_C8000:
1704         case MSR_MTRRfix4K_D0000:
1705         case MSR_MTRRfix4K_D8000:
1706         case MSR_MTRRfix4K_E0000:
1707         case MSR_MTRRfix4K_E8000:
1708         case MSR_MTRRfix4K_F0000:
1709         case MSR_MTRRfix4K_F8000:
1710         case MSR_MTRRdefType:
1711         case MSR_IA32_CR_PAT:
1712                 return true;
1713         case 0x2f8:
1714                 return true;
1715         }
1716         return false;
1717 }
1718
1719 static bool valid_pat_type(unsigned t)
1720 {
1721         return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1722 }
1723
1724 static bool valid_mtrr_type(unsigned t)
1725 {
1726         return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1727 }
1728
1729 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1730 {
1731         int i;
1732         u64 mask;
1733
1734         if (!msr_mtrr_valid(msr))
1735                 return false;
1736
1737         if (msr == MSR_IA32_CR_PAT) {
1738                 for (i = 0; i < 8; i++)
1739                         if (!valid_pat_type((data >> (i * 8)) & 0xff))
1740                                 return false;
1741                 return true;
1742         } else if (msr == MSR_MTRRdefType) {
1743                 if (data & ~0xcff)
1744                         return false;
1745                 return valid_mtrr_type(data & 0xff);
1746         } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1747                 for (i = 0; i < 8 ; i++)
1748                         if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1749                                 return false;
1750                 return true;
1751         }
1752
1753         /* variable MTRRs */
1754         WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1755
1756         mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
1757         if ((msr & 1) == 0) {
1758                 /* MTRR base */
1759                 if (!valid_mtrr_type(data & 0xff))
1760                         return false;
1761                 mask |= 0xf00;
1762         } else
1763                 /* MTRR mask */
1764                 mask |= 0x7ff;
1765         if (data & mask) {
1766                 kvm_inject_gp(vcpu, 0);
1767                 return false;
1768         }
1769
1770         return true;
1771 }
1772 EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
1773
1774 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1775 {
1776         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1777
1778         if (!kvm_mtrr_valid(vcpu, msr, data))
1779                 return 1;
1780
1781         if (msr == MSR_MTRRdefType) {
1782                 vcpu->arch.mtrr_state.def_type = data;
1783                 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1784         } else if (msr == MSR_MTRRfix64K_00000)
1785                 p[0] = data;
1786         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1787                 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1788         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1789                 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1790         else if (msr == MSR_IA32_CR_PAT)
1791                 vcpu->arch.pat = data;
1792         else {  /* Variable MTRRs */
1793                 int idx, is_mtrr_mask;
1794                 u64 *pt;
1795
1796                 idx = (msr - 0x200) / 2;
1797                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1798                 if (!is_mtrr_mask)
1799                         pt =
1800                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1801                 else
1802                         pt =
1803                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1804                 *pt = data;
1805         }
1806
1807         kvm_mmu_reset_context(vcpu);
1808         return 0;
1809 }
1810
1811 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1812 {
1813         u64 mcg_cap = vcpu->arch.mcg_cap;
1814         unsigned bank_num = mcg_cap & 0xff;
1815
1816         switch (msr) {
1817         case MSR_IA32_MCG_STATUS:
1818                 vcpu->arch.mcg_status = data;
1819                 break;
1820         case MSR_IA32_MCG_CTL:
1821                 if (!(mcg_cap & MCG_CTL_P))
1822                         return 1;
1823                 if (data != 0 && data != ~(u64)0)
1824                         return -1;
1825                 vcpu->arch.mcg_ctl = data;
1826                 break;
1827         default:
1828                 if (msr >= MSR_IA32_MC0_CTL &&
1829                     msr < MSR_IA32_MCx_CTL(bank_num)) {
1830                         u32 offset = msr - MSR_IA32_MC0_CTL;
1831                         /* only 0 or all 1s can be written to IA32_MCi_CTL
1832                          * some Linux kernels though clear bit 10 in bank 4 to
1833                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1834                          * this to avoid an uncatched #GP in the guest
1835                          */
1836                         if ((offset & 0x3) == 0 &&
1837                             data != 0 && (data | (1 << 10)) != ~(u64)0)
1838                                 return -1;
1839                         vcpu->arch.mce_banks[offset] = data;
1840                         break;
1841                 }
1842                 return 1;
1843         }
1844         return 0;
1845 }
1846
1847 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1848 {
1849         struct kvm *kvm = vcpu->kvm;
1850         int lm = is_long_mode(vcpu);
1851         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1852                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1853         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1854                 : kvm->arch.xen_hvm_config.blob_size_32;
1855         u32 page_num = data & ~PAGE_MASK;
1856         u64 page_addr = data & PAGE_MASK;
1857         u8 *page;
1858         int r;
1859
1860         r = -E2BIG;
1861         if (page_num >= blob_size)
1862                 goto out;
1863         r = -ENOMEM;
1864         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1865         if (IS_ERR(page)) {
1866                 r = PTR_ERR(page);
1867                 goto out;
1868         }
1869         if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1870                 goto out_free;
1871         r = 0;
1872 out_free:
1873         kfree(page);
1874 out:
1875         return r;
1876 }
1877
1878 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1879 {
1880         return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1881 }
1882
1883 static bool kvm_hv_msr_partition_wide(u32 msr)
1884 {
1885         bool r = false;
1886         switch (msr) {
1887         case HV_X64_MSR_GUEST_OS_ID:
1888         case HV_X64_MSR_HYPERCALL:
1889         case HV_X64_MSR_REFERENCE_TSC:
1890         case HV_X64_MSR_TIME_REF_COUNT:
1891                 r = true;
1892                 break;
1893         }
1894
1895         return r;
1896 }
1897
1898 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1899 {
1900         struct kvm *kvm = vcpu->kvm;
1901
1902         switch (msr) {
1903         case HV_X64_MSR_GUEST_OS_ID:
1904                 kvm->arch.hv_guest_os_id = data;
1905                 /* setting guest os id to zero disables hypercall page */
1906                 if (!kvm->arch.hv_guest_os_id)
1907                         kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1908                 break;
1909         case HV_X64_MSR_HYPERCALL: {
1910                 u64 gfn;
1911                 unsigned long addr;
1912                 u8 instructions[4];
1913
1914                 /* if guest os id is not set hypercall should remain disabled */
1915                 if (!kvm->arch.hv_guest_os_id)
1916                         break;
1917                 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1918                         kvm->arch.hv_hypercall = data;
1919                         break;
1920                 }
1921                 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1922                 addr = gfn_to_hva(kvm, gfn);
1923                 if (kvm_is_error_hva(addr))
1924                         return 1;
1925                 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1926                 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1927                 if (__copy_to_user((void __user *)addr, instructions, 4))
1928                         return 1;
1929                 kvm->arch.hv_hypercall = data;
1930                 mark_page_dirty(kvm, gfn);
1931                 break;
1932         }
1933         case HV_X64_MSR_REFERENCE_TSC: {
1934                 u64 gfn;
1935                 HV_REFERENCE_TSC_PAGE tsc_ref;
1936                 memset(&tsc_ref, 0, sizeof(tsc_ref));
1937                 kvm->arch.hv_tsc_page = data;
1938                 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1939                         break;
1940                 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1941                 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
1942                         &tsc_ref, sizeof(tsc_ref)))
1943                         return 1;
1944                 mark_page_dirty(kvm, gfn);
1945                 break;
1946         }
1947         default:
1948                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1949                             "data 0x%llx\n", msr, data);
1950                 return 1;
1951         }
1952         return 0;
1953 }
1954
1955 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1956 {
1957         switch (msr) {
1958         case HV_X64_MSR_APIC_ASSIST_PAGE: {
1959                 u64 gfn;
1960                 unsigned long addr;
1961
1962                 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1963                         vcpu->arch.hv_vapic = data;
1964                         if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1965                                 return 1;
1966                         break;
1967                 }
1968                 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1969                 addr = gfn_to_hva(vcpu->kvm, gfn);
1970                 if (kvm_is_error_hva(addr))
1971                         return 1;
1972                 if (__clear_user((void __user *)addr, PAGE_SIZE))
1973                         return 1;
1974                 vcpu->arch.hv_vapic = data;
1975                 mark_page_dirty(vcpu->kvm, gfn);
1976                 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1977                         return 1;
1978                 break;
1979         }
1980         case HV_X64_MSR_EOI:
1981                 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1982         case HV_X64_MSR_ICR:
1983                 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1984         case HV_X64_MSR_TPR:
1985                 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1986         default:
1987                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1988                             "data 0x%llx\n", msr, data);
1989                 return 1;
1990         }
1991
1992         return 0;
1993 }
1994
1995 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1996 {
1997         gpa_t gpa = data & ~0x3f;
1998
1999         /* Bits 2:5 are reserved, Should be zero */
2000         if (data & 0x3c)
2001                 return 1;
2002
2003         vcpu->arch.apf.msr_val = data;
2004
2005         if (!(data & KVM_ASYNC_PF_ENABLED)) {
2006                 kvm_clear_async_pf_completion_queue(vcpu);
2007                 kvm_async_pf_hash_reset(vcpu);
2008                 return 0;
2009         }
2010
2011         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2012                                         sizeof(u32)))
2013                 return 1;
2014
2015         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2016         kvm_async_pf_wakeup_all(vcpu);
2017         return 0;
2018 }
2019
2020 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2021 {
2022         vcpu->arch.pv_time_enabled = false;
2023 }
2024
2025 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2026 {
2027         u64 delta;
2028
2029         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2030                 return;
2031
2032         delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2033         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2034         vcpu->arch.st.accum_steal = delta;
2035 }
2036
2037 static void record_steal_time(struct kvm_vcpu *vcpu)
2038 {
2039         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2040                 return;
2041
2042         if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2043                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2044                 return;
2045
2046         vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2047         vcpu->arch.st.steal.version += 2;
2048         vcpu->arch.st.accum_steal = 0;
2049
2050         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2051                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2052 }
2053
2054 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2055 {
2056         bool pr = false;
2057         u32 msr = msr_info->index;
2058         u64 data = msr_info->data;
2059
2060         switch (msr) {
2061         case MSR_AMD64_NB_CFG:
2062         case MSR_IA32_UCODE_REV:
2063         case MSR_IA32_UCODE_WRITE:
2064         case MSR_VM_HSAVE_PA:
2065         case MSR_AMD64_PATCH_LOADER:
2066         case MSR_AMD64_BU_CFG2:
2067                 break;
2068
2069         case MSR_EFER:
2070                 return set_efer(vcpu, data);
2071         case MSR_K7_HWCR:
2072                 data &= ~(u64)0x40;     /* ignore flush filter disable */
2073                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
2074                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
2075                 data &= ~(u64)0x40000;  /* ignore Mc status write enable */
2076                 if (data != 0) {
2077                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2078                                     data);
2079                         return 1;
2080                 }
2081                 break;
2082         case MSR_FAM10H_MMIO_CONF_BASE:
2083                 if (data != 0) {
2084                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2085                                     "0x%llx\n", data);
2086                         return 1;
2087                 }
2088                 break;
2089         case MSR_IA32_DEBUGCTLMSR:
2090                 if (!data) {
2091                         /* We support the non-activated case already */
2092                         break;
2093                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2094                         /* Values other than LBR and BTF are vendor-specific,
2095                            thus reserved and should throw a #GP */
2096                         return 1;
2097                 }
2098                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2099                             __func__, data);
2100                 break;
2101         case 0x200 ... 0x2ff:
2102                 return set_msr_mtrr(vcpu, msr, data);
2103         case MSR_IA32_APICBASE:
2104                 return kvm_set_apic_base(vcpu, msr_info);
2105         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2106                 return kvm_x2apic_msr_write(vcpu, msr, data);
2107         case MSR_IA32_TSCDEADLINE:
2108                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2109                 break;
2110         case MSR_IA32_TSC_ADJUST:
2111                 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2112                         if (!msr_info->host_initiated) {
2113                                 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2114                                 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2115                         }
2116                         vcpu->arch.ia32_tsc_adjust_msr = data;
2117                 }
2118                 break;
2119         case MSR_IA32_MISC_ENABLE:
2120                 vcpu->arch.ia32_misc_enable_msr = data;
2121                 break;
2122         case MSR_KVM_WALL_CLOCK_NEW:
2123         case MSR_KVM_WALL_CLOCK:
2124                 vcpu->kvm->arch.wall_clock = data;
2125                 kvm_write_wall_clock(vcpu->kvm, data);
2126                 break;
2127         case MSR_KVM_SYSTEM_TIME_NEW:
2128         case MSR_KVM_SYSTEM_TIME: {
2129                 u64 gpa_offset;
2130                 kvmclock_reset(vcpu);
2131
2132                 vcpu->arch.time = data;
2133                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2134
2135                 /* we verify if the enable bit is set... */
2136                 if (!(data & 1))
2137                         break;
2138
2139                 gpa_offset = data & ~(PAGE_MASK | 1);
2140
2141                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2142                      &vcpu->arch.pv_time, data & ~1ULL,
2143                      sizeof(struct pvclock_vcpu_time_info)))
2144                         vcpu->arch.pv_time_enabled = false;
2145                 else
2146                         vcpu->arch.pv_time_enabled = true;
2147
2148                 break;
2149         }
2150         case MSR_KVM_ASYNC_PF_EN:
2151                 if (kvm_pv_enable_async_pf(vcpu, data))
2152                         return 1;
2153                 break;
2154         case MSR_KVM_STEAL_TIME:
2155
2156                 if (unlikely(!sched_info_on()))
2157                         return 1;
2158
2159                 if (data & KVM_STEAL_RESERVED_MASK)
2160                         return 1;
2161
2162                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2163                                                 data & KVM_STEAL_VALID_BITS,
2164                                                 sizeof(struct kvm_steal_time)))
2165                         return 1;
2166
2167                 vcpu->arch.st.msr_val = data;
2168
2169                 if (!(data & KVM_MSR_ENABLED))
2170                         break;
2171
2172                 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2173
2174                 preempt_disable();
2175                 accumulate_steal_time(vcpu);
2176                 preempt_enable();
2177
2178                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2179
2180                 break;
2181         case MSR_KVM_PV_EOI_EN:
2182                 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2183                         return 1;
2184                 break;
2185
2186         case MSR_IA32_MCG_CTL:
2187         case MSR_IA32_MCG_STATUS:
2188         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2189                 return set_msr_mce(vcpu, msr, data);
2190
2191         /* Performance counters are not protected by a CPUID bit,
2192          * so we should check all of them in the generic path for the sake of
2193          * cross vendor migration.
2194          * Writing a zero into the event select MSRs disables them,
2195          * which we perfectly emulate ;-). Any other value should be at least
2196          * reported, some guests depend on them.
2197          */
2198         case MSR_K7_EVNTSEL0:
2199         case MSR_K7_EVNTSEL1:
2200         case MSR_K7_EVNTSEL2:
2201         case MSR_K7_EVNTSEL3:
2202                 if (data != 0)
2203                         vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2204                                     "0x%x data 0x%llx\n", msr, data);
2205                 break;
2206         /* at least RHEL 4 unconditionally writes to the perfctr registers,
2207          * so we ignore writes to make it happy.
2208          */
2209         case MSR_K7_PERFCTR0:
2210         case MSR_K7_PERFCTR1:
2211         case MSR_K7_PERFCTR2:
2212         case MSR_K7_PERFCTR3:
2213                 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2214                             "0x%x data 0x%llx\n", msr, data);
2215                 break;
2216         case MSR_P6_PERFCTR0:
2217         case MSR_P6_PERFCTR1:
2218                 pr = true;
2219         case MSR_P6_EVNTSEL0:
2220         case MSR_P6_EVNTSEL1:
2221                 if (kvm_pmu_msr(vcpu, msr))
2222                         return kvm_pmu_set_msr(vcpu, msr_info);
2223
2224                 if (pr || data != 0)
2225                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2226                                     "0x%x data 0x%llx\n", msr, data);
2227                 break;
2228         case MSR_K7_CLK_CTL:
2229                 /*
2230                  * Ignore all writes to this no longer documented MSR.
2231                  * Writes are only relevant for old K7 processors,
2232                  * all pre-dating SVM, but a recommended workaround from
2233                  * AMD for these chips. It is possible to specify the
2234                  * affected processor models on the command line, hence
2235                  * the need to ignore the workaround.
2236                  */
2237                 break;
2238         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2239                 if (kvm_hv_msr_partition_wide(msr)) {
2240                         int r;
2241                         mutex_lock(&vcpu->kvm->lock);
2242                         r = set_msr_hyperv_pw(vcpu, msr, data);
2243                         mutex_unlock(&vcpu->kvm->lock);
2244                         return r;
2245                 } else
2246                         return set_msr_hyperv(vcpu, msr, data);
2247                 break;
2248         case MSR_IA32_BBL_CR_CTL3:
2249                 /* Drop writes to this legacy MSR -- see rdmsr
2250                  * counterpart for further detail.
2251                  */
2252                 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2253                 break;
2254         case MSR_AMD64_OSVW_ID_LENGTH:
2255                 if (!guest_cpuid_has_osvw(vcpu))
2256                         return 1;
2257                 vcpu->arch.osvw.length = data;
2258                 break;
2259         case MSR_AMD64_OSVW_STATUS:
2260                 if (!guest_cpuid_has_osvw(vcpu))
2261                         return 1;
2262                 vcpu->arch.osvw.status = data;
2263                 break;
2264         default:
2265                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2266                         return xen_hvm_config(vcpu, data);
2267                 if (kvm_pmu_msr(vcpu, msr))
2268                         return kvm_pmu_set_msr(vcpu, msr_info);
2269                 if (!ignore_msrs) {
2270                         vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2271                                     msr, data);
2272                         return 1;
2273                 } else {
2274                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2275                                     msr, data);
2276                         break;
2277                 }
2278         }
2279         return 0;
2280 }
2281 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2282
2283
2284 /*
2285  * Reads an msr value (of 'msr_index') into 'pdata'.
2286  * Returns 0 on success, non-0 otherwise.
2287  * Assumes vcpu_load() was already called.
2288  */
2289 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2290 {
2291         return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2292 }
2293
2294 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2295 {
2296         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2297
2298         if (!msr_mtrr_valid(msr))
2299                 return 1;
2300
2301         if (msr == MSR_MTRRdefType)
2302                 *pdata = vcpu->arch.mtrr_state.def_type +
2303                          (vcpu->arch.mtrr_state.enabled << 10);
2304         else if (msr == MSR_MTRRfix64K_00000)
2305                 *pdata = p[0];
2306         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2307                 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2308         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2309                 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2310         else if (msr == MSR_IA32_CR_PAT)
2311                 *pdata = vcpu->arch.pat;
2312         else {  /* Variable MTRRs */
2313                 int idx, is_mtrr_mask;
2314                 u64 *pt;
2315
2316                 idx = (msr - 0x200) / 2;
2317                 is_mtrr_mask = msr - 0x200 - 2 * idx;
2318                 if (!is_mtrr_mask)
2319                         pt =
2320                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2321                 else
2322                         pt =
2323                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2324                 *pdata = *pt;
2325         }
2326
2327         return 0;
2328 }
2329
2330 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2331 {
2332         u64 data;
2333         u64 mcg_cap = vcpu->arch.mcg_cap;
2334         unsigned bank_num = mcg_cap & 0xff;
2335
2336         switch (msr) {
2337         case MSR_IA32_P5_MC_ADDR:
2338         case MSR_IA32_P5_MC_TYPE:
2339                 data = 0;
2340                 break;
2341         case MSR_IA32_MCG_CAP:
2342                 data = vcpu->arch.mcg_cap;
2343                 break;
2344         case MSR_IA32_MCG_CTL:
2345                 if (!(mcg_cap & MCG_CTL_P))
2346                         return 1;
2347                 data = vcpu->arch.mcg_ctl;
2348                 break;
2349         case MSR_IA32_MCG_STATUS:
2350                 data = vcpu->arch.mcg_status;
2351                 break;
2352         default:
2353                 if (msr >= MSR_IA32_MC0_CTL &&
2354                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2355                         u32 offset = msr - MSR_IA32_MC0_CTL;
2356                         data = vcpu->arch.mce_banks[offset];
2357                         break;
2358                 }
2359                 return 1;
2360         }
2361         *pdata = data;
2362         return 0;
2363 }
2364
2365 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2366 {
2367         u64 data = 0;
2368         struct kvm *kvm = vcpu->kvm;
2369
2370         switch (msr) {
2371         case HV_X64_MSR_GUEST_OS_ID:
2372                 data = kvm->arch.hv_guest_os_id;
2373                 break;
2374         case HV_X64_MSR_HYPERCALL:
2375                 data = kvm->arch.hv_hypercall;
2376                 break;
2377         case HV_X64_MSR_TIME_REF_COUNT: {
2378                 data =
2379                      div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2380                 break;
2381         }
2382         case HV_X64_MSR_REFERENCE_TSC:
2383                 data = kvm->arch.hv_tsc_page;
2384                 break;
2385         default:
2386                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2387                 return 1;
2388         }
2389
2390         *pdata = data;
2391         return 0;
2392 }
2393
2394 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2395 {
2396         u64 data = 0;
2397
2398         switch (msr) {
2399         case HV_X64_MSR_VP_INDEX: {
2400                 int r;
2401                 struct kvm_vcpu *v;
2402                 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2403                         if (v == vcpu) {
2404                                 data = r;
2405                                 break;
2406                         }
2407                 }
2408                 break;
2409         }
2410         case HV_X64_MSR_EOI:
2411                 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2412         case HV_X64_MSR_ICR:
2413                 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2414         case HV_X64_MSR_TPR:
2415                 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2416         case HV_X64_MSR_APIC_ASSIST_PAGE:
2417                 data = vcpu->arch.hv_vapic;
2418                 break;
2419         default:
2420                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2421                 return 1;
2422         }
2423         *pdata = data;
2424         return 0;
2425 }
2426
2427 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2428 {
2429         u64 data;
2430
2431         switch (msr) {
2432         case MSR_IA32_PLATFORM_ID:
2433         case MSR_IA32_EBL_CR_POWERON:
2434         case MSR_IA32_DEBUGCTLMSR:
2435         case MSR_IA32_LASTBRANCHFROMIP:
2436         case MSR_IA32_LASTBRANCHTOIP:
2437         case MSR_IA32_LASTINTFROMIP:
2438         case MSR_IA32_LASTINTTOIP:
2439         case MSR_K8_SYSCFG:
2440         case MSR_K7_HWCR:
2441         case MSR_VM_HSAVE_PA:
2442         case MSR_K7_EVNTSEL0:
2443         case MSR_K7_EVNTSEL1:
2444         case MSR_K7_EVNTSEL2:
2445         case MSR_K7_EVNTSEL3:
2446         case MSR_K7_PERFCTR0:
2447         case MSR_K7_PERFCTR1:
2448         case MSR_K7_PERFCTR2:
2449         case MSR_K7_PERFCTR3:
2450         case MSR_K8_INT_PENDING_MSG:
2451         case MSR_AMD64_NB_CFG:
2452         case MSR_FAM10H_MMIO_CONF_BASE:
2453         case MSR_AMD64_BU_CFG2:
2454                 data = 0;
2455                 break;
2456         case MSR_P6_PERFCTR0:
2457         case MSR_P6_PERFCTR1:
2458         case MSR_P6_EVNTSEL0:
2459         case MSR_P6_EVNTSEL1:
2460                 if (kvm_pmu_msr(vcpu, msr))
2461                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2462                 data = 0;
2463                 break;
2464         case MSR_IA32_UCODE_REV:
2465                 data = 0x100000000ULL;
2466                 break;
2467         case MSR_MTRRcap:
2468                 data = 0x500 | KVM_NR_VAR_MTRR;
2469                 break;
2470         case 0x200 ... 0x2ff:
2471                 return get_msr_mtrr(vcpu, msr, pdata);
2472         case 0xcd: /* fsb frequency */
2473                 data = 3;
2474                 break;
2475                 /*
2476                  * MSR_EBC_FREQUENCY_ID
2477                  * Conservative value valid for even the basic CPU models.
2478                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2479                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2480                  * and 266MHz for model 3, or 4. Set Core Clock
2481                  * Frequency to System Bus Frequency Ratio to 1 (bits
2482                  * 31:24) even though these are only valid for CPU
2483                  * models > 2, however guests may end up dividing or
2484                  * multiplying by zero otherwise.
2485                  */
2486         case MSR_EBC_FREQUENCY_ID:
2487                 data = 1 << 24;
2488                 break;
2489         case MSR_IA32_APICBASE:
2490                 data = kvm_get_apic_base(vcpu);
2491                 break;
2492         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2493                 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2494                 break;
2495         case MSR_IA32_TSCDEADLINE:
2496                 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2497                 break;
2498         case MSR_IA32_TSC_ADJUST:
2499                 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2500                 break;
2501         case MSR_IA32_MISC_ENABLE:
2502                 data = vcpu->arch.ia32_misc_enable_msr;
2503                 break;
2504         case MSR_IA32_PERF_STATUS:
2505                 /* TSC increment by tick */
2506                 data = 1000ULL;
2507                 /* CPU multiplier */
2508                 data |= (((uint64_t)4ULL) << 40);
2509                 break;
2510         case MSR_EFER:
2511                 data = vcpu->arch.efer;
2512                 break;
2513         case MSR_KVM_WALL_CLOCK:
2514         case MSR_KVM_WALL_CLOCK_NEW:
2515                 data = vcpu->kvm->arch.wall_clock;
2516                 break;
2517         case MSR_KVM_SYSTEM_TIME:
2518         case MSR_KVM_SYSTEM_TIME_NEW:
2519                 data = vcpu->arch.time;
2520                 break;
2521         case MSR_KVM_ASYNC_PF_EN:
2522                 data = vcpu->arch.apf.msr_val;
2523                 break;
2524         case MSR_KVM_STEAL_TIME:
2525                 data = vcpu->arch.st.msr_val;
2526                 break;
2527         case MSR_KVM_PV_EOI_EN:
2528                 data = vcpu->arch.pv_eoi.msr_val;
2529                 break;
2530         case MSR_IA32_P5_MC_ADDR:
2531         case MSR_IA32_P5_MC_TYPE:
2532         case MSR_IA32_MCG_CAP:
2533         case MSR_IA32_MCG_CTL:
2534         case MSR_IA32_MCG_STATUS:
2535         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2536                 return get_msr_mce(vcpu, msr, pdata);
2537         case MSR_K7_CLK_CTL:
2538                 /*
2539                  * Provide expected ramp-up count for K7. All other
2540                  * are set to zero, indicating minimum divisors for
2541                  * every field.
2542                  *
2543                  * This prevents guest kernels on AMD host with CPU
2544                  * type 6, model 8 and higher from exploding due to
2545                  * the rdmsr failing.
2546                  */
2547                 data = 0x20000000;
2548                 break;
2549         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2550                 if (kvm_hv_msr_partition_wide(msr)) {
2551                         int r;
2552                         mutex_lock(&vcpu->kvm->lock);
2553                         r = get_msr_hyperv_pw(vcpu, msr, pdata);
2554                         mutex_unlock(&vcpu->kvm->lock);
2555                         return r;
2556                 } else
2557                         return get_msr_hyperv(vcpu, msr, pdata);
2558                 break;
2559         case MSR_IA32_BBL_CR_CTL3:
2560                 /* This legacy MSR exists but isn't fully documented in current
2561                  * silicon.  It is however accessed by winxp in very narrow
2562                  * scenarios where it sets bit #19, itself documented as
2563                  * a "reserved" bit.  Best effort attempt to source coherent
2564                  * read data here should the balance of the register be
2565                  * interpreted by the guest:
2566                  *
2567                  * L2 cache control register 3: 64GB range, 256KB size,
2568                  * enabled, latency 0x1, configured
2569                  */
2570                 data = 0xbe702111;
2571                 break;
2572         case MSR_AMD64_OSVW_ID_LENGTH:
2573                 if (!guest_cpuid_has_osvw(vcpu))
2574                         return 1;
2575                 data = vcpu->arch.osvw.length;
2576                 break;
2577         case MSR_AMD64_OSVW_STATUS:
2578                 if (!guest_cpuid_has_osvw(vcpu))
2579                         return 1;
2580                 data = vcpu->arch.osvw.status;
2581                 break;
2582         default:
2583                 if (kvm_pmu_msr(vcpu, msr))
2584                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2585                 if (!ignore_msrs) {
2586                         vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2587                         return 1;
2588                 } else {
2589                         vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2590                         data = 0;
2591                 }
2592                 break;
2593         }
2594         *pdata = data;
2595         return 0;
2596 }
2597 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2598
2599 /*
2600  * Read or write a bunch of msrs. All parameters are kernel addresses.
2601  *
2602  * @return number of msrs set successfully.
2603  */
2604 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2605                     struct kvm_msr_entry *entries,
2606                     int (*do_msr)(struct kvm_vcpu *vcpu,
2607                                   unsigned index, u64 *data))
2608 {
2609         int i, idx;
2610
2611         idx = srcu_read_lock(&vcpu->kvm->srcu);
2612         for (i = 0; i < msrs->nmsrs; ++i)
2613                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2614                         break;
2615         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2616
2617         return i;
2618 }
2619
2620 /*
2621  * Read or write a bunch of msrs. Parameters are user addresses.
2622  *
2623  * @return number of msrs set successfully.
2624  */
2625 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2626                   int (*do_msr)(struct kvm_vcpu *vcpu,
2627                                 unsigned index, u64 *data),
2628                   int writeback)
2629 {
2630         struct kvm_msrs msrs;
2631         struct kvm_msr_entry *entries;
2632         int r, n;
2633         unsigned size;
2634
2635         r = -EFAULT;
2636         if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2637                 goto out;
2638
2639         r = -E2BIG;
2640         if (msrs.nmsrs >= MAX_IO_MSRS)
2641                 goto out;
2642
2643         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2644         entries = memdup_user(user_msrs->entries, size);
2645         if (IS_ERR(entries)) {
2646                 r = PTR_ERR(entries);
2647                 goto out;
2648         }
2649
2650         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2651         if (r < 0)
2652                 goto out_free;
2653
2654         r = -EFAULT;
2655         if (writeback && copy_to_user(user_msrs->entries, entries, size))
2656                 goto out_free;
2657
2658         r = n;
2659
2660 out_free:
2661         kfree(entries);
2662 out:
2663         return r;
2664 }
2665
2666 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2667 {
2668         int r;
2669
2670         switch (ext) {
2671         case KVM_CAP_IRQCHIP:
2672         case KVM_CAP_HLT:
2673         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2674         case KVM_CAP_SET_TSS_ADDR:
2675         case KVM_CAP_EXT_CPUID:
2676         case KVM_CAP_EXT_EMUL_CPUID:
2677         case KVM_CAP_CLOCKSOURCE:
2678         case KVM_CAP_PIT:
2679         case KVM_CAP_NOP_IO_DELAY:
2680         case KVM_CAP_MP_STATE:
2681         case KVM_CAP_SYNC_MMU:
2682         case KVM_CAP_USER_NMI:
2683         case KVM_CAP_REINJECT_CONTROL:
2684         case KVM_CAP_IRQ_INJECT_STATUS:
2685         case KVM_CAP_IRQFD:
2686         case KVM_CAP_IOEVENTFD:
2687         case KVM_CAP_IOEVENTFD_NO_LENGTH:
2688         case KVM_CAP_PIT2:
2689         case KVM_CAP_PIT_STATE2:
2690         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2691         case KVM_CAP_XEN_HVM:
2692         case KVM_CAP_ADJUST_CLOCK:
2693         case KVM_CAP_VCPU_EVENTS:
2694         case KVM_CAP_HYPERV:
2695         case KVM_CAP_HYPERV_VAPIC:
2696         case KVM_CAP_HYPERV_SPIN:
2697         case KVM_CAP_PCI_SEGMENT:
2698         case KVM_CAP_DEBUGREGS:
2699         case KVM_CAP_X86_ROBUST_SINGLESTEP:
2700         case KVM_CAP_XSAVE:
2701         case KVM_CAP_ASYNC_PF:
2702         case KVM_CAP_GET_TSC_KHZ:
2703         case KVM_CAP_KVMCLOCK_CTRL:
2704         case KVM_CAP_READONLY_MEM:
2705         case KVM_CAP_HYPERV_TIME:
2706         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2707 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2708         case KVM_CAP_ASSIGN_DEV_IRQ:
2709         case KVM_CAP_PCI_2_3:
2710 #endif
2711                 r = 1;
2712                 break;
2713         case KVM_CAP_COALESCED_MMIO:
2714                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2715                 break;
2716         case KVM_CAP_VAPIC:
2717                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2718                 break;
2719         case KVM_CAP_NR_VCPUS:
2720                 r = KVM_SOFT_MAX_VCPUS;
2721                 break;
2722         case KVM_CAP_MAX_VCPUS:
2723                 r = KVM_MAX_VCPUS;
2724                 break;
2725         case KVM_CAP_NR_MEMSLOTS:
2726                 r = KVM_USER_MEM_SLOTS;
2727                 break;
2728         case KVM_CAP_PV_MMU:    /* obsolete */
2729                 r = 0;
2730                 break;
2731 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2732         case KVM_CAP_IOMMU:
2733                 r = iommu_present(&pci_bus_type);
2734                 break;
2735 #endif
2736         case KVM_CAP_MCE:
2737                 r = KVM_MAX_MCE_BANKS;
2738                 break;
2739         case KVM_CAP_XCRS:
2740                 r = cpu_has_xsave;
2741                 break;
2742         case KVM_CAP_TSC_CONTROL:
2743                 r = kvm_has_tsc_control;
2744                 break;
2745         case KVM_CAP_TSC_DEADLINE_TIMER:
2746                 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2747                 break;
2748         default:
2749                 r = 0;
2750                 break;
2751         }
2752         return r;
2753
2754 }
2755
2756 long kvm_arch_dev_ioctl(struct file *filp,
2757                         unsigned int ioctl, unsigned long arg)
2758 {
2759         void __user *argp = (void __user *)arg;
2760         long r;
2761
2762         switch (ioctl) {
2763         case KVM_GET_MSR_INDEX_LIST: {
2764                 struct kvm_msr_list __user *user_msr_list = argp;
2765                 struct kvm_msr_list msr_list;
2766                 unsigned n;
2767
2768                 r = -EFAULT;
2769                 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2770                         goto out;
2771                 n = msr_list.nmsrs;
2772                 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2773                 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2774                         goto out;
2775                 r = -E2BIG;
2776                 if (n < msr_list.nmsrs)
2777                         goto out;
2778                 r = -EFAULT;
2779                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2780                                  num_msrs_to_save * sizeof(u32)))
2781                         goto out;
2782                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2783                                  &emulated_msrs,
2784                                  ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2785                         goto out;
2786                 r = 0;
2787                 break;
2788         }
2789         case KVM_GET_SUPPORTED_CPUID:
2790         case KVM_GET_EMULATED_CPUID: {
2791                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2792                 struct kvm_cpuid2 cpuid;
2793
2794                 r = -EFAULT;
2795                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2796                         goto out;
2797
2798                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2799                                             ioctl);
2800                 if (r)
2801                         goto out;
2802
2803                 r = -EFAULT;
2804                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2805                         goto out;
2806                 r = 0;
2807                 break;
2808         }
2809         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2810                 u64 mce_cap;
2811
2812                 mce_cap = KVM_MCE_CAP_SUPPORTED;
2813                 r = -EFAULT;
2814                 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2815                         goto out;
2816                 r = 0;
2817                 break;
2818         }
2819         default:
2820                 r = -EINVAL;
2821         }
2822 out:
2823         return r;
2824 }
2825
2826 static void wbinvd_ipi(void *garbage)
2827 {
2828         wbinvd();
2829 }
2830
2831 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2832 {
2833         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2834 }
2835
2836 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2837 {
2838         /* Address WBINVD may be executed by guest */
2839         if (need_emulate_wbinvd(vcpu)) {
2840                 if (kvm_x86_ops->has_wbinvd_exit())
2841                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2842                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2843                         smp_call_function_single(vcpu->cpu,
2844                                         wbinvd_ipi, NULL, 1);
2845         }
2846
2847         kvm_x86_ops->vcpu_load(vcpu, cpu);
2848
2849         /* Apply any externally detected TSC adjustments (due to suspend) */
2850         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2851                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2852                 vcpu->arch.tsc_offset_adjustment = 0;
2853                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2854         }
2855
2856         if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2857                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2858                                 native_read_tsc() - vcpu->arch.last_host_tsc;
2859                 if (tsc_delta < 0)
2860                         mark_tsc_unstable("KVM discovered backwards TSC");
2861                 if (check_tsc_unstable()) {
2862                         u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2863                                                 vcpu->arch.last_guest_tsc);
2864                         kvm_x86_ops->write_tsc_offset(vcpu, offset);
2865                         vcpu->arch.tsc_catchup = 1;
2866                 }
2867                 /*
2868                  * On a host with synchronized TSC, there is no need to update
2869                  * kvmclock on vcpu->cpu migration
2870                  */
2871                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2872                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2873                 if (vcpu->cpu != cpu)
2874                         kvm_migrate_timers(vcpu);
2875                 vcpu->cpu = cpu;
2876         }
2877
2878         accumulate_steal_time(vcpu);
2879         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2880 }
2881
2882 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2883 {
2884         kvm_x86_ops->vcpu_put(vcpu);
2885         kvm_put_guest_fpu(vcpu);
2886         vcpu->arch.last_host_tsc = native_read_tsc();
2887 }
2888
2889 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2890                                     struct kvm_lapic_state *s)
2891 {
2892         kvm_x86_ops->sync_pir_to_irr(vcpu);
2893         memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2894
2895         return 0;
2896 }
2897
2898 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2899                                     struct kvm_lapic_state *s)
2900 {
2901         kvm_apic_post_state_restore(vcpu, s);
2902         update_cr8_intercept(vcpu);
2903
2904         return 0;
2905 }
2906
2907 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2908                                     struct kvm_interrupt *irq)
2909 {
2910         if (irq->irq >= KVM_NR_INTERRUPTS)
2911                 return -EINVAL;
2912         if (irqchip_in_kernel(vcpu->kvm))
2913                 return -ENXIO;
2914
2915         kvm_queue_interrupt(vcpu, irq->irq, false);
2916         kvm_make_request(KVM_REQ_EVENT, vcpu);
2917
2918         return 0;
2919 }
2920
2921 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2922 {
2923         kvm_inject_nmi(vcpu);
2924
2925         return 0;
2926 }
2927
2928 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2929                                            struct kvm_tpr_access_ctl *tac)
2930 {
2931         if (tac->flags)
2932                 return -EINVAL;
2933         vcpu->arch.tpr_access_reporting = !!tac->enabled;
2934         return 0;
2935 }
2936
2937 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2938                                         u64 mcg_cap)
2939 {
2940         int r;
2941         unsigned bank_num = mcg_cap & 0xff, bank;
2942
2943         r = -EINVAL;
2944         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2945                 goto out;
2946         if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2947                 goto out;
2948         r = 0;
2949         vcpu->arch.mcg_cap = mcg_cap;
2950         /* Init IA32_MCG_CTL to all 1s */
2951         if (mcg_cap & MCG_CTL_P)
2952                 vcpu->arch.mcg_ctl = ~(u64)0;
2953         /* Init IA32_MCi_CTL to all 1s */
2954         for (bank = 0; bank < bank_num; bank++)
2955                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2956 out:
2957         return r;
2958 }
2959
2960 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2961                                       struct kvm_x86_mce *mce)
2962 {
2963         u64 mcg_cap = vcpu->arch.mcg_cap;
2964         unsigned bank_num = mcg_cap & 0xff;
2965         u64 *banks = vcpu->arch.mce_banks;
2966
2967         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2968                 return -EINVAL;
2969         /*
2970          * if IA32_MCG_CTL is not all 1s, the uncorrected error
2971          * reporting is disabled
2972          */
2973         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2974             vcpu->arch.mcg_ctl != ~(u64)0)
2975                 return 0;
2976         banks += 4 * mce->bank;
2977         /*
2978          * if IA32_MCi_CTL is not all 1s, the uncorrected error
2979          * reporting is disabled for the bank
2980          */
2981         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2982                 return 0;
2983         if (mce->status & MCI_STATUS_UC) {
2984                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2985                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2986                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2987                         return 0;
2988                 }
2989                 if (banks[1] & MCI_STATUS_VAL)
2990                         mce->status |= MCI_STATUS_OVER;
2991                 banks[2] = mce->addr;
2992                 banks[3] = mce->misc;
2993                 vcpu->arch.mcg_status = mce->mcg_status;
2994                 banks[1] = mce->status;
2995                 kvm_queue_exception(vcpu, MC_VECTOR);
2996         } else if (!(banks[1] & MCI_STATUS_VAL)
2997                    || !(banks[1] & MCI_STATUS_UC)) {
2998                 if (banks[1] & MCI_STATUS_VAL)
2999                         mce->status |= MCI_STATUS_OVER;
3000                 banks[2] = mce->addr;
3001                 banks[3] = mce->misc;
3002                 banks[1] = mce->status;
3003         } else
3004                 banks[1] |= MCI_STATUS_OVER;
3005         return 0;
3006 }
3007
3008 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3009                                                struct kvm_vcpu_events *events)
3010 {
3011         process_nmi(vcpu);
3012         events->exception.injected =
3013                 vcpu->arch.exception.pending &&
3014                 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3015         events->exception.nr = vcpu->arch.exception.nr;
3016         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3017         events->exception.pad = 0;
3018         events->exception.error_code = vcpu->arch.exception.error_code;
3019
3020         events->interrupt.injected =
3021                 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3022         events->interrupt.nr = vcpu->arch.interrupt.nr;
3023         events->interrupt.soft = 0;
3024         events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3025
3026         events->nmi.injected = vcpu->arch.nmi_injected;
3027         events->nmi.pending = vcpu->arch.nmi_pending != 0;
3028         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3029         events->nmi.pad = 0;
3030
3031         events->sipi_vector = 0; /* never valid when reporting to user space */
3032
3033         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3034                          | KVM_VCPUEVENT_VALID_SHADOW);
3035         memset(&events->reserved, 0, sizeof(events->reserved));
3036 }
3037
3038 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3039                                               struct kvm_vcpu_events *events)
3040 {
3041         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3042                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3043                               | KVM_VCPUEVENT_VALID_SHADOW))
3044                 return -EINVAL;
3045
3046         process_nmi(vcpu);
3047         vcpu->arch.exception.pending = events->exception.injected;
3048         vcpu->arch.exception.nr = events->exception.nr;
3049         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3050         vcpu->arch.exception.error_code = events->exception.error_code;
3051
3052         vcpu->arch.interrupt.pending = events->interrupt.injected;
3053         vcpu->arch.interrupt.nr = events->interrupt.nr;
3054         vcpu->arch.interrupt.soft = events->interrupt.soft;
3055         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3056                 kvm_x86_ops->set_interrupt_shadow(vcpu,
3057                                                   events->interrupt.shadow);
3058
3059         vcpu->arch.nmi_injected = events->nmi.injected;
3060         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3061                 vcpu->arch.nmi_pending = events->nmi.pending;
3062         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3063
3064         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3065             kvm_vcpu_has_lapic(vcpu))
3066                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3067
3068         kvm_make_request(KVM_REQ_EVENT, vcpu);
3069
3070         return 0;
3071 }
3072
3073 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3074                                              struct kvm_debugregs *dbgregs)
3075 {
3076         unsigned long val;
3077
3078         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3079         _kvm_get_dr(vcpu, 6, &val);
3080         dbgregs->dr6 = val;
3081         dbgregs->dr7 = vcpu->arch.dr7;
3082         dbgregs->flags = 0;
3083         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3084 }
3085
3086 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3087                                             struct kvm_debugregs *dbgregs)
3088 {
3089         if (dbgregs->flags)
3090                 return -EINVAL;
3091
3092         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3093         vcpu->arch.dr6 = dbgregs->dr6;
3094         kvm_update_dr6(vcpu);
3095         vcpu->arch.dr7 = dbgregs->dr7;
3096         kvm_update_dr7(vcpu);
3097
3098         return 0;
3099 }
3100
3101 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3102                                          struct kvm_xsave *guest_xsave)
3103 {
3104         if (cpu_has_xsave) {
3105                 memcpy(guest_xsave->region,
3106                         &vcpu->arch.guest_fpu.state->xsave,
3107                         vcpu->arch.guest_xstate_size);
3108                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3109                         vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3110         } else {
3111                 memcpy(guest_xsave->region,
3112                         &vcpu->arch.guest_fpu.state->fxsave,
3113                         sizeof(struct i387_fxsave_struct));
3114                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3115                         XSTATE_FPSSE;
3116         }
3117 }
3118
3119 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3120                                         struct kvm_xsave *guest_xsave)
3121 {
3122         u64 xstate_bv =
3123                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3124
3125         if (cpu_has_xsave) {
3126                 /*
3127                  * Here we allow setting states that are not present in
3128                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
3129                  * with old userspace.
3130                  */
3131                 if (xstate_bv & ~kvm_supported_xcr0())
3132                         return -EINVAL;
3133                 memcpy(&vcpu->arch.guest_fpu.state->xsave,
3134                         guest_xsave->region, vcpu->arch.guest_xstate_size);
3135         } else {
3136                 if (xstate_bv & ~XSTATE_FPSSE)
3137                         return -EINVAL;
3138                 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3139                         guest_xsave->region, sizeof(struct i387_fxsave_struct));
3140         }
3141         return 0;
3142 }
3143
3144 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3145                                         struct kvm_xcrs *guest_xcrs)
3146 {
3147         if (!cpu_has_xsave) {
3148                 guest_xcrs->nr_xcrs = 0;
3149                 return;
3150         }
3151
3152         guest_xcrs->nr_xcrs = 1;
3153         guest_xcrs->flags = 0;
3154         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3155         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3156 }
3157
3158 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3159                                        struct kvm_xcrs *guest_xcrs)
3160 {
3161         int i, r = 0;
3162
3163         if (!cpu_has_xsave)
3164                 return -EINVAL;
3165
3166         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3167                 return -EINVAL;
3168
3169         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3170                 /* Only support XCR0 currently */
3171                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3172                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3173                                 guest_xcrs->xcrs[i].value);
3174                         break;
3175                 }
3176         if (r)
3177                 r = -EINVAL;
3178         return r;
3179 }
3180
3181 /*
3182  * kvm_set_guest_paused() indicates to the guest kernel that it has been
3183  * stopped by the hypervisor.  This function will be called from the host only.
3184  * EINVAL is returned when the host attempts to set the flag for a guest that
3185  * does not support pv clocks.
3186  */
3187 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3188 {
3189         if (!vcpu->arch.pv_time_enabled)
3190                 return -EINVAL;
3191         vcpu->arch.pvclock_set_guest_stopped_request = true;
3192         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3193         return 0;
3194 }
3195
3196 long kvm_arch_vcpu_ioctl(struct file *filp,
3197                          unsigned int ioctl, unsigned long arg)
3198 {
3199         struct kvm_vcpu *vcpu = filp->private_data;
3200         void __user *argp = (void __user *)arg;
3201         int r;
3202         union {
3203                 struct kvm_lapic_state *lapic;
3204                 struct kvm_xsave *xsave;
3205                 struct kvm_xcrs *xcrs;
3206                 void *buffer;
3207         } u;
3208
3209         u.buffer = NULL;
3210         switch (ioctl) {
3211         case KVM_GET_LAPIC: {
3212                 r = -EINVAL;
3213                 if (!vcpu->arch.apic)
3214                         goto out;
3215                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3216
3217                 r = -ENOMEM;
3218                 if (!u.lapic)
3219                         goto out;
3220                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3221                 if (r)
3222                         goto out;
3223                 r = -EFAULT;
3224                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3225                         goto out;
3226                 r = 0;
3227                 break;
3228         }
3229         case KVM_SET_LAPIC: {
3230                 r = -EINVAL;
3231                 if (!vcpu->arch.apic)
3232                         goto out;
3233                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3234                 if (IS_ERR(u.lapic))
3235                         return PTR_ERR(u.lapic);
3236
3237                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3238                 break;
3239         }
3240         case KVM_INTERRUPT: {
3241                 struct kvm_interrupt irq;
3242
3243                 r = -EFAULT;
3244                 if (copy_from_user(&irq, argp, sizeof irq))
3245                         goto out;
3246                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3247                 break;
3248         }
3249         case KVM_NMI: {
3250                 r = kvm_vcpu_ioctl_nmi(vcpu);
3251                 break;
3252         }
3253         case KVM_SET_CPUID: {
3254                 struct kvm_cpuid __user *cpuid_arg = argp;
3255                 struct kvm_cpuid cpuid;
3256
3257                 r = -EFAULT;
3258                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3259                         goto out;
3260                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3261                 break;
3262         }
3263         case KVM_SET_CPUID2: {
3264                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3265                 struct kvm_cpuid2 cpuid;
3266
3267                 r = -EFAULT;
3268                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3269                         goto out;
3270                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3271                                               cpuid_arg->entries);
3272                 break;
3273         }
3274         case KVM_GET_CPUID2: {
3275                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3276                 struct kvm_cpuid2 cpuid;
3277
3278                 r = -EFAULT;
3279                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3280                         goto out;
3281                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3282                                               cpuid_arg->entries);
3283                 if (r)
3284                         goto out;
3285                 r = -EFAULT;
3286                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3287                         goto out;
3288                 r = 0;
3289                 break;
3290         }
3291         case KVM_GET_MSRS:
3292                 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3293                 break;
3294         case KVM_SET_MSRS:
3295                 r = msr_io(vcpu, argp, do_set_msr, 0);
3296                 break;
3297         case KVM_TPR_ACCESS_REPORTING: {
3298                 struct kvm_tpr_access_ctl tac;
3299
3300                 r = -EFAULT;
3301                 if (copy_from_user(&tac, argp, sizeof tac))
3302                         goto out;
3303                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3304                 if (r)
3305                         goto out;
3306                 r = -EFAULT;
3307                 if (copy_to_user(argp, &tac, sizeof tac))
3308                         goto out;
3309                 r = 0;
3310                 break;
3311         };
3312         case KVM_SET_VAPIC_ADDR: {
3313                 struct kvm_vapic_addr va;
3314
3315                 r = -EINVAL;
3316                 if (!irqchip_in_kernel(vcpu->kvm))
3317                         goto out;
3318                 r = -EFAULT;
3319                 if (copy_from_user(&va, argp, sizeof va))
3320                         goto out;
3321                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3322                 break;
3323         }
3324         case KVM_X86_SETUP_MCE: {
3325                 u64 mcg_cap;
3326
3327                 r = -EFAULT;
3328                 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3329                         goto out;
3330                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3331                 break;
3332         }
3333         case KVM_X86_SET_MCE: {
3334                 struct kvm_x86_mce mce;
3335
3336                 r = -EFAULT;
3337                 if (copy_from_user(&mce, argp, sizeof mce))
3338                         goto out;
3339                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3340                 break;
3341         }
3342         case KVM_GET_VCPU_EVENTS: {
3343                 struct kvm_vcpu_events events;
3344
3345                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3346
3347                 r = -EFAULT;
3348                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3349                         break;
3350                 r = 0;
3351                 break;
3352         }
3353         case KVM_SET_VCPU_EVENTS: {
3354                 struct kvm_vcpu_events events;
3355
3356                 r = -EFAULT;
3357                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3358                         break;
3359
3360                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3361                 break;
3362         }
3363         case KVM_GET_DEBUGREGS: {
3364                 struct kvm_debugregs dbgregs;
3365
3366                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3367
3368                 r = -EFAULT;
3369                 if (copy_to_user(argp, &dbgregs,
3370                                  sizeof(struct kvm_debugregs)))
3371                         break;
3372                 r = 0;
3373                 break;
3374         }
3375         case KVM_SET_DEBUGREGS: {
3376                 struct kvm_debugregs dbgregs;
3377
3378                 r = -EFAULT;
3379                 if (copy_from_user(&dbgregs, argp,
3380                                    sizeof(struct kvm_debugregs)))
3381                         break;
3382
3383                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3384                 break;
3385         }
3386         case KVM_GET_XSAVE: {
3387                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3388                 r = -ENOMEM;
3389                 if (!u.xsave)
3390                         break;
3391
3392                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3393
3394                 r = -EFAULT;
3395                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3396                         break;
3397                 r = 0;
3398                 break;
3399         }
3400         case KVM_SET_XSAVE: {
3401                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3402                 if (IS_ERR(u.xsave))
3403                         return PTR_ERR(u.xsave);
3404
3405                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3406                 break;
3407         }
3408         case KVM_GET_XCRS: {
3409                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3410                 r = -ENOMEM;
3411                 if (!u.xcrs)
3412                         break;
3413
3414                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3415
3416                 r = -EFAULT;
3417                 if (copy_to_user(argp, u.xcrs,
3418                                  sizeof(struct kvm_xcrs)))
3419                         break;
3420                 r = 0;
3421                 break;
3422         }
3423         case KVM_SET_XCRS: {
3424                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3425                 if (IS_ERR(u.xcrs))
3426                         return PTR_ERR(u.xcrs);
3427
3428                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3429                 break;
3430         }
3431         case KVM_SET_TSC_KHZ: {
3432                 u32 user_tsc_khz;
3433
3434                 r = -EINVAL;
3435                 user_tsc_khz = (u32)arg;
3436
3437                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3438                         goto out;
3439
3440                 if (user_tsc_khz == 0)
3441                         user_tsc_khz = tsc_khz;
3442
3443                 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3444
3445                 r = 0;
3446                 goto out;
3447         }
3448         case KVM_GET_TSC_KHZ: {
3449                 r = vcpu->arch.virtual_tsc_khz;
3450                 goto out;
3451         }
3452         case KVM_KVMCLOCK_CTRL: {
3453                 r = kvm_set_guest_paused(vcpu);
3454                 goto out;
3455         }
3456         default:
3457                 r = -EINVAL;
3458         }
3459 out:
3460         kfree(u.buffer);
3461         return r;
3462 }
3463
3464 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3465 {
3466         return VM_FAULT_SIGBUS;
3467 }
3468
3469 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3470 {
3471         int ret;
3472
3473         if (addr > (unsigned int)(-3 * PAGE_SIZE))
3474                 return -EINVAL;
3475         ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3476         return ret;
3477 }
3478
3479 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3480                                               u64 ident_addr)
3481 {
3482         kvm->arch.ept_identity_map_addr = ident_addr;
3483         return 0;
3484 }
3485
3486 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3487                                           u32 kvm_nr_mmu_pages)
3488 {
3489         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3490                 return -EINVAL;
3491
3492         mutex_lock(&kvm->slots_lock);
3493
3494         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3495         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3496
3497         mutex_unlock(&kvm->slots_lock);
3498         return 0;
3499 }
3500
3501 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3502 {
3503         return kvm->arch.n_max_mmu_pages;
3504 }
3505
3506 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3507 {
3508         int r;
3509
3510         r = 0;
3511         switch (chip->chip_id) {
3512         case KVM_IRQCHIP_PIC_MASTER:
3513                 memcpy(&chip->chip.pic,
3514                         &pic_irqchip(kvm)->pics[0],
3515                         sizeof(struct kvm_pic_state));
3516                 break;
3517         case KVM_IRQCHIP_PIC_SLAVE:
3518                 memcpy(&chip->chip.pic,
3519                         &pic_irqchip(kvm)->pics[1],
3520                         sizeof(struct kvm_pic_state));
3521                 break;
3522         case KVM_IRQCHIP_IOAPIC:
3523                 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3524                 break;
3525         default:
3526                 r = -EINVAL;
3527                 break;
3528         }
3529         return r;
3530 }
3531
3532 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3533 {
3534         int r;
3535
3536         r = 0;
3537         switch (chip->chip_id) {
3538         case KVM_IRQCHIP_PIC_MASTER:
3539                 spin_lock(&pic_irqchip(kvm)->lock);
3540                 memcpy(&pic_irqchip(kvm)->pics[0],
3541                         &chip->chip.pic,
3542                         sizeof(struct kvm_pic_state));
3543                 spin_unlock(&pic_irqchip(kvm)->lock);
3544                 break;
3545         case KVM_IRQCHIP_PIC_SLAVE:
3546                 spin_lock(&pic_irqchip(kvm)->lock);
3547                 memcpy(&pic_irqchip(kvm)->pics[1],
3548                         &chip->chip.pic,
3549                         sizeof(struct kvm_pic_state));
3550                 spin_unlock(&pic_irqchip(kvm)->lock);
3551                 break;
3552         case KVM_IRQCHIP_IOAPIC:
3553                 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3554                 break;
3555         default:
3556                 r = -EINVAL;
3557                 break;
3558         }
3559         kvm_pic_update_irq(pic_irqchip(kvm));
3560         return r;
3561 }
3562
3563 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3564 {
3565         int r = 0;
3566
3567         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3568         memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3569         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3570         return r;
3571 }
3572
3573 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3574 {
3575         int r = 0;
3576
3577         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3578         memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3579         kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3580         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3581         return r;
3582 }
3583
3584 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3585 {
3586         int r = 0;
3587
3588         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3589         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3590                 sizeof(ps->channels));
3591         ps->flags = kvm->arch.vpit->pit_state.flags;
3592         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3593         memset(&ps->reserved, 0, sizeof(ps->reserved));
3594         return r;
3595 }
3596
3597 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3598 {
3599         int r = 0, start = 0;
3600         u32 prev_legacy, cur_legacy;
3601         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3602         prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3603         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3604         if (!prev_legacy && cur_legacy)
3605                 start = 1;
3606         memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3607                sizeof(kvm->arch.vpit->pit_state.channels));
3608         kvm->arch.vpit->pit_state.flags = ps->flags;
3609         kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3610         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3611         return r;
3612 }
3613
3614 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3615                                  struct kvm_reinject_control *control)
3616 {
3617         if (!kvm->arch.vpit)
3618                 return -ENXIO;
3619         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3620         kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3621         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3622         return 0;
3623 }
3624
3625 /**
3626  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3627  * @kvm: kvm instance
3628  * @log: slot id and address to which we copy the log
3629  *
3630  * We need to keep it in mind that VCPU threads can write to the bitmap
3631  * concurrently.  So, to avoid losing data, we keep the following order for
3632  * each bit:
3633  *
3634  *   1. Take a snapshot of the bit and clear it if needed.
3635  *   2. Write protect the corresponding page.
3636  *   3. Flush TLB's if needed.
3637  *   4. Copy the snapshot to the userspace.
3638  *
3639  * Between 2 and 3, the guest may write to the page using the remaining TLB
3640  * entry.  This is not a problem because the page will be reported dirty at
3641  * step 4 using the snapshot taken before and step 3 ensures that successive
3642  * writes will be logged for the next call.
3643  */
3644 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3645 {
3646         int r;
3647         struct kvm_memory_slot *memslot;
3648         unsigned long n, i;
3649         unsigned long *dirty_bitmap;
3650         unsigned long *dirty_bitmap_buffer;
3651         bool is_dirty = false;
3652
3653         mutex_lock(&kvm->slots_lock);
3654
3655         r = -EINVAL;
3656         if (log->slot >= KVM_USER_MEM_SLOTS)
3657                 goto out;
3658
3659         memslot = id_to_memslot(kvm->memslots, log->slot);
3660
3661         dirty_bitmap = memslot->dirty_bitmap;
3662         r = -ENOENT;
3663         if (!dirty_bitmap)
3664                 goto out;
3665
3666         n = kvm_dirty_bitmap_bytes(memslot);
3667
3668         dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3669         memset(dirty_bitmap_buffer, 0, n);
3670
3671         spin_lock(&kvm->mmu_lock);
3672
3673         for (i = 0; i < n / sizeof(long); i++) {
3674                 unsigned long mask;
3675                 gfn_t offset;
3676
3677                 if (!dirty_bitmap[i])
3678                         continue;
3679
3680                 is_dirty = true;
3681
3682                 mask = xchg(&dirty_bitmap[i], 0);
3683                 dirty_bitmap_buffer[i] = mask;
3684
3685                 offset = i * BITS_PER_LONG;
3686                 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3687         }
3688
3689         spin_unlock(&kvm->mmu_lock);
3690
3691         /* See the comments in kvm_mmu_slot_remove_write_access(). */
3692         lockdep_assert_held(&kvm->slots_lock);
3693
3694         /*
3695          * All the TLBs can be flushed out of mmu lock, see the comments in
3696          * kvm_mmu_slot_remove_write_access().
3697          */
3698         if (is_dirty)
3699                 kvm_flush_remote_tlbs(kvm);
3700
3701         r = -EFAULT;
3702         if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3703                 goto out;
3704
3705         r = 0;
3706 out:
3707         mutex_unlock(&kvm->slots_lock);
3708         return r;
3709 }
3710
3711 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3712                         bool line_status)
3713 {
3714         if (!irqchip_in_kernel(kvm))
3715                 return -ENXIO;
3716
3717         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3718                                         irq_event->irq, irq_event->level,
3719                                         line_status);
3720         return 0;
3721 }
3722
3723 long kvm_arch_vm_ioctl(struct file *filp,
3724                        unsigned int ioctl, unsigned long arg)
3725 {
3726         struct kvm *kvm = filp->private_data;
3727         void __user *argp = (void __user *)arg;
3728         int r = -ENOTTY;
3729         /*
3730          * This union makes it completely explicit to gcc-3.x
3731          * that these two variables' stack usage should be
3732          * combined, not added together.
3733          */
3734         union {
3735                 struct kvm_pit_state ps;
3736                 struct kvm_pit_state2 ps2;
3737                 struct kvm_pit_config pit_config;
3738         } u;
3739
3740         switch (ioctl) {
3741         case KVM_SET_TSS_ADDR:
3742                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3743                 break;
3744         case KVM_SET_IDENTITY_MAP_ADDR: {
3745                 u64 ident_addr;
3746
3747                 r = -EFAULT;
3748                 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3749                         goto out;
3750                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3751                 break;
3752         }
3753         case KVM_SET_NR_MMU_PAGES:
3754                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3755                 break;
3756         case KVM_GET_NR_MMU_PAGES:
3757                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3758                 break;
3759         case KVM_CREATE_IRQCHIP: {
3760                 struct kvm_pic *vpic;
3761
3762                 mutex_lock(&kvm->lock);
3763                 r = -EEXIST;
3764                 if (kvm->arch.vpic)
3765                         goto create_irqchip_unlock;
3766                 r = -EINVAL;
3767                 if (atomic_read(&kvm->online_vcpus))
3768                         goto create_irqchip_unlock;
3769                 r = -ENOMEM;
3770                 vpic = kvm_create_pic(kvm);
3771                 if (vpic) {
3772                         r = kvm_ioapic_init(kvm);
3773                         if (r) {
3774                                 mutex_lock(&kvm->slots_lock);
3775                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3776                                                           &vpic->dev_master);
3777                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3778                                                           &vpic->dev_slave);
3779                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3780                                                           &vpic->dev_eclr);
3781                                 mutex_unlock(&kvm->slots_lock);
3782                                 kfree(vpic);
3783                                 goto create_irqchip_unlock;
3784                         }
3785                 } else
3786                         goto create_irqchip_unlock;
3787                 smp_wmb();
3788                 kvm->arch.vpic = vpic;
3789                 smp_wmb();
3790                 r = kvm_setup_default_irq_routing(kvm);
3791                 if (r) {
3792                         mutex_lock(&kvm->slots_lock);
3793                         mutex_lock(&kvm->irq_lock);
3794                         kvm_ioapic_destroy(kvm);
3795                         kvm_destroy_pic(kvm);
3796                         mutex_unlock(&kvm->irq_lock);
3797                         mutex_unlock(&kvm->slots_lock);
3798                 }
3799         create_irqchip_unlock:
3800                 mutex_unlock(&kvm->lock);
3801                 break;
3802         }
3803         case KVM_CREATE_PIT:
3804                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3805                 goto create_pit;
3806         case KVM_CREATE_PIT2:
3807                 r = -EFAULT;
3808                 if (copy_from_user(&u.pit_config, argp,
3809                                    sizeof(struct kvm_pit_config)))
3810                         goto out;
3811         create_pit:
3812                 mutex_lock(&kvm->slots_lock);
3813                 r = -EEXIST;
3814                 if (kvm->arch.vpit)
3815                         goto create_pit_unlock;
3816                 r = -ENOMEM;
3817                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3818                 if (kvm->arch.vpit)
3819                         r = 0;
3820         create_pit_unlock:
3821                 mutex_unlock(&kvm->slots_lock);
3822                 break;
3823         case KVM_GET_IRQCHIP: {
3824                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3825                 struct kvm_irqchip *chip;
3826
3827                 chip = memdup_user(argp, sizeof(*chip));
3828                 if (IS_ERR(chip)) {
3829                         r = PTR_ERR(chip);
3830                         goto out;
3831                 }
3832
3833                 r = -ENXIO;
3834                 if (!irqchip_in_kernel(kvm))
3835                         goto get_irqchip_out;
3836                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3837                 if (r)
3838                         goto get_irqchip_out;
3839                 r = -EFAULT;
3840                 if (copy_to_user(argp, chip, sizeof *chip))
3841                         goto get_irqchip_out;
3842                 r = 0;
3843         get_irqchip_out:
3844                 kfree(chip);
3845                 break;
3846         }
3847         case KVM_SET_IRQCHIP: {
3848                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3849                 struct kvm_irqchip *chip;
3850
3851                 chip = memdup_user(argp, sizeof(*chip));
3852                 if (IS_ERR(chip)) {
3853                         r = PTR_ERR(chip);
3854                         goto out;
3855                 }
3856
3857                 r = -ENXIO;
3858                 if (!irqchip_in_kernel(kvm))
3859                         goto set_irqchip_out;
3860                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3861                 if (r)
3862                         goto set_irqchip_out;
3863                 r = 0;
3864         set_irqchip_out:
3865                 kfree(chip);
3866                 break;
3867         }
3868         case KVM_GET_PIT: {
3869                 r = -EFAULT;
3870                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3871                         goto out;
3872                 r = -ENXIO;
3873                 if (!kvm->arch.vpit)
3874                         goto out;
3875                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3876                 if (r)
3877                         goto out;
3878                 r = -EFAULT;
3879                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3880                         goto out;
3881                 r = 0;
3882                 break;
3883         }
3884         case KVM_SET_PIT: {
3885                 r = -EFAULT;
3886                 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3887                         goto out;
3888                 r = -ENXIO;
3889                 if (!kvm->arch.vpit)
3890                         goto out;
3891                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3892                 break;
3893         }
3894         case KVM_GET_PIT2: {
3895                 r = -ENXIO;
3896                 if (!kvm->arch.vpit)
3897                         goto out;
3898                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3899                 if (r)
3900                         goto out;
3901                 r = -EFAULT;
3902                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3903                         goto out;
3904                 r = 0;
3905                 break;
3906         }
3907         case KVM_SET_PIT2: {
3908                 r = -EFAULT;
3909                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3910                         goto out;
3911                 r = -ENXIO;
3912                 if (!kvm->arch.vpit)
3913                         goto out;
3914                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3915                 break;
3916         }
3917         case KVM_REINJECT_CONTROL: {
3918                 struct kvm_reinject_control control;
3919                 r =  -EFAULT;
3920                 if (copy_from_user(&control, argp, sizeof(control)))
3921                         goto out;
3922                 r = kvm_vm_ioctl_reinject(kvm, &control);
3923                 break;
3924         }
3925         case KVM_XEN_HVM_CONFIG: {
3926                 r = -EFAULT;
3927                 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3928                                    sizeof(struct kvm_xen_hvm_config)))
3929                         goto out;
3930                 r = -EINVAL;
3931                 if (kvm->arch.xen_hvm_config.flags)
3932                         goto out;
3933                 r = 0;
3934                 break;
3935         }
3936         case KVM_SET_CLOCK: {
3937                 struct kvm_clock_data user_ns;
3938                 u64 now_ns;
3939                 s64 delta;
3940
3941                 r = -EFAULT;
3942                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3943                         goto out;
3944
3945                 r = -EINVAL;
3946                 if (user_ns.flags)
3947                         goto out;
3948
3949                 r = 0;
3950                 local_irq_disable();
3951                 now_ns = get_kernel_ns();
3952                 delta = user_ns.clock - now_ns;
3953                 local_irq_enable();
3954                 kvm->arch.kvmclock_offset = delta;
3955                 kvm_gen_update_masterclock(kvm);
3956                 break;
3957         }
3958         case KVM_GET_CLOCK: {
3959                 struct kvm_clock_data user_ns;
3960                 u64 now_ns;
3961
3962                 local_irq_disable();
3963                 now_ns = get_kernel_ns();
3964                 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3965                 local_irq_enable();
3966                 user_ns.flags = 0;
3967                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3968
3969                 r = -EFAULT;
3970                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3971                         goto out;
3972                 r = 0;
3973                 break;
3974         }
3975
3976         default:
3977                 ;
3978         }
3979 out:
3980         return r;
3981 }
3982
3983 static void kvm_init_msr_list(void)
3984 {
3985         u32 dummy[2];
3986         unsigned i, j;
3987
3988         /* skip the first msrs in the list. KVM-specific */
3989         for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3990                 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3991                         continue;
3992
3993                 /*
3994                  * Even MSRs that are valid in the host may not be exposed
3995                  * to the guests in some cases.  We could work around this
3996                  * in VMX with the generic MSR save/load machinery, but it
3997                  * is not really worthwhile since it will really only
3998                  * happen with nested virtualization.
3999                  */
4000                 switch (msrs_to_save[i]) {
4001                 case MSR_IA32_BNDCFGS:
4002                         if (!kvm_x86_ops->mpx_supported())
4003                                 continue;
4004                         break;
4005                 default:
4006                         break;
4007                 }
4008
4009                 if (j < i)
4010                         msrs_to_save[j] = msrs_to_save[i];
4011                 j++;
4012         }
4013         num_msrs_to_save = j;
4014 }
4015
4016 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4017                            const void *v)
4018 {
4019         int handled = 0;
4020         int n;
4021
4022         do {
4023                 n = min(len, 8);
4024                 if (!(vcpu->arch.apic &&
4025                       !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
4026                     && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4027                         break;
4028                 handled += n;
4029                 addr += n;
4030                 len -= n;
4031                 v += n;
4032         } while (len);
4033
4034         return handled;
4035 }
4036
4037 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4038 {
4039         int handled = 0;
4040         int n;
4041
4042         do {
4043                 n = min(len, 8);
4044                 if (!(vcpu->arch.apic &&
4045                       !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4046                     && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4047                         break;
4048                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4049                 handled += n;
4050                 addr += n;
4051                 len -= n;
4052                 v += n;
4053         } while (len);
4054
4055         return handled;
4056 }
4057
4058 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4059                         struct kvm_segment *var, int seg)
4060 {
4061         kvm_x86_ops->set_segment(vcpu, var, seg);
4062 }
4063
4064 void kvm_get_segment(struct kvm_vcpu *vcpu,
4065                      struct kvm_segment *var, int seg)
4066 {
4067         kvm_x86_ops->get_segment(vcpu, var, seg);
4068 }
4069
4070 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4071                            struct x86_exception *exception)
4072 {
4073         gpa_t t_gpa;
4074
4075         BUG_ON(!mmu_is_nested(vcpu));
4076
4077         /* NPT walks are always user-walks */
4078         access |= PFERR_USER_MASK;
4079         t_gpa  = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4080
4081         return t_gpa;
4082 }
4083
4084 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4085                               struct x86_exception *exception)
4086 {
4087         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4088         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4089 }
4090
4091  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4092                                 struct x86_exception *exception)
4093 {
4094         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4095         access |= PFERR_FETCH_MASK;
4096         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4097 }
4098
4099 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4100                                struct x86_exception *exception)
4101 {
4102         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4103         access |= PFERR_WRITE_MASK;
4104         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4105 }
4106
4107 /* uses this to access any guest's mapped memory without checking CPL */
4108 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4109                                 struct x86_exception *exception)
4110 {
4111         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4112 }
4113
4114 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4115                                       struct kvm_vcpu *vcpu, u32 access,
4116                                       struct x86_exception *exception)
4117 {
4118         void *data = val;
4119         int r = X86EMUL_CONTINUE;
4120
4121         while (bytes) {
4122                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4123                                                             exception);
4124                 unsigned offset = addr & (PAGE_SIZE-1);
4125                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4126                 int ret;
4127
4128                 if (gpa == UNMAPPED_GVA)
4129                         return X86EMUL_PROPAGATE_FAULT;
4130                 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4131                                           offset, toread);
4132                 if (ret < 0) {
4133                         r = X86EMUL_IO_NEEDED;
4134                         goto out;
4135                 }
4136
4137                 bytes -= toread;
4138                 data += toread;
4139                 addr += toread;
4140         }
4141 out:
4142         return r;
4143 }
4144
4145 /* used for instruction fetching */
4146 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4147                                 gva_t addr, void *val, unsigned int bytes,
4148                                 struct x86_exception *exception)
4149 {
4150         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4151         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4152         unsigned offset;
4153         int ret;
4154
4155         /* Inline kvm_read_guest_virt_helper for speed.  */
4156         gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4157                                                     exception);
4158         if (unlikely(gpa == UNMAPPED_GVA))
4159                 return X86EMUL_PROPAGATE_FAULT;
4160
4161         offset = addr & (PAGE_SIZE-1);
4162         if (WARN_ON(offset + bytes > PAGE_SIZE))
4163                 bytes = (unsigned)PAGE_SIZE - offset;
4164         ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4165                                   offset, bytes);
4166         if (unlikely(ret < 0))
4167                 return X86EMUL_IO_NEEDED;
4168
4169         return X86EMUL_CONTINUE;
4170 }
4171
4172 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4173                                gva_t addr, void *val, unsigned int bytes,
4174                                struct x86_exception *exception)
4175 {
4176         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4177         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4178
4179         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4180                                           exception);
4181 }
4182 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4183
4184 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4185                                       gva_t addr, void *val, unsigned int bytes,
4186                                       struct x86_exception *exception)
4187 {
4188         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4189         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4190 }
4191
4192 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4193                                        gva_t addr, void *val,
4194                                        unsigned int bytes,
4195                                        struct x86_exception *exception)
4196 {
4197         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4198         void *data = val;
4199         int r = X86EMUL_CONTINUE;
4200
4201         while (bytes) {
4202                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4203                                                              PFERR_WRITE_MASK,
4204                                                              exception);
4205                 unsigned offset = addr & (PAGE_SIZE-1);
4206                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4207                 int ret;
4208
4209                 if (gpa == UNMAPPED_GVA)
4210                         return X86EMUL_PROPAGATE_FAULT;
4211                 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4212                 if (ret < 0) {
4213                         r = X86EMUL_IO_NEEDED;
4214                         goto out;
4215                 }
4216
4217                 bytes -= towrite;
4218                 data += towrite;
4219                 addr += towrite;
4220         }
4221 out:
4222         return r;
4223 }
4224 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4225
4226 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4227                                 gpa_t *gpa, struct x86_exception *exception,
4228                                 bool write)
4229 {
4230         u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4231                 | (write ? PFERR_WRITE_MASK : 0);
4232
4233         if (vcpu_match_mmio_gva(vcpu, gva)
4234             && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4235                                  vcpu->arch.access, access)) {
4236                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4237                                         (gva & (PAGE_SIZE - 1));
4238                 trace_vcpu_match_mmio(gva, *gpa, write, false);
4239                 return 1;
4240         }
4241
4242         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4243
4244         if (*gpa == UNMAPPED_GVA)
4245                 return -1;
4246
4247         /* For APIC access vmexit */
4248         if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4249                 return 1;
4250
4251         if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4252                 trace_vcpu_match_mmio(gva, *gpa, write, true);
4253                 return 1;
4254         }
4255
4256         return 0;
4257 }
4258
4259 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4260                         const void *val, int bytes)
4261 {
4262         int ret;
4263
4264         ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4265         if (ret < 0)
4266                 return 0;
4267         kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4268         return 1;
4269 }
4270
4271 struct read_write_emulator_ops {
4272         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4273                                   int bytes);
4274         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4275                                   void *val, int bytes);
4276         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4277                                int bytes, void *val);
4278         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4279                                     void *val, int bytes);
4280         bool write;
4281 };
4282
4283 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4284 {
4285         if (vcpu->mmio_read_completed) {
4286                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4287                                vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4288                 vcpu->mmio_read_completed = 0;
4289                 return 1;
4290         }
4291
4292         return 0;
4293 }
4294
4295 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4296                         void *val, int bytes)
4297 {
4298         return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4299 }
4300
4301 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4302                          void *val, int bytes)
4303 {
4304         return emulator_write_phys(vcpu, gpa, val, bytes);
4305 }
4306
4307 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4308 {
4309         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4310         return vcpu_mmio_write(vcpu, gpa, bytes, val);
4311 }
4312
4313 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4314                           void *val, int bytes)
4315 {
4316         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4317         return X86EMUL_IO_NEEDED;
4318 }
4319
4320 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4321                            void *val, int bytes)
4322 {
4323         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4324
4325         memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4326         return X86EMUL_CONTINUE;
4327 }
4328
4329 static const struct read_write_emulator_ops read_emultor = {
4330         .read_write_prepare = read_prepare,
4331         .read_write_emulate = read_emulate,
4332         .read_write_mmio = vcpu_mmio_read,
4333         .read_write_exit_mmio = read_exit_mmio,
4334 };
4335
4336 static const struct read_write_emulator_ops write_emultor = {
4337         .read_write_emulate = write_emulate,
4338         .read_write_mmio = write_mmio,
4339         .read_write_exit_mmio = write_exit_mmio,
4340         .write = true,
4341 };
4342
4343 static int emulator_read_write_onepage(unsigned long addr, void *val,
4344                                        unsigned int bytes,
4345                                        struct x86_exception *exception,
4346                                        struct kvm_vcpu *vcpu,
4347                                        const struct read_write_emulator_ops *ops)
4348 {
4349         gpa_t gpa;
4350         int handled, ret;
4351         bool write = ops->write;
4352         struct kvm_mmio_fragment *frag;
4353
4354         ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4355
4356         if (ret < 0)
4357                 return X86EMUL_PROPAGATE_FAULT;
4358
4359         /* For APIC access vmexit */
4360         if (ret)
4361                 goto mmio;
4362
4363         if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4364                 return X86EMUL_CONTINUE;
4365
4366 mmio:
4367         /*
4368          * Is this MMIO handled locally?
4369          */
4370         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4371         if (handled == bytes)
4372                 return X86EMUL_CONTINUE;
4373
4374         gpa += handled;
4375         bytes -= handled;
4376         val += handled;
4377
4378         WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4379         frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4380         frag->gpa = gpa;
4381         frag->data = val;
4382         frag->len = bytes;
4383         return X86EMUL_CONTINUE;
4384 }
4385
4386 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4387                         void *val, unsigned int bytes,
4388                         struct x86_exception *exception,
4389                         const struct read_write_emulator_ops *ops)
4390 {
4391         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4392         gpa_t gpa;
4393         int rc;
4394
4395         if (ops->read_write_prepare &&
4396                   ops->read_write_prepare(vcpu, val, bytes))
4397                 return X86EMUL_CONTINUE;
4398
4399         vcpu->mmio_nr_fragments = 0;
4400
4401         /* Crossing a page boundary? */
4402         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4403                 int now;
4404
4405                 now = -addr & ~PAGE_MASK;
4406                 rc = emulator_read_write_onepage(addr, val, now, exception,
4407                                                  vcpu, ops);
4408
4409                 if (rc != X86EMUL_CONTINUE)
4410                         return rc;
4411                 addr += now;
4412                 val += now;
4413                 bytes -= now;
4414         }
4415
4416         rc = emulator_read_write_onepage(addr, val, bytes, exception,
4417                                          vcpu, ops);
4418         if (rc != X86EMUL_CONTINUE)
4419                 return rc;
4420
4421         if (!vcpu->mmio_nr_fragments)
4422                 return rc;
4423
4424         gpa = vcpu->mmio_fragments[0].gpa;
4425
4426         vcpu->mmio_needed = 1;
4427         vcpu->mmio_cur_fragment = 0;
4428
4429         vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4430         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4431         vcpu->run->exit_reason = KVM_EXIT_MMIO;
4432         vcpu->run->mmio.phys_addr = gpa;
4433
4434         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4435 }
4436
4437 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4438                                   unsigned long addr,
4439                                   void *val,
4440                                   unsigned int bytes,
4441                                   struct x86_exception *exception)
4442 {
4443         return emulator_read_write(ctxt, addr, val, bytes,
4444                                    exception, &read_emultor);
4445 }
4446
4447 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4448                             unsigned long addr,
4449                             const void *val,
4450                             unsigned int bytes,
4451                             struct x86_exception *exception)
4452 {
4453         return emulator_read_write(ctxt, addr, (void *)val, bytes,
4454                                    exception, &write_emultor);
4455 }
4456
4457 #define CMPXCHG_TYPE(t, ptr, old, new) \
4458         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4459
4460 #ifdef CONFIG_X86_64
4461 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4462 #else
4463 #  define CMPXCHG64(ptr, old, new) \
4464         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4465 #endif
4466
4467 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4468                                      unsigned long addr,
4469                                      const void *old,
4470                                      const void *new,
4471                                      unsigned int bytes,
4472                                      struct x86_exception *exception)
4473 {
4474         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4475         gpa_t gpa;
4476         struct page *page;
4477         char *kaddr;
4478         bool exchanged;
4479
4480         /* guests cmpxchg8b have to be emulated atomically */
4481         if (bytes > 8 || (bytes & (bytes - 1)))
4482                 goto emul_write;
4483
4484         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4485
4486         if (gpa == UNMAPPED_GVA ||
4487             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4488                 goto emul_write;
4489
4490         if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4491                 goto emul_write;
4492
4493         page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4494         if (is_error_page(page))
4495                 goto emul_write;
4496
4497         kaddr = kmap_atomic(page);
4498         kaddr += offset_in_page(gpa);
4499         switch (bytes) {
4500         case 1:
4501                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4502                 break;
4503         case 2:
4504                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4505                 break;
4506         case 4:
4507                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4508                 break;
4509         case 8:
4510                 exchanged = CMPXCHG64(kaddr, old, new);
4511                 break;
4512         default:
4513                 BUG();
4514         }
4515         kunmap_atomic(kaddr);
4516         kvm_release_page_dirty(page);
4517
4518         if (!exchanged)
4519                 return X86EMUL_CMPXCHG_FAILED;
4520
4521         mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
4522         kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4523
4524         return X86EMUL_CONTINUE;
4525
4526 emul_write:
4527         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4528
4529         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4530 }
4531
4532 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4533 {
4534         /* TODO: String I/O for in kernel device */
4535         int r;
4536
4537         if (vcpu->arch.pio.in)
4538                 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4539                                     vcpu->arch.pio.size, pd);
4540         else
4541                 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4542                                      vcpu->arch.pio.port, vcpu->arch.pio.size,
4543                                      pd);
4544         return r;
4545 }
4546
4547 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4548                                unsigned short port, void *val,
4549                                unsigned int count, bool in)
4550 {
4551         vcpu->arch.pio.port = port;
4552         vcpu->arch.pio.in = in;
4553         vcpu->arch.pio.count  = count;
4554         vcpu->arch.pio.size = size;
4555
4556         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4557                 vcpu->arch.pio.count = 0;
4558                 return 1;
4559         }
4560
4561         vcpu->run->exit_reason = KVM_EXIT_IO;
4562         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4563         vcpu->run->io.size = size;
4564         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4565         vcpu->run->io.count = count;
4566         vcpu->run->io.port = port;
4567
4568         return 0;
4569 }
4570
4571 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4572                                     int size, unsigned short port, void *val,
4573                                     unsigned int count)
4574 {
4575         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4576         int ret;
4577
4578         if (vcpu->arch.pio.count)
4579                 goto data_avail;
4580
4581         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4582         if (ret) {
4583 data_avail:
4584                 memcpy(val, vcpu->arch.pio_data, size * count);
4585                 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4586                 vcpu->arch.pio.count = 0;
4587                 return 1;
4588         }
4589
4590         return 0;
4591 }
4592
4593 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4594                                      int size, unsigned short port,
4595                                      const void *val, unsigned int count)
4596 {
4597         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4598
4599         memcpy(vcpu->arch.pio_data, val, size * count);
4600         trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4601         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4602 }
4603
4604 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4605 {
4606         return kvm_x86_ops->get_segment_base(vcpu, seg);
4607 }
4608
4609 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4610 {
4611         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4612 }
4613
4614 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4615 {
4616         if (!need_emulate_wbinvd(vcpu))
4617                 return X86EMUL_CONTINUE;
4618
4619         if (kvm_x86_ops->has_wbinvd_exit()) {
4620                 int cpu = get_cpu();
4621
4622                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4623                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4624                                 wbinvd_ipi, NULL, 1);
4625                 put_cpu();
4626                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4627         } else
4628                 wbinvd();
4629         return X86EMUL_CONTINUE;
4630 }
4631 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4632
4633 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4634 {
4635         kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4636 }
4637
4638 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4639 {
4640         return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4641 }
4642
4643 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4644 {
4645
4646         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4647 }
4648
4649 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4650 {
4651         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4652 }
4653
4654 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4655 {
4656         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4657         unsigned long value;
4658
4659         switch (cr) {
4660         case 0:
4661                 value = kvm_read_cr0(vcpu);
4662                 break;
4663         case 2:
4664                 value = vcpu->arch.cr2;
4665                 break;
4666         case 3:
4667                 value = kvm_read_cr3(vcpu);
4668                 break;
4669         case 4:
4670                 value = kvm_read_cr4(vcpu);
4671                 break;
4672         case 8:
4673                 value = kvm_get_cr8(vcpu);
4674                 break;
4675         default:
4676                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4677                 return 0;
4678         }
4679
4680         return value;
4681 }
4682
4683 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4684 {
4685         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4686         int res = 0;
4687
4688         switch (cr) {
4689         case 0:
4690                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4691                 break;
4692         case 2:
4693                 vcpu->arch.cr2 = val;
4694                 break;
4695         case 3:
4696                 res = kvm_set_cr3(vcpu, val);
4697                 break;
4698         case 4:
4699                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4700                 break;
4701         case 8:
4702                 res = kvm_set_cr8(vcpu, val);
4703                 break;
4704         default:
4705                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4706                 res = -1;
4707         }
4708
4709         return res;
4710 }
4711
4712 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4713 {
4714         return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4715 }
4716
4717 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4718 {
4719         kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4720 }
4721
4722 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4723 {
4724         kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4725 }
4726
4727 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4728 {
4729         kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4730 }
4731
4732 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4733 {
4734         kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4735 }
4736
4737 static unsigned long emulator_get_cached_segment_base(
4738         struct x86_emulate_ctxt *ctxt, int seg)
4739 {
4740         return get_segment_base(emul_to_vcpu(ctxt), seg);
4741 }
4742
4743 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4744                                  struct desc_struct *desc, u32 *base3,
4745                                  int seg)
4746 {
4747         struct kvm_segment var;
4748
4749         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4750         *selector = var.selector;
4751
4752         if (var.unusable) {
4753                 memset(desc, 0, sizeof(*desc));
4754                 return false;
4755         }
4756
4757         if (var.g)
4758                 var.limit >>= 12;
4759         set_desc_limit(desc, var.limit);
4760         set_desc_base(desc, (unsigned long)var.base);
4761 #ifdef CONFIG_X86_64
4762         if (base3)
4763                 *base3 = var.base >> 32;
4764 #endif
4765         desc->type = var.type;
4766         desc->s = var.s;
4767         desc->dpl = var.dpl;
4768         desc->p = var.present;
4769         desc->avl = var.avl;
4770         desc->l = var.l;
4771         desc->d = var.db;
4772         desc->g = var.g;
4773
4774         return true;
4775 }
4776
4777 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4778                                  struct desc_struct *desc, u32 base3,
4779                                  int seg)
4780 {
4781         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4782         struct kvm_segment var;
4783
4784         var.selector = selector;
4785         var.base = get_desc_base(desc);
4786 #ifdef CONFIG_X86_64
4787         var.base |= ((u64)base3) << 32;
4788 #endif
4789         var.limit = get_desc_limit(desc);
4790         if (desc->g)
4791                 var.limit = (var.limit << 12) | 0xfff;
4792         var.type = desc->type;
4793         var.dpl = desc->dpl;
4794         var.db = desc->d;
4795         var.s = desc->s;
4796         var.l = desc->l;
4797         var.g = desc->g;
4798         var.avl = desc->avl;
4799         var.present = desc->p;
4800         var.unusable = !var.present;
4801         var.padding = 0;
4802
4803         kvm_set_segment(vcpu, &var, seg);
4804         return;
4805 }
4806
4807 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4808                             u32 msr_index, u64 *pdata)
4809 {
4810         return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4811 }
4812
4813 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4814                             u32 msr_index, u64 data)
4815 {
4816         struct msr_data msr;
4817
4818         msr.data = data;
4819         msr.index = msr_index;
4820         msr.host_initiated = false;
4821         return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4822 }
4823
4824 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4825                               u32 pmc)
4826 {
4827         return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4828 }
4829
4830 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4831                              u32 pmc, u64 *pdata)
4832 {
4833         return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4834 }
4835
4836 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4837 {
4838         emul_to_vcpu(ctxt)->arch.halt_request = 1;
4839 }
4840
4841 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4842 {
4843         preempt_disable();
4844         kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4845         /*
4846          * CR0.TS may reference the host fpu state, not the guest fpu state,
4847          * so it may be clear at this point.
4848          */
4849         clts();
4850 }
4851
4852 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4853 {
4854         preempt_enable();
4855 }
4856
4857 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4858                               struct x86_instruction_info *info,
4859                               enum x86_intercept_stage stage)
4860 {
4861         return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4862 }
4863
4864 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4865                                u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4866 {
4867         kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4868 }
4869
4870 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4871 {
4872         return kvm_register_read(emul_to_vcpu(ctxt), reg);
4873 }
4874
4875 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4876 {
4877         kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4878 }
4879
4880 static const struct x86_emulate_ops emulate_ops = {
4881         .read_gpr            = emulator_read_gpr,
4882         .write_gpr           = emulator_write_gpr,
4883         .read_std            = kvm_read_guest_virt_system,
4884         .write_std           = kvm_write_guest_virt_system,
4885         .fetch               = kvm_fetch_guest_virt,
4886         .read_emulated       = emulator_read_emulated,
4887         .write_emulated      = emulator_write_emulated,
4888         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
4889         .invlpg              = emulator_invlpg,
4890         .pio_in_emulated     = emulator_pio_in_emulated,
4891         .pio_out_emulated    = emulator_pio_out_emulated,
4892         .get_segment         = emulator_get_segment,
4893         .set_segment         = emulator_set_segment,
4894         .get_cached_segment_base = emulator_get_cached_segment_base,
4895         .get_gdt             = emulator_get_gdt,
4896         .get_idt             = emulator_get_idt,
4897         .set_gdt             = emulator_set_gdt,
4898         .set_idt             = emulator_set_idt,
4899         .get_cr              = emulator_get_cr,
4900         .set_cr              = emulator_set_cr,
4901         .cpl                 = emulator_get_cpl,
4902         .get_dr              = emulator_get_dr,
4903         .set_dr              = emulator_set_dr,
4904         .set_msr             = emulator_set_msr,
4905         .get_msr             = emulator_get_msr,
4906         .check_pmc           = emulator_check_pmc,
4907         .read_pmc            = emulator_read_pmc,
4908         .halt                = emulator_halt,
4909         .wbinvd              = emulator_wbinvd,
4910         .fix_hypercall       = emulator_fix_hypercall,
4911         .get_fpu             = emulator_get_fpu,
4912         .put_fpu             = emulator_put_fpu,
4913         .intercept           = emulator_intercept,
4914         .get_cpuid           = emulator_get_cpuid,
4915 };
4916
4917 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4918 {
4919         u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
4920         /*
4921          * an sti; sti; sequence only disable interrupts for the first
4922          * instruction. So, if the last instruction, be it emulated or
4923          * not, left the system with the INT_STI flag enabled, it
4924          * means that the last instruction is an sti. We should not
4925          * leave the flag on in this case. The same goes for mov ss
4926          */
4927         if (int_shadow & mask)
4928                 mask = 0;
4929         if (unlikely(int_shadow || mask)) {
4930                 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4931                 if (!mask)
4932                         kvm_make_request(KVM_REQ_EVENT, vcpu);
4933         }
4934 }
4935
4936 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
4937 {
4938         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4939         if (ctxt->exception.vector == PF_VECTOR)
4940                 return kvm_propagate_fault(vcpu, &ctxt->exception);
4941
4942         if (ctxt->exception.error_code_valid)
4943                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4944                                       ctxt->exception.error_code);
4945         else
4946                 kvm_queue_exception(vcpu, ctxt->exception.vector);
4947         return false;
4948 }
4949
4950 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4951 {
4952         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4953         int cs_db, cs_l;
4954
4955         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4956
4957         ctxt->eflags = kvm_get_rflags(vcpu);
4958         ctxt->eip = kvm_rip_read(vcpu);
4959         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
4960                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
4961                      (cs_l && is_long_mode(vcpu))       ? X86EMUL_MODE_PROT64 :
4962                      cs_db                              ? X86EMUL_MODE_PROT32 :
4963                                                           X86EMUL_MODE_PROT16;
4964         ctxt->guest_mode = is_guest_mode(vcpu);
4965
4966         init_decode_cache(ctxt);
4967         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4968 }
4969
4970 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4971 {
4972         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4973         int ret;
4974
4975         init_emulate_ctxt(vcpu);
4976
4977         ctxt->op_bytes = 2;
4978         ctxt->ad_bytes = 2;
4979         ctxt->_eip = ctxt->eip + inc_eip;
4980         ret = emulate_int_real(ctxt, irq);
4981
4982         if (ret != X86EMUL_CONTINUE)
4983                 return EMULATE_FAIL;
4984
4985         ctxt->eip = ctxt->_eip;
4986         kvm_rip_write(vcpu, ctxt->eip);
4987         kvm_set_rflags(vcpu, ctxt->eflags);
4988
4989         if (irq == NMI_VECTOR)
4990                 vcpu->arch.nmi_pending = 0;
4991         else
4992                 vcpu->arch.interrupt.pending = false;
4993
4994         return EMULATE_DONE;
4995 }
4996 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4997
4998 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4999 {
5000         int r = EMULATE_DONE;
5001
5002         ++vcpu->stat.insn_emulation_fail;
5003         trace_kvm_emulate_insn_failed(vcpu);
5004         if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5005                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5006                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5007                 vcpu->run->internal.ndata = 0;
5008                 r = EMULATE_FAIL;
5009         }
5010         kvm_queue_exception(vcpu, UD_VECTOR);
5011
5012         return r;
5013 }
5014
5015 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5016                                   bool write_fault_to_shadow_pgtable,
5017                                   int emulation_type)
5018 {
5019         gpa_t gpa = cr2;
5020         pfn_t pfn;
5021
5022         if (emulation_type & EMULTYPE_NO_REEXECUTE)
5023                 return false;
5024
5025         if (!vcpu->arch.mmu.direct_map) {
5026                 /*
5027                  * Write permission should be allowed since only
5028                  * write access need to be emulated.
5029                  */
5030                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5031
5032                 /*
5033                  * If the mapping is invalid in guest, let cpu retry
5034                  * it to generate fault.
5035                  */
5036                 if (gpa == UNMAPPED_GVA)
5037                         return true;
5038         }
5039
5040         /*
5041          * Do not retry the unhandleable instruction if it faults on the
5042          * readonly host memory, otherwise it will goto a infinite loop:
5043          * retry instruction -> write #PF -> emulation fail -> retry
5044          * instruction -> ...
5045          */
5046         pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5047
5048         /*
5049          * If the instruction failed on the error pfn, it can not be fixed,
5050          * report the error to userspace.
5051          */
5052         if (is_error_noslot_pfn(pfn))
5053                 return false;
5054
5055         kvm_release_pfn_clean(pfn);
5056
5057         /* The instructions are well-emulated on direct mmu. */
5058         if (vcpu->arch.mmu.direct_map) {
5059                 unsigned int indirect_shadow_pages;
5060
5061                 spin_lock(&vcpu->kvm->mmu_lock);
5062                 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5063                 spin_unlock(&vcpu->kvm->mmu_lock);
5064
5065                 if (indirect_shadow_pages)
5066                         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5067
5068                 return true;
5069         }
5070
5071         /*
5072          * if emulation was due to access to shadowed page table
5073          * and it failed try to unshadow page and re-enter the
5074          * guest to let CPU execute the instruction.
5075          */
5076         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5077
5078         /*
5079          * If the access faults on its page table, it can not
5080          * be fixed by unprotecting shadow page and it should
5081          * be reported to userspace.
5082          */
5083         return !write_fault_to_shadow_pgtable;
5084 }
5085
5086 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5087                               unsigned long cr2,  int emulation_type)
5088 {
5089         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5090         unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5091
5092         last_retry_eip = vcpu->arch.last_retry_eip;
5093         last_retry_addr = vcpu->arch.last_retry_addr;
5094
5095         /*
5096          * If the emulation is caused by #PF and it is non-page_table
5097          * writing instruction, it means the VM-EXIT is caused by shadow
5098          * page protected, we can zap the shadow page and retry this
5099          * instruction directly.
5100          *
5101          * Note: if the guest uses a non-page-table modifying instruction
5102          * on the PDE that points to the instruction, then we will unmap
5103          * the instruction and go to an infinite loop. So, we cache the
5104          * last retried eip and the last fault address, if we meet the eip
5105          * and the address again, we can break out of the potential infinite
5106          * loop.
5107          */
5108         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5109
5110         if (!(emulation_type & EMULTYPE_RETRY))
5111                 return false;
5112
5113         if (x86_page_table_writing_insn(ctxt))
5114                 return false;
5115
5116         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5117                 return false;
5118
5119         vcpu->arch.last_retry_eip = ctxt->eip;
5120         vcpu->arch.last_retry_addr = cr2;
5121
5122         if (!vcpu->arch.mmu.direct_map)
5123                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5124
5125         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5126
5127         return true;
5128 }
5129
5130 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5131 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5132
5133 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5134                                 unsigned long *db)
5135 {
5136         u32 dr6 = 0;
5137         int i;
5138         u32 enable, rwlen;
5139
5140         enable = dr7;
5141         rwlen = dr7 >> 16;
5142         for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5143                 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5144                         dr6 |= (1 << i);
5145         return dr6;
5146 }
5147
5148 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5149 {
5150         struct kvm_run *kvm_run = vcpu->run;
5151
5152         /*
5153          * rflags is the old, "raw" value of the flags.  The new value has
5154          * not been saved yet.
5155          *
5156          * This is correct even for TF set by the guest, because "the
5157          * processor will not generate this exception after the instruction
5158          * that sets the TF flag".
5159          */
5160         if (unlikely(rflags & X86_EFLAGS_TF)) {
5161                 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5162                         kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5163                                                   DR6_RTM;
5164                         kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5165                         kvm_run->debug.arch.exception = DB_VECTOR;
5166                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
5167                         *r = EMULATE_USER_EXIT;
5168                 } else {
5169                         vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5170                         /*
5171                          * "Certain debug exceptions may clear bit 0-3.  The
5172                          * remaining contents of the DR6 register are never
5173                          * cleared by the processor".
5174                          */
5175                         vcpu->arch.dr6 &= ~15;
5176                         vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5177                         kvm_queue_exception(vcpu, DB_VECTOR);
5178                 }
5179         }
5180 }
5181
5182 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5183 {
5184         struct kvm_run *kvm_run = vcpu->run;
5185         unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5186         u32 dr6 = 0;
5187
5188         if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5189             (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5190                 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5191                                            vcpu->arch.guest_debug_dr7,
5192                                            vcpu->arch.eff_db);
5193
5194                 if (dr6 != 0) {
5195                         kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5196                         kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5197                                 get_segment_base(vcpu, VCPU_SREG_CS);
5198
5199                         kvm_run->debug.arch.exception = DB_VECTOR;
5200                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
5201                         *r = EMULATE_USER_EXIT;
5202                         return true;
5203                 }
5204         }
5205
5206         if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5207             !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5208                 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5209                                            vcpu->arch.dr7,
5210                                            vcpu->arch.db);
5211
5212                 if (dr6 != 0) {
5213                         vcpu->arch.dr6 &= ~15;
5214                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5215                         kvm_queue_exception(vcpu, DB_VECTOR);
5216                         *r = EMULATE_DONE;
5217                         return true;
5218                 }
5219         }
5220
5221         return false;
5222 }
5223
5224 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5225                             unsigned long cr2,
5226                             int emulation_type,
5227                             void *insn,
5228                             int insn_len)
5229 {
5230         int r;
5231         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5232         bool writeback = true;
5233         bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5234
5235         /*
5236          * Clear write_fault_to_shadow_pgtable here to ensure it is
5237          * never reused.
5238          */
5239         vcpu->arch.write_fault_to_shadow_pgtable = false;
5240         kvm_clear_exception_queue(vcpu);
5241
5242         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5243                 init_emulate_ctxt(vcpu);
5244
5245                 /*
5246                  * We will reenter on the same instruction since
5247                  * we do not set complete_userspace_io.  This does not
5248                  * handle watchpoints yet, those would be handled in
5249                  * the emulate_ops.
5250                  */
5251                 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5252                         return r;
5253
5254                 ctxt->interruptibility = 0;
5255                 ctxt->have_exception = false;
5256                 ctxt->exception.vector = -1;
5257                 ctxt->perm_ok = false;
5258
5259                 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5260
5261                 r = x86_decode_insn(ctxt, insn, insn_len);
5262
5263                 trace_kvm_emulate_insn_start(vcpu);
5264                 ++vcpu->stat.insn_emulation;
5265                 if (r != EMULATION_OK)  {
5266                         if (emulation_type & EMULTYPE_TRAP_UD)
5267                                 return EMULATE_FAIL;
5268                         if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5269                                                 emulation_type))
5270                                 return EMULATE_DONE;
5271                         if (emulation_type & EMULTYPE_SKIP)
5272                                 return EMULATE_FAIL;
5273                         return handle_emulation_failure(vcpu);
5274                 }
5275         }
5276
5277         if (emulation_type & EMULTYPE_SKIP) {
5278                 kvm_rip_write(vcpu, ctxt->_eip);
5279                 if (ctxt->eflags & X86_EFLAGS_RF)
5280                         kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5281                 return EMULATE_DONE;
5282         }
5283
5284         if (retry_instruction(ctxt, cr2, emulation_type))
5285                 return EMULATE_DONE;
5286
5287         /* this is needed for vmware backdoor interface to work since it
5288            changes registers values  during IO operation */
5289         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5290                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5291                 emulator_invalidate_register_cache(ctxt);
5292         }
5293
5294 restart:
5295         r = x86_emulate_insn(ctxt);
5296
5297         if (r == EMULATION_INTERCEPTED)
5298                 return EMULATE_DONE;
5299
5300         if (r == EMULATION_FAILED) {
5301                 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5302                                         emulation_type))
5303                         return EMULATE_DONE;
5304
5305                 return handle_emulation_failure(vcpu);
5306         }
5307
5308         if (ctxt->have_exception) {
5309                 r = EMULATE_DONE;
5310                 if (inject_emulated_exception(vcpu))
5311                         return r;
5312         } else if (vcpu->arch.pio.count) {
5313                 if (!vcpu->arch.pio.in) {
5314                         /* FIXME: return into emulator if single-stepping.  */
5315                         vcpu->arch.pio.count = 0;
5316                 } else {
5317                         writeback = false;
5318                         vcpu->arch.complete_userspace_io = complete_emulated_pio;
5319                 }
5320                 r = EMULATE_USER_EXIT;
5321         } else if (vcpu->mmio_needed) {
5322                 if (!vcpu->mmio_is_write)
5323                         writeback = false;
5324                 r = EMULATE_USER_EXIT;
5325                 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5326         } else if (r == EMULATION_RESTART)
5327                 goto restart;
5328         else
5329                 r = EMULATE_DONE;
5330
5331         if (writeback) {
5332                 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5333                 toggle_interruptibility(vcpu, ctxt->interruptibility);
5334                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5335                 kvm_rip_write(vcpu, ctxt->eip);
5336                 if (r == EMULATE_DONE)
5337                         kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5338                 __kvm_set_rflags(vcpu, ctxt->eflags);
5339
5340                 /*
5341                  * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5342                  * do nothing, and it will be requested again as soon as
5343                  * the shadow expires.  But we still need to check here,
5344                  * because POPF has no interrupt shadow.
5345                  */
5346                 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5347                         kvm_make_request(KVM_REQ_EVENT, vcpu);
5348         } else
5349                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5350
5351         return r;
5352 }
5353 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5354
5355 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5356 {
5357         unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5358         int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5359                                             size, port, &val, 1);
5360         /* do not return to emulator after return from userspace */
5361         vcpu->arch.pio.count = 0;
5362         return ret;
5363 }
5364 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5365
5366 static void tsc_bad(void *info)
5367 {
5368         __this_cpu_write(cpu_tsc_khz, 0);
5369 }
5370
5371 static void tsc_khz_changed(void *data)
5372 {
5373         struct cpufreq_freqs *freq = data;
5374         unsigned long khz = 0;
5375
5376         if (data)
5377                 khz = freq->new;
5378         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5379                 khz = cpufreq_quick_get(raw_smp_processor_id());
5380         if (!khz)
5381                 khz = tsc_khz;
5382         __this_cpu_write(cpu_tsc_khz, khz);
5383 }
5384
5385 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5386                                      void *data)
5387 {
5388         struct cpufreq_freqs *freq = data;
5389         struct kvm *kvm;
5390         struct kvm_vcpu *vcpu;
5391         int i, send_ipi = 0;
5392
5393         /*
5394          * We allow guests to temporarily run on slowing clocks,
5395          * provided we notify them after, or to run on accelerating
5396          * clocks, provided we notify them before.  Thus time never
5397          * goes backwards.
5398          *
5399          * However, we have a problem.  We can't atomically update
5400          * the frequency of a given CPU from this function; it is
5401          * merely a notifier, which can be called from any CPU.
5402          * Changing the TSC frequency at arbitrary points in time
5403          * requires a recomputation of local variables related to
5404          * the TSC for each VCPU.  We must flag these local variables
5405          * to be updated and be sure the update takes place with the
5406          * new frequency before any guests proceed.
5407          *
5408          * Unfortunately, the combination of hotplug CPU and frequency
5409          * change creates an intractable locking scenario; the order
5410          * of when these callouts happen is undefined with respect to
5411          * CPU hotplug, and they can race with each other.  As such,
5412          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5413          * undefined; you can actually have a CPU frequency change take
5414          * place in between the computation of X and the setting of the
5415          * variable.  To protect against this problem, all updates of
5416          * the per_cpu tsc_khz variable are done in an interrupt
5417          * protected IPI, and all callers wishing to update the value
5418          * must wait for a synchronous IPI to complete (which is trivial
5419          * if the caller is on the CPU already).  This establishes the
5420          * necessary total order on variable updates.
5421          *
5422          * Note that because a guest time update may take place
5423          * anytime after the setting of the VCPU's request bit, the
5424          * correct TSC value must be set before the request.  However,
5425          * to ensure the update actually makes it to any guest which
5426          * starts running in hardware virtualization between the set
5427          * and the acquisition of the spinlock, we must also ping the
5428          * CPU after setting the request bit.
5429          *
5430          */
5431
5432         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5433                 return 0;
5434         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5435                 return 0;
5436
5437         smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5438
5439         spin_lock(&kvm_lock);
5440         list_for_each_entry(kvm, &vm_list, vm_list) {
5441                 kvm_for_each_vcpu(i, vcpu, kvm) {
5442                         if (vcpu->cpu != freq->cpu)
5443                                 continue;
5444                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5445                         if (vcpu->cpu != smp_processor_id())
5446                                 send_ipi = 1;
5447                 }
5448         }
5449         spin_unlock(&kvm_lock);
5450
5451         if (freq->old < freq->new && send_ipi) {
5452                 /*
5453                  * We upscale the frequency.  Must make the guest
5454                  * doesn't see old kvmclock values while running with
5455                  * the new frequency, otherwise we risk the guest sees
5456                  * time go backwards.
5457                  *
5458                  * In case we update the frequency for another cpu
5459                  * (which might be in guest context) send an interrupt
5460                  * to kick the cpu out of guest context.  Next time
5461                  * guest context is entered kvmclock will be updated,
5462                  * so the guest will not see stale values.
5463                  */
5464                 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5465         }
5466         return 0;
5467 }
5468
5469 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5470         .notifier_call  = kvmclock_cpufreq_notifier
5471 };
5472
5473 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5474                                         unsigned long action, void *hcpu)
5475 {
5476         unsigned int cpu = (unsigned long)hcpu;
5477
5478         switch (action) {
5479                 case CPU_ONLINE:
5480                 case CPU_DOWN_FAILED:
5481                         smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5482                         break;
5483                 case CPU_DOWN_PREPARE:
5484                         smp_call_function_single(cpu, tsc_bad, NULL, 1);
5485                         break;
5486         }
5487         return NOTIFY_OK;
5488 }
5489
5490 static struct notifier_block kvmclock_cpu_notifier_block = {
5491         .notifier_call  = kvmclock_cpu_notifier,
5492         .priority = -INT_MAX
5493 };
5494
5495 static void kvm_timer_init(void)
5496 {
5497         int cpu;
5498
5499         max_tsc_khz = tsc_khz;
5500
5501         cpu_notifier_register_begin();
5502         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5503 #ifdef CONFIG_CPU_FREQ
5504                 struct cpufreq_policy policy;
5505                 memset(&policy, 0, sizeof(policy));
5506                 cpu = get_cpu();
5507                 cpufreq_get_policy(&policy, cpu);
5508                 if (policy.cpuinfo.max_freq)
5509                         max_tsc_khz = policy.cpuinfo.max_freq;
5510                 put_cpu();
5511 #endif
5512                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5513                                           CPUFREQ_TRANSITION_NOTIFIER);
5514         }
5515         pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5516         for_each_online_cpu(cpu)
5517                 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5518
5519         __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5520         cpu_notifier_register_done();
5521
5522 }
5523
5524 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5525
5526 int kvm_is_in_guest(void)
5527 {
5528         return __this_cpu_read(current_vcpu) != NULL;
5529 }
5530
5531 static int kvm_is_user_mode(void)
5532 {
5533         int user_mode = 3;
5534
5535         if (__this_cpu_read(current_vcpu))
5536                 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5537
5538         return user_mode != 0;
5539 }
5540
5541 static unsigned long kvm_get_guest_ip(void)
5542 {
5543         unsigned long ip = 0;
5544
5545         if (__this_cpu_read(current_vcpu))
5546                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5547
5548         return ip;
5549 }
5550
5551 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5552         .is_in_guest            = kvm_is_in_guest,
5553         .is_user_mode           = kvm_is_user_mode,
5554         .get_guest_ip           = kvm_get_guest_ip,
5555 };
5556
5557 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5558 {
5559         __this_cpu_write(current_vcpu, vcpu);
5560 }
5561 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5562
5563 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5564 {
5565         __this_cpu_write(current_vcpu, NULL);
5566 }
5567 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5568
5569 static void kvm_set_mmio_spte_mask(void)
5570 {
5571         u64 mask;
5572         int maxphyaddr = boot_cpu_data.x86_phys_bits;
5573
5574         /*
5575          * Set the reserved bits and the present bit of an paging-structure
5576          * entry to generate page fault with PFER.RSV = 1.
5577          */
5578          /* Mask the reserved physical address bits. */
5579         mask = rsvd_bits(maxphyaddr, 51);
5580
5581         /* Bit 62 is always reserved for 32bit host. */
5582         mask |= 0x3ull << 62;
5583
5584         /* Set the present bit. */
5585         mask |= 1ull;
5586
5587 #ifdef CONFIG_X86_64
5588         /*
5589          * If reserved bit is not supported, clear the present bit to disable
5590          * mmio page fault.
5591          */
5592         if (maxphyaddr == 52)
5593                 mask &= ~1ull;
5594 #endif
5595
5596         kvm_mmu_set_mmio_spte_mask(mask);
5597 }
5598
5599 #ifdef CONFIG_X86_64
5600 static void pvclock_gtod_update_fn(struct work_struct *work)
5601 {
5602         struct kvm *kvm;
5603
5604         struct kvm_vcpu *vcpu;
5605         int i;
5606
5607         spin_lock(&kvm_lock);
5608         list_for_each_entry(kvm, &vm_list, vm_list)
5609                 kvm_for_each_vcpu(i, vcpu, kvm)
5610                         kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5611         atomic_set(&kvm_guest_has_master_clock, 0);
5612         spin_unlock(&kvm_lock);
5613 }
5614
5615 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5616
5617 /*
5618  * Notification about pvclock gtod data update.
5619  */
5620 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5621                                void *priv)
5622 {
5623         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5624         struct timekeeper *tk = priv;
5625
5626         update_pvclock_gtod(tk);
5627
5628         /* disable master clock if host does not trust, or does not
5629          * use, TSC clocksource
5630          */
5631         if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5632             atomic_read(&kvm_guest_has_master_clock) != 0)
5633                 queue_work(system_long_wq, &pvclock_gtod_work);
5634
5635         return 0;
5636 }
5637
5638 static struct notifier_block pvclock_gtod_notifier = {
5639         .notifier_call = pvclock_gtod_notify,
5640 };
5641 #endif
5642
5643 int kvm_arch_init(void *opaque)
5644 {
5645         int r;
5646         struct kvm_x86_ops *ops = opaque;
5647
5648         if (kvm_x86_ops) {
5649                 printk(KERN_ERR "kvm: already loaded the other module\n");
5650                 r = -EEXIST;
5651                 goto out;
5652         }
5653
5654         if (!ops->cpu_has_kvm_support()) {
5655                 printk(KERN_ERR "kvm: no hardware support\n");
5656                 r = -EOPNOTSUPP;
5657                 goto out;
5658         }
5659         if (ops->disabled_by_bios()) {
5660                 printk(KERN_ERR "kvm: disabled by bios\n");
5661                 r = -EOPNOTSUPP;
5662                 goto out;
5663         }
5664
5665         r = -ENOMEM;
5666         shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5667         if (!shared_msrs) {
5668                 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5669                 goto out;
5670         }
5671
5672         r = kvm_mmu_module_init();
5673         if (r)
5674                 goto out_free_percpu;
5675
5676         kvm_set_mmio_spte_mask();
5677
5678         kvm_x86_ops = ops;
5679         kvm_init_msr_list();
5680
5681         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5682                         PT_DIRTY_MASK, PT64_NX_MASK, 0);
5683
5684         kvm_timer_init();
5685
5686         perf_register_guest_info_callbacks(&kvm_guest_cbs);
5687
5688         if (cpu_has_xsave)
5689                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5690
5691         kvm_lapic_init();
5692 #ifdef CONFIG_X86_64
5693         pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5694 #endif
5695
5696         return 0;
5697
5698 out_free_percpu:
5699         free_percpu(shared_msrs);
5700 out:
5701         return r;
5702 }
5703
5704 void kvm_arch_exit(void)
5705 {
5706         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5707
5708         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5709                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5710                                             CPUFREQ_TRANSITION_NOTIFIER);
5711         unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5712 #ifdef CONFIG_X86_64
5713         pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5714 #endif
5715         kvm_x86_ops = NULL;
5716         kvm_mmu_module_exit();
5717         free_percpu(shared_msrs);
5718 }
5719
5720 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5721 {
5722         ++vcpu->stat.halt_exits;
5723         if (irqchip_in_kernel(vcpu->kvm)) {
5724                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5725                 return 1;
5726         } else {
5727                 vcpu->run->exit_reason = KVM_EXIT_HLT;
5728                 return 0;
5729         }
5730 }
5731 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5732
5733 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5734 {
5735         u64 param, ingpa, outgpa, ret;
5736         uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5737         bool fast, longmode;
5738
5739         /*
5740          * hypercall generates UD from non zero cpl and real mode
5741          * per HYPER-V spec
5742          */
5743         if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5744                 kvm_queue_exception(vcpu, UD_VECTOR);
5745                 return 0;
5746         }
5747
5748         longmode = is_64_bit_mode(vcpu);
5749
5750         if (!longmode) {
5751                 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5752                         (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5753                 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5754                         (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5755                 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5756                         (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5757         }
5758 #ifdef CONFIG_X86_64
5759         else {
5760                 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5761                 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5762                 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5763         }
5764 #endif
5765
5766         code = param & 0xffff;
5767         fast = (param >> 16) & 0x1;
5768         rep_cnt = (param >> 32) & 0xfff;
5769         rep_idx = (param >> 48) & 0xfff;
5770
5771         trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5772
5773         switch (code) {
5774         case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5775                 kvm_vcpu_on_spin(vcpu);
5776                 break;
5777         default:
5778                 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5779                 break;
5780         }
5781
5782         ret = res | (((u64)rep_done & 0xfff) << 32);
5783         if (longmode) {
5784                 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5785         } else {
5786                 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5787                 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5788         }
5789
5790         return 1;
5791 }
5792
5793 /*
5794  * kvm_pv_kick_cpu_op:  Kick a vcpu.
5795  *
5796  * @apicid - apicid of vcpu to be kicked.
5797  */
5798 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5799 {
5800         struct kvm_lapic_irq lapic_irq;
5801
5802         lapic_irq.shorthand = 0;
5803         lapic_irq.dest_mode = 0;
5804         lapic_irq.dest_id = apicid;
5805
5806         lapic_irq.delivery_mode = APIC_DM_REMRD;
5807         kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
5808 }
5809
5810 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5811 {
5812         unsigned long nr, a0, a1, a2, a3, ret;
5813         int op_64_bit, r = 1;
5814
5815         if (kvm_hv_hypercall_enabled(vcpu->kvm))
5816                 return kvm_hv_hypercall(vcpu);
5817
5818         nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5819         a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5820         a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5821         a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5822         a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5823
5824         trace_kvm_hypercall(nr, a0, a1, a2, a3);
5825
5826         op_64_bit = is_64_bit_mode(vcpu);
5827         if (!op_64_bit) {
5828                 nr &= 0xFFFFFFFF;
5829                 a0 &= 0xFFFFFFFF;
5830                 a1 &= 0xFFFFFFFF;
5831                 a2 &= 0xFFFFFFFF;
5832                 a3 &= 0xFFFFFFFF;
5833         }
5834
5835         if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5836                 ret = -KVM_EPERM;
5837                 goto out;
5838         }
5839
5840         switch (nr) {
5841         case KVM_HC_VAPIC_POLL_IRQ:
5842                 ret = 0;
5843                 break;
5844         case KVM_HC_KICK_CPU:
5845                 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5846                 ret = 0;
5847                 break;
5848         default:
5849                 ret = -KVM_ENOSYS;
5850                 break;
5851         }
5852 out:
5853         if (!op_64_bit)
5854                 ret = (u32)ret;
5855         kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5856         ++vcpu->stat.hypercalls;
5857         return r;
5858 }
5859 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5860
5861 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5862 {
5863         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5864         char instruction[3];
5865         unsigned long rip = kvm_rip_read(vcpu);
5866
5867         kvm_x86_ops->patch_hypercall(vcpu, instruction);
5868
5869         return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5870 }
5871
5872 /*
5873  * Check if userspace requested an interrupt window, and that the
5874  * interrupt window is open.
5875  *
5876  * No need to exit to userspace if we already have an interrupt queued.
5877  */
5878 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5879 {
5880         return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5881                 vcpu->run->request_interrupt_window &&
5882                 kvm_arch_interrupt_allowed(vcpu));
5883 }
5884
5885 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5886 {
5887         struct kvm_run *kvm_run = vcpu->run;
5888
5889         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5890         kvm_run->cr8 = kvm_get_cr8(vcpu);
5891         kvm_run->apic_base = kvm_get_apic_base(vcpu);
5892         if (irqchip_in_kernel(vcpu->kvm))
5893                 kvm_run->ready_for_interrupt_injection = 1;
5894         else
5895                 kvm_run->ready_for_interrupt_injection =
5896                         kvm_arch_interrupt_allowed(vcpu) &&
5897                         !kvm_cpu_has_interrupt(vcpu) &&
5898                         !kvm_event_needs_reinjection(vcpu);
5899 }
5900
5901 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5902 {
5903         int max_irr, tpr;
5904
5905         if (!kvm_x86_ops->update_cr8_intercept)
5906                 return;
5907
5908         if (!vcpu->arch.apic)
5909                 return;
5910
5911         if (!vcpu->arch.apic->vapic_addr)
5912                 max_irr = kvm_lapic_find_highest_irr(vcpu);
5913         else
5914                 max_irr = -1;
5915
5916         if (max_irr != -1)
5917                 max_irr >>= 4;
5918
5919         tpr = kvm_lapic_get_cr8(vcpu);
5920
5921         kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5922 }
5923
5924 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
5925 {
5926         int r;
5927
5928         /* try to reinject previous events if any */
5929         if (vcpu->arch.exception.pending) {
5930                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5931                                         vcpu->arch.exception.has_error_code,
5932                                         vcpu->arch.exception.error_code);
5933
5934                 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5935                         __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5936                                              X86_EFLAGS_RF);
5937
5938                 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5939                                           vcpu->arch.exception.has_error_code,
5940                                           vcpu->arch.exception.error_code,
5941                                           vcpu->arch.exception.reinject);
5942                 return 0;
5943         }
5944
5945         if (vcpu->arch.nmi_injected) {
5946                 kvm_x86_ops->set_nmi(vcpu);
5947                 return 0;
5948         }
5949
5950         if (vcpu->arch.interrupt.pending) {
5951                 kvm_x86_ops->set_irq(vcpu);
5952                 return 0;
5953         }
5954
5955         if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5956                 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5957                 if (r != 0)
5958                         return r;
5959         }
5960
5961         /* try to inject new event if pending */
5962         if (vcpu->arch.nmi_pending) {
5963                 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5964                         --vcpu->arch.nmi_pending;
5965                         vcpu->arch.nmi_injected = true;
5966                         kvm_x86_ops->set_nmi(vcpu);
5967                 }
5968         } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5969                 /*
5970                  * Because interrupts can be injected asynchronously, we are
5971                  * calling check_nested_events again here to avoid a race condition.
5972                  * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5973                  * proposal and current concerns.  Perhaps we should be setting
5974                  * KVM_REQ_EVENT only on certain events and not unconditionally?
5975                  */
5976                 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5977                         r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5978                         if (r != 0)
5979                                 return r;
5980                 }
5981                 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5982                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5983                                             false);
5984                         kvm_x86_ops->set_irq(vcpu);
5985                 }
5986         }
5987         return 0;
5988 }
5989
5990 static void process_nmi(struct kvm_vcpu *vcpu)
5991 {
5992         unsigned limit = 2;
5993
5994         /*
5995          * x86 is limited to one NMI running, and one NMI pending after it.
5996          * If an NMI is already in progress, limit further NMIs to just one.
5997          * Otherwise, allow two (and we'll inject the first one immediately).
5998          */
5999         if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6000                 limit = 1;
6001
6002         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6003         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6004         kvm_make_request(KVM_REQ_EVENT, vcpu);
6005 }
6006
6007 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6008 {
6009         u64 eoi_exit_bitmap[4];
6010         u32 tmr[8];
6011
6012         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6013                 return;
6014
6015         memset(eoi_exit_bitmap, 0, 32);
6016         memset(tmr, 0, 32);
6017
6018         kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
6019         kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6020         kvm_apic_update_tmr(vcpu, tmr);
6021 }
6022
6023 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6024 {
6025         ++vcpu->stat.tlb_flush;
6026         kvm_x86_ops->tlb_flush(vcpu);
6027 }
6028
6029 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6030 {
6031         struct page *page = NULL;
6032
6033         if (!irqchip_in_kernel(vcpu->kvm))
6034                 return;
6035
6036         if (!kvm_x86_ops->set_apic_access_page_addr)
6037                 return;
6038
6039         page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6040         kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6041
6042         /*
6043          * Do not pin apic access page in memory, the MMU notifier
6044          * will call us again if it is migrated or swapped out.
6045          */
6046         put_page(page);
6047 }
6048 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6049
6050 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6051                                            unsigned long address)
6052 {
6053         /*
6054          * The physical address of apic access page is stored in the VMCS.
6055          * Update it when it becomes invalid.
6056          */
6057         if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6058                 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6059 }
6060
6061 /*
6062  * Returns 1 to let __vcpu_run() continue the guest execution loop without
6063  * exiting to the userspace.  Otherwise, the value will be returned to the
6064  * userspace.
6065  */
6066 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6067 {
6068         int r;
6069         bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
6070                 vcpu->run->request_interrupt_window;
6071         bool req_immediate_exit = false;
6072
6073         if (vcpu->requests) {
6074                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6075                         kvm_mmu_unload(vcpu);
6076                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6077                         __kvm_migrate_timers(vcpu);
6078                 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6079                         kvm_gen_update_masterclock(vcpu->kvm);
6080                 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6081                         kvm_gen_kvmclock_update(vcpu);
6082                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6083                         r = kvm_guest_time_update(vcpu);
6084                         if (unlikely(r))
6085                                 goto out;
6086                 }
6087                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6088                         kvm_mmu_sync_roots(vcpu);
6089                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6090                         kvm_vcpu_flush_tlb(vcpu);
6091                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6092                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6093                         r = 0;
6094                         goto out;
6095                 }
6096                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6097                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6098                         r = 0;
6099                         goto out;
6100                 }
6101                 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6102                         vcpu->fpu_active = 0;
6103                         kvm_x86_ops->fpu_deactivate(vcpu);
6104                 }
6105                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6106                         /* Page is swapped out. Do synthetic halt */
6107                         vcpu->arch.apf.halted = true;
6108                         r = 1;
6109                         goto out;
6110                 }
6111                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6112                         record_steal_time(vcpu);
6113                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6114                         process_nmi(vcpu);
6115                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6116                         kvm_handle_pmu_event(vcpu);
6117                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6118                         kvm_deliver_pmi(vcpu);
6119                 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6120                         vcpu_scan_ioapic(vcpu);
6121                 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6122                         kvm_vcpu_reload_apic_access_page(vcpu);
6123         }
6124
6125         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6126                 kvm_apic_accept_events(vcpu);
6127                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6128                         r = 1;
6129                         goto out;
6130                 }
6131
6132                 if (inject_pending_event(vcpu, req_int_win) != 0)
6133                         req_immediate_exit = true;
6134                 /* enable NMI/IRQ window open exits if needed */
6135                 else if (vcpu->arch.nmi_pending)
6136                         kvm_x86_ops->enable_nmi_window(vcpu);
6137                 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6138                         kvm_x86_ops->enable_irq_window(vcpu);
6139
6140                 if (kvm_lapic_enabled(vcpu)) {
6141                         /*
6142                          * Update architecture specific hints for APIC
6143                          * virtual interrupt delivery.
6144                          */
6145                         if (kvm_x86_ops->hwapic_irr_update)
6146                                 kvm_x86_ops->hwapic_irr_update(vcpu,
6147                                         kvm_lapic_find_highest_irr(vcpu));
6148                         update_cr8_intercept(vcpu);
6149                         kvm_lapic_sync_to_vapic(vcpu);
6150                 }
6151         }
6152
6153         r = kvm_mmu_reload(vcpu);
6154         if (unlikely(r)) {
6155                 goto cancel_injection;
6156         }
6157
6158         preempt_disable();
6159
6160         kvm_x86_ops->prepare_guest_switch(vcpu);
6161         if (vcpu->fpu_active)
6162                 kvm_load_guest_fpu(vcpu);
6163         kvm_load_guest_xcr0(vcpu);
6164
6165         vcpu->mode = IN_GUEST_MODE;
6166
6167         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6168
6169         /* We should set ->mode before check ->requests,
6170          * see the comment in make_all_cpus_request.
6171          */
6172         smp_mb__after_srcu_read_unlock();
6173
6174         local_irq_disable();
6175
6176         if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6177             || need_resched() || signal_pending(current)) {
6178                 vcpu->mode = OUTSIDE_GUEST_MODE;
6179                 smp_wmb();
6180                 local_irq_enable();
6181                 preempt_enable();
6182                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6183                 r = 1;
6184                 goto cancel_injection;
6185         }
6186
6187         if (req_immediate_exit)
6188                 smp_send_reschedule(vcpu->cpu);
6189
6190         kvm_guest_enter();
6191
6192         if (unlikely(vcpu->arch.switch_db_regs)) {
6193                 set_debugreg(0, 7);
6194                 set_debugreg(vcpu->arch.eff_db[0], 0);
6195                 set_debugreg(vcpu->arch.eff_db[1], 1);
6196                 set_debugreg(vcpu->arch.eff_db[2], 2);
6197                 set_debugreg(vcpu->arch.eff_db[3], 3);
6198                 set_debugreg(vcpu->arch.dr6, 6);
6199         }
6200
6201         trace_kvm_entry(vcpu->vcpu_id);
6202         kvm_x86_ops->run(vcpu);
6203
6204         /*
6205          * Do this here before restoring debug registers on the host.  And
6206          * since we do this before handling the vmexit, a DR access vmexit
6207          * can (a) read the correct value of the debug registers, (b) set
6208          * KVM_DEBUGREG_WONT_EXIT again.
6209          */
6210         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6211                 int i;
6212
6213                 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6214                 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6215                 for (i = 0; i < KVM_NR_DB_REGS; i++)
6216                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6217         }
6218
6219         /*
6220          * If the guest has used debug registers, at least dr7
6221          * will be disabled while returning to the host.
6222          * If we don't have active breakpoints in the host, we don't
6223          * care about the messed up debug address registers. But if
6224          * we have some of them active, restore the old state.
6225          */
6226         if (hw_breakpoint_active())
6227                 hw_breakpoint_restore();
6228
6229         vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6230                                                            native_read_tsc());
6231
6232         vcpu->mode = OUTSIDE_GUEST_MODE;
6233         smp_wmb();
6234
6235         /* Interrupt is enabled by handle_external_intr() */
6236         kvm_x86_ops->handle_external_intr(vcpu);
6237
6238         ++vcpu->stat.exits;
6239
6240         /*
6241          * We must have an instruction between local_irq_enable() and
6242          * kvm_guest_exit(), so the timer interrupt isn't delayed by
6243          * the interrupt shadow.  The stat.exits increment will do nicely.
6244          * But we need to prevent reordering, hence this barrier():
6245          */
6246         barrier();
6247
6248         kvm_guest_exit();
6249
6250         preempt_enable();
6251
6252         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6253
6254         /*
6255          * Profile KVM exit RIPs:
6256          */
6257         if (unlikely(prof_on == KVM_PROFILING)) {
6258                 unsigned long rip = kvm_rip_read(vcpu);
6259                 profile_hit(KVM_PROFILING, (void *)rip);
6260         }
6261
6262         if (unlikely(vcpu->arch.tsc_always_catchup))
6263                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6264
6265         if (vcpu->arch.apic_attention)
6266                 kvm_lapic_sync_from_vapic(vcpu);
6267
6268         r = kvm_x86_ops->handle_exit(vcpu);
6269         return r;
6270
6271 cancel_injection:
6272         kvm_x86_ops->cancel_injection(vcpu);
6273         if (unlikely(vcpu->arch.apic_attention))
6274                 kvm_lapic_sync_from_vapic(vcpu);
6275 out:
6276         return r;
6277 }
6278
6279
6280 static int __vcpu_run(struct kvm_vcpu *vcpu)
6281 {
6282         int r;
6283         struct kvm *kvm = vcpu->kvm;
6284
6285         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6286
6287         r = 1;
6288         while (r > 0) {
6289                 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6290                     !vcpu->arch.apf.halted)
6291                         r = vcpu_enter_guest(vcpu);
6292                 else {
6293                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6294                         kvm_vcpu_block(vcpu);
6295                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6296                         if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6297                                 kvm_apic_accept_events(vcpu);
6298                                 switch(vcpu->arch.mp_state) {
6299                                 case KVM_MP_STATE_HALTED:
6300                                         vcpu->arch.pv.pv_unhalted = false;
6301                                         vcpu->arch.mp_state =
6302                                                 KVM_MP_STATE_RUNNABLE;
6303                                 case KVM_MP_STATE_RUNNABLE:
6304                                         vcpu->arch.apf.halted = false;
6305                                         break;
6306                                 case KVM_MP_STATE_INIT_RECEIVED:
6307                                         break;
6308                                 default:
6309                                         r = -EINTR;
6310                                         break;
6311                                 }
6312                         }
6313                 }
6314
6315                 if (r <= 0)
6316                         break;
6317
6318                 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6319                 if (kvm_cpu_has_pending_timer(vcpu))
6320                         kvm_inject_pending_timer_irqs(vcpu);
6321
6322                 if (dm_request_for_irq_injection(vcpu)) {
6323                         r = -EINTR;
6324                         vcpu->run->exit_reason = KVM_EXIT_INTR;
6325                         ++vcpu->stat.request_irq_exits;
6326                 }
6327
6328                 kvm_check_async_pf_completion(vcpu);
6329
6330                 if (signal_pending(current)) {
6331                         r = -EINTR;
6332                         vcpu->run->exit_reason = KVM_EXIT_INTR;
6333                         ++vcpu->stat.signal_exits;
6334                 }
6335                 if (need_resched()) {
6336                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6337                         cond_resched();
6338                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6339                 }
6340         }
6341
6342         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6343
6344         return r;
6345 }
6346
6347 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6348 {
6349         int r;
6350         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6351         r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6352         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6353         if (r != EMULATE_DONE)
6354                 return 0;
6355         return 1;
6356 }
6357
6358 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6359 {
6360         BUG_ON(!vcpu->arch.pio.count);
6361
6362         return complete_emulated_io(vcpu);
6363 }
6364
6365 /*
6366  * Implements the following, as a state machine:
6367  *
6368  * read:
6369  *   for each fragment
6370  *     for each mmio piece in the fragment
6371  *       write gpa, len
6372  *       exit
6373  *       copy data
6374  *   execute insn
6375  *
6376  * write:
6377  *   for each fragment
6378  *     for each mmio piece in the fragment
6379  *       write gpa, len
6380  *       copy data
6381  *       exit
6382  */
6383 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6384 {
6385         struct kvm_run *run = vcpu->run;
6386         struct kvm_mmio_fragment *frag;
6387         unsigned len;
6388
6389         BUG_ON(!vcpu->mmio_needed);
6390
6391         /* Complete previous fragment */
6392         frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6393         len = min(8u, frag->len);
6394         if (!vcpu->mmio_is_write)
6395                 memcpy(frag->data, run->mmio.data, len);
6396
6397         if (frag->len <= 8) {
6398                 /* Switch to the next fragment. */
6399                 frag++;
6400                 vcpu->mmio_cur_fragment++;
6401         } else {
6402                 /* Go forward to the next mmio piece. */
6403                 frag->data += len;
6404                 frag->gpa += len;
6405                 frag->len -= len;
6406         }
6407
6408         if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6409                 vcpu->mmio_needed = 0;
6410
6411                 /* FIXME: return into emulator if single-stepping.  */
6412                 if (vcpu->mmio_is_write)
6413                         return 1;
6414                 vcpu->mmio_read_completed = 1;
6415                 return complete_emulated_io(vcpu);
6416         }
6417
6418         run->exit_reason = KVM_EXIT_MMIO;
6419         run->mmio.phys_addr = frag->gpa;
6420         if (vcpu->mmio_is_write)
6421                 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6422         run->mmio.len = min(8u, frag->len);
6423         run->mmio.is_write = vcpu->mmio_is_write;
6424         vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6425         return 0;
6426 }
6427
6428
6429 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6430 {
6431         int r;
6432         sigset_t sigsaved;
6433
6434         if (!tsk_used_math(current) && init_fpu(current))
6435                 return -ENOMEM;
6436
6437         if (vcpu->sigset_active)
6438                 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6439
6440         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6441                 kvm_vcpu_block(vcpu);
6442                 kvm_apic_accept_events(vcpu);
6443                 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6444                 r = -EAGAIN;
6445                 goto out;
6446         }
6447
6448         /* re-sync apic's tpr */
6449         if (!irqchip_in_kernel(vcpu->kvm)) {
6450                 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6451                         r = -EINVAL;
6452                         goto out;
6453                 }
6454         }
6455
6456         if (unlikely(vcpu->arch.complete_userspace_io)) {
6457                 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6458                 vcpu->arch.complete_userspace_io = NULL;
6459                 r = cui(vcpu);
6460                 if (r <= 0)
6461                         goto out;
6462         } else
6463                 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6464
6465         r = __vcpu_run(vcpu);
6466
6467 out:
6468         post_kvm_run_save(vcpu);
6469         if (vcpu->sigset_active)
6470                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6471
6472         return r;
6473 }
6474
6475 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6476 {
6477         if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6478                 /*
6479                  * We are here if userspace calls get_regs() in the middle of
6480                  * instruction emulation. Registers state needs to be copied
6481                  * back from emulation context to vcpu. Userspace shouldn't do
6482                  * that usually, but some bad designed PV devices (vmware
6483                  * backdoor interface) need this to work
6484                  */
6485                 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6486                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6487         }
6488         regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6489         regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6490         regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6491         regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6492         regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6493         regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6494         regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6495         regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6496 #ifdef CONFIG_X86_64
6497         regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6498         regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6499         regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6500         regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6501         regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6502         regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6503         regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6504         regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6505 #endif
6506
6507         regs->rip = kvm_rip_read(vcpu);
6508         regs->rflags = kvm_get_rflags(vcpu);
6509
6510         return 0;
6511 }
6512
6513 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6514 {
6515         vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6516         vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6517
6518         kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6519         kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6520         kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6521         kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6522         kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6523         kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6524         kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6525         kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6526 #ifdef CONFIG_X86_64
6527         kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6528         kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6529         kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6530         kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6531         kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6532         kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6533         kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6534         kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6535 #endif
6536
6537         kvm_rip_write(vcpu, regs->rip);
6538         kvm_set_rflags(vcpu, regs->rflags);
6539
6540         vcpu->arch.exception.pending = false;
6541
6542         kvm_make_request(KVM_REQ_EVENT, vcpu);
6543
6544         return 0;
6545 }
6546
6547 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6548 {
6549         struct kvm_segment cs;
6550
6551         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6552         *db = cs.db;
6553         *l = cs.l;
6554 }
6555 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6556
6557 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6558                                   struct kvm_sregs *sregs)
6559 {
6560         struct desc_ptr dt;
6561
6562         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6563         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6564         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6565         kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6566         kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6567         kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6568
6569         kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6570         kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6571
6572         kvm_x86_ops->get_idt(vcpu, &dt);
6573         sregs->idt.limit = dt.size;
6574         sregs->idt.base = dt.address;
6575         kvm_x86_ops->get_gdt(vcpu, &dt);
6576         sregs->gdt.limit = dt.size;
6577         sregs->gdt.base = dt.address;
6578
6579         sregs->cr0 = kvm_read_cr0(vcpu);
6580         sregs->cr2 = vcpu->arch.cr2;
6581         sregs->cr3 = kvm_read_cr3(vcpu);
6582         sregs->cr4 = kvm_read_cr4(vcpu);
6583         sregs->cr8 = kvm_get_cr8(vcpu);
6584         sregs->efer = vcpu->arch.efer;
6585         sregs->apic_base = kvm_get_apic_base(vcpu);
6586
6587         memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6588
6589         if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6590                 set_bit(vcpu->arch.interrupt.nr,
6591                         (unsigned long *)sregs->interrupt_bitmap);
6592
6593         return 0;
6594 }
6595
6596 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6597                                     struct kvm_mp_state *mp_state)
6598 {
6599         kvm_apic_accept_events(vcpu);
6600         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6601                                         vcpu->arch.pv.pv_unhalted)
6602                 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6603         else
6604                 mp_state->mp_state = vcpu->arch.mp_state;
6605
6606         return 0;
6607 }
6608
6609 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6610                                     struct kvm_mp_state *mp_state)
6611 {
6612         if (!kvm_vcpu_has_lapic(vcpu) &&
6613             mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6614                 return -EINVAL;
6615
6616         if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6617                 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6618                 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6619         } else
6620                 vcpu->arch.mp_state = mp_state->mp_state;
6621         kvm_make_request(KVM_REQ_EVENT, vcpu);
6622         return 0;
6623 }
6624
6625 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6626                     int reason, bool has_error_code, u32 error_code)
6627 {
6628         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6629         int ret;
6630
6631         init_emulate_ctxt(vcpu);
6632
6633         ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6634                                    has_error_code, error_code);
6635
6636         if (ret)
6637                 return EMULATE_FAIL;
6638
6639         kvm_rip_write(vcpu, ctxt->eip);
6640         kvm_set_rflags(vcpu, ctxt->eflags);
6641         kvm_make_request(KVM_REQ_EVENT, vcpu);
6642         return EMULATE_DONE;
6643 }
6644 EXPORT_SYMBOL_GPL(kvm_task_switch);
6645
6646 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6647                                   struct kvm_sregs *sregs)
6648 {
6649         struct msr_data apic_base_msr;
6650         int mmu_reset_needed = 0;
6651         int pending_vec, max_bits, idx;
6652         struct desc_ptr dt;
6653
6654         if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6655                 return -EINVAL;
6656
6657         dt.size = sregs->idt.limit;
6658         dt.address = sregs->idt.base;
6659         kvm_x86_ops->set_idt(vcpu, &dt);
6660         dt.size = sregs->gdt.limit;
6661         dt.address = sregs->gdt.base;
6662         kvm_x86_ops->set_gdt(vcpu, &dt);
6663
6664         vcpu->arch.cr2 = sregs->cr2;
6665         mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6666         vcpu->arch.cr3 = sregs->cr3;
6667         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6668
6669         kvm_set_cr8(vcpu, sregs->cr8);
6670
6671         mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6672         kvm_x86_ops->set_efer(vcpu, sregs->efer);
6673         apic_base_msr.data = sregs->apic_base;
6674         apic_base_msr.host_initiated = true;
6675         kvm_set_apic_base(vcpu, &apic_base_msr);
6676
6677         mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6678         kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6679         vcpu->arch.cr0 = sregs->cr0;
6680
6681         mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6682         kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6683         if (sregs->cr4 & X86_CR4_OSXSAVE)
6684                 kvm_update_cpuid(vcpu);
6685
6686         idx = srcu_read_lock(&vcpu->kvm->srcu);
6687         if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6688                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6689                 mmu_reset_needed = 1;
6690         }
6691         srcu_read_unlock(&vcpu->kvm->srcu, idx);
6692
6693         if (mmu_reset_needed)
6694                 kvm_mmu_reset_context(vcpu);
6695
6696         max_bits = KVM_NR_INTERRUPTS;
6697         pending_vec = find_first_bit(
6698                 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6699         if (pending_vec < max_bits) {
6700                 kvm_queue_interrupt(vcpu, pending_vec, false);
6701                 pr_debug("Set back pending irq %d\n", pending_vec);
6702         }
6703
6704         kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6705         kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6706         kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6707         kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6708         kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6709         kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6710
6711         kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6712         kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6713
6714         update_cr8_intercept(vcpu);
6715
6716         /* Older userspace won't unhalt the vcpu on reset. */
6717         if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6718             sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6719             !is_protmode(vcpu))
6720                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6721
6722         kvm_make_request(KVM_REQ_EVENT, vcpu);
6723
6724         return 0;
6725 }
6726
6727 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6728                                         struct kvm_guest_debug *dbg)
6729 {
6730         unsigned long rflags;
6731         int i, r;
6732
6733         if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6734                 r = -EBUSY;
6735                 if (vcpu->arch.exception.pending)
6736                         goto out;
6737                 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6738                         kvm_queue_exception(vcpu, DB_VECTOR);
6739                 else
6740                         kvm_queue_exception(vcpu, BP_VECTOR);
6741         }
6742
6743         /*
6744          * Read rflags as long as potentially injected trace flags are still
6745          * filtered out.
6746          */
6747         rflags = kvm_get_rflags(vcpu);
6748
6749         vcpu->guest_debug = dbg->control;
6750         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6751                 vcpu->guest_debug = 0;
6752
6753         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6754                 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6755                         vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6756                 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6757         } else {
6758                 for (i = 0; i < KVM_NR_DB_REGS; i++)
6759                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6760         }
6761         kvm_update_dr7(vcpu);
6762
6763         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6764                 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6765                         get_segment_base(vcpu, VCPU_SREG_CS);
6766
6767         /*
6768          * Trigger an rflags update that will inject or remove the trace
6769          * flags.
6770          */
6771         kvm_set_rflags(vcpu, rflags);
6772
6773         kvm_x86_ops->update_db_bp_intercept(vcpu);
6774
6775         r = 0;
6776
6777 out:
6778
6779         return r;
6780 }
6781
6782 /*
6783  * Translate a guest virtual address to a guest physical address.
6784  */
6785 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6786                                     struct kvm_translation *tr)
6787 {
6788         unsigned long vaddr = tr->linear_address;
6789         gpa_t gpa;
6790         int idx;
6791
6792         idx = srcu_read_lock(&vcpu->kvm->srcu);
6793         gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6794         srcu_read_unlock(&vcpu->kvm->srcu, idx);
6795         tr->physical_address = gpa;
6796         tr->valid = gpa != UNMAPPED_GVA;
6797         tr->writeable = 1;
6798         tr->usermode = 0;
6799
6800         return 0;
6801 }
6802
6803 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6804 {
6805         struct i387_fxsave_struct *fxsave =
6806                         &vcpu->arch.guest_fpu.state->fxsave;
6807
6808         memcpy(fpu->fpr, fxsave->st_space, 128);
6809         fpu->fcw = fxsave->cwd;
6810         fpu->fsw = fxsave->swd;
6811         fpu->ftwx = fxsave->twd;
6812         fpu->last_opcode = fxsave->fop;
6813         fpu->last_ip = fxsave->rip;
6814         fpu->last_dp = fxsave->rdp;
6815         memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6816
6817         return 0;
6818 }
6819
6820 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6821 {
6822         struct i387_fxsave_struct *fxsave =
6823                         &vcpu->arch.guest_fpu.state->fxsave;
6824
6825         memcpy(fxsave->st_space, fpu->fpr, 128);
6826         fxsave->cwd = fpu->fcw;
6827         fxsave->swd = fpu->fsw;
6828         fxsave->twd = fpu->ftwx;
6829         fxsave->fop = fpu->last_opcode;
6830         fxsave->rip = fpu->last_ip;
6831         fxsave->rdp = fpu->last_dp;
6832         memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6833
6834         return 0;
6835 }
6836
6837 int fx_init(struct kvm_vcpu *vcpu)
6838 {
6839         int err;
6840
6841         err = fpu_alloc(&vcpu->arch.guest_fpu);
6842         if (err)
6843                 return err;
6844
6845         fpu_finit(&vcpu->arch.guest_fpu);
6846
6847         /*
6848          * Ensure guest xcr0 is valid for loading
6849          */
6850         vcpu->arch.xcr0 = XSTATE_FP;
6851
6852         vcpu->arch.cr0 |= X86_CR0_ET;
6853
6854         return 0;
6855 }
6856 EXPORT_SYMBOL_GPL(fx_init);
6857
6858 static void fx_free(struct kvm_vcpu *vcpu)
6859 {
6860         fpu_free(&vcpu->arch.guest_fpu);
6861 }
6862
6863 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6864 {
6865         if (vcpu->guest_fpu_loaded)
6866                 return;
6867
6868         /*
6869          * Restore all possible states in the guest,
6870          * and assume host would use all available bits.
6871          * Guest xcr0 would be loaded later.
6872          */
6873         kvm_put_guest_xcr0(vcpu);
6874         vcpu->guest_fpu_loaded = 1;
6875         __kernel_fpu_begin();
6876         fpu_restore_checking(&vcpu->arch.guest_fpu);
6877         trace_kvm_fpu(1);
6878 }
6879
6880 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6881 {
6882         kvm_put_guest_xcr0(vcpu);
6883
6884         if (!vcpu->guest_fpu_loaded)
6885                 return;
6886
6887         vcpu->guest_fpu_loaded = 0;
6888         fpu_save_init(&vcpu->arch.guest_fpu);
6889         __kernel_fpu_end();
6890         ++vcpu->stat.fpu_reload;
6891         kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6892         trace_kvm_fpu(0);
6893 }
6894
6895 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6896 {
6897         kvmclock_reset(vcpu);
6898
6899         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6900         fx_free(vcpu);
6901         kvm_x86_ops->vcpu_free(vcpu);
6902 }
6903
6904 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6905                                                 unsigned int id)
6906 {
6907         if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6908                 printk_once(KERN_WARNING
6909                 "kvm: SMP vm created on host with unstable TSC; "
6910                 "guest TSC will not be reliable\n");
6911         return kvm_x86_ops->vcpu_create(kvm, id);
6912 }
6913
6914 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6915 {
6916         int r;
6917
6918         vcpu->arch.mtrr_state.have_fixed = 1;
6919         r = vcpu_load(vcpu);
6920         if (r)
6921                 return r;
6922         kvm_vcpu_reset(vcpu);
6923         kvm_mmu_setup(vcpu);
6924         vcpu_put(vcpu);
6925
6926         return r;
6927 }
6928
6929 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6930 {
6931         int r;
6932         struct msr_data msr;
6933         struct kvm *kvm = vcpu->kvm;
6934
6935         r = vcpu_load(vcpu);
6936         if (r)
6937                 return r;
6938         msr.data = 0x0;
6939         msr.index = MSR_IA32_TSC;
6940         msr.host_initiated = true;
6941         kvm_write_tsc(vcpu, &msr);
6942         vcpu_put(vcpu);
6943
6944         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6945                                         KVMCLOCK_SYNC_PERIOD);
6946
6947         return r;
6948 }
6949
6950 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6951 {
6952         int r;
6953         vcpu->arch.apf.msr_val = 0;
6954
6955         r = vcpu_load(vcpu);
6956         BUG_ON(r);
6957         kvm_mmu_unload(vcpu);
6958         vcpu_put(vcpu);
6959
6960         fx_free(vcpu);
6961         kvm_x86_ops->vcpu_free(vcpu);
6962 }
6963
6964 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6965 {
6966         atomic_set(&vcpu->arch.nmi_queued, 0);
6967         vcpu->arch.nmi_pending = 0;
6968         vcpu->arch.nmi_injected = false;
6969         kvm_clear_interrupt_queue(vcpu);
6970         kvm_clear_exception_queue(vcpu);
6971
6972         memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6973         vcpu->arch.dr6 = DR6_INIT;
6974         kvm_update_dr6(vcpu);
6975         vcpu->arch.dr7 = DR7_FIXED_1;
6976         kvm_update_dr7(vcpu);
6977
6978         kvm_make_request(KVM_REQ_EVENT, vcpu);
6979         vcpu->arch.apf.msr_val = 0;
6980         vcpu->arch.st.msr_val = 0;
6981
6982         kvmclock_reset(vcpu);
6983
6984         kvm_clear_async_pf_completion_queue(vcpu);
6985         kvm_async_pf_hash_reset(vcpu);
6986         vcpu->arch.apf.halted = false;
6987
6988         kvm_pmu_reset(vcpu);
6989
6990         memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6991         vcpu->arch.regs_avail = ~0;
6992         vcpu->arch.regs_dirty = ~0;
6993
6994         kvm_x86_ops->vcpu_reset(vcpu);
6995 }
6996
6997 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6998 {
6999         struct kvm_segment cs;
7000
7001         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7002         cs.selector = vector << 8;
7003         cs.base = vector << 12;
7004         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7005         kvm_rip_write(vcpu, 0);
7006 }
7007
7008 int kvm_arch_hardware_enable(void)
7009 {
7010         struct kvm *kvm;
7011         struct kvm_vcpu *vcpu;
7012         int i;
7013         int ret;
7014         u64 local_tsc;
7015         u64 max_tsc = 0;
7016         bool stable, backwards_tsc = false;
7017
7018         kvm_shared_msr_cpu_online();
7019         ret = kvm_x86_ops->hardware_enable();
7020         if (ret != 0)
7021                 return ret;
7022
7023         local_tsc = native_read_tsc();
7024         stable = !check_tsc_unstable();
7025         list_for_each_entry(kvm, &vm_list, vm_list) {
7026                 kvm_for_each_vcpu(i, vcpu, kvm) {
7027                         if (!stable && vcpu->cpu == smp_processor_id())
7028                                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7029                         if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7030                                 backwards_tsc = true;
7031                                 if (vcpu->arch.last_host_tsc > max_tsc)
7032                                         max_tsc = vcpu->arch.last_host_tsc;
7033                         }
7034                 }
7035         }
7036
7037         /*
7038          * Sometimes, even reliable TSCs go backwards.  This happens on
7039          * platforms that reset TSC during suspend or hibernate actions, but
7040          * maintain synchronization.  We must compensate.  Fortunately, we can
7041          * detect that condition here, which happens early in CPU bringup,
7042          * before any KVM threads can be running.  Unfortunately, we can't
7043          * bring the TSCs fully up to date with real time, as we aren't yet far
7044          * enough into CPU bringup that we know how much real time has actually
7045          * elapsed; our helper function, get_kernel_ns() will be using boot
7046          * variables that haven't been updated yet.
7047          *
7048          * So we simply find the maximum observed TSC above, then record the
7049          * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
7050          * the adjustment will be applied.  Note that we accumulate
7051          * adjustments, in case multiple suspend cycles happen before some VCPU
7052          * gets a chance to run again.  In the event that no KVM threads get a
7053          * chance to run, we will miss the entire elapsed period, as we'll have
7054          * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7055          * loose cycle time.  This isn't too big a deal, since the loss will be
7056          * uniform across all VCPUs (not to mention the scenario is extremely
7057          * unlikely). It is possible that a second hibernate recovery happens
7058          * much faster than a first, causing the observed TSC here to be
7059          * smaller; this would require additional padding adjustment, which is
7060          * why we set last_host_tsc to the local tsc observed here.
7061          *
7062          * N.B. - this code below runs only on platforms with reliable TSC,
7063          * as that is the only way backwards_tsc is set above.  Also note
7064          * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7065          * have the same delta_cyc adjustment applied if backwards_tsc
7066          * is detected.  Note further, this adjustment is only done once,
7067          * as we reset last_host_tsc on all VCPUs to stop this from being
7068          * called multiple times (one for each physical CPU bringup).
7069          *
7070          * Platforms with unreliable TSCs don't have to deal with this, they
7071          * will be compensated by the logic in vcpu_load, which sets the TSC to
7072          * catchup mode.  This will catchup all VCPUs to real time, but cannot
7073          * guarantee that they stay in perfect synchronization.
7074          */
7075         if (backwards_tsc) {
7076                 u64 delta_cyc = max_tsc - local_tsc;
7077                 backwards_tsc_observed = true;
7078                 list_for_each_entry(kvm, &vm_list, vm_list) {
7079                         kvm_for_each_vcpu(i, vcpu, kvm) {
7080                                 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7081                                 vcpu->arch.last_host_tsc = local_tsc;
7082                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7083                         }
7084
7085                         /*
7086                          * We have to disable TSC offset matching.. if you were
7087                          * booting a VM while issuing an S4 host suspend....
7088                          * you may have some problem.  Solving this issue is
7089                          * left as an exercise to the reader.
7090                          */
7091                         kvm->arch.last_tsc_nsec = 0;
7092                         kvm->arch.last_tsc_write = 0;
7093                 }
7094
7095         }
7096         return 0;
7097 }
7098
7099 void kvm_arch_hardware_disable(void)
7100 {
7101         kvm_x86_ops->hardware_disable();
7102         drop_user_return_notifiers();
7103 }
7104
7105 int kvm_arch_hardware_setup(void)
7106 {
7107         return kvm_x86_ops->hardware_setup();
7108 }
7109
7110 void kvm_arch_hardware_unsetup(void)
7111 {
7112         kvm_x86_ops->hardware_unsetup();
7113 }
7114
7115 void kvm_arch_check_processor_compat(void *rtn)
7116 {
7117         kvm_x86_ops->check_processor_compatibility(rtn);
7118 }
7119
7120 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7121 {
7122         return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7123 }
7124
7125 struct static_key kvm_no_apic_vcpu __read_mostly;
7126
7127 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7128 {
7129         struct page *page;
7130         struct kvm *kvm;
7131         int r;
7132
7133         BUG_ON(vcpu->kvm == NULL);
7134         kvm = vcpu->kvm;
7135
7136         vcpu->arch.pv.pv_unhalted = false;
7137         vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7138         if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
7139                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7140         else
7141                 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7142
7143         page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7144         if (!page) {
7145                 r = -ENOMEM;
7146                 goto fail;
7147         }
7148         vcpu->arch.pio_data = page_address(page);
7149
7150         kvm_set_tsc_khz(vcpu, max_tsc_khz);
7151
7152         r = kvm_mmu_create(vcpu);
7153         if (r < 0)
7154                 goto fail_free_pio_data;
7155
7156         if (irqchip_in_kernel(kvm)) {
7157                 r = kvm_create_lapic(vcpu);
7158                 if (r < 0)
7159                         goto fail_mmu_destroy;
7160         } else
7161                 static_key_slow_inc(&kvm_no_apic_vcpu);
7162
7163         vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7164                                        GFP_KERNEL);
7165         if (!vcpu->arch.mce_banks) {
7166                 r = -ENOMEM;
7167                 goto fail_free_lapic;
7168         }
7169         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7170
7171         if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7172                 r = -ENOMEM;
7173                 goto fail_free_mce_banks;
7174         }
7175
7176         r = fx_init(vcpu);
7177         if (r)
7178                 goto fail_free_wbinvd_dirty_mask;
7179
7180         vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7181         vcpu->arch.pv_time_enabled = false;
7182
7183         vcpu->arch.guest_supported_xcr0 = 0;
7184         vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7185
7186         kvm_async_pf_hash_reset(vcpu);
7187         kvm_pmu_init(vcpu);
7188
7189         return 0;
7190 fail_free_wbinvd_dirty_mask:
7191         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7192 fail_free_mce_banks:
7193         kfree(vcpu->arch.mce_banks);
7194 fail_free_lapic:
7195         kvm_free_lapic(vcpu);
7196 fail_mmu_destroy:
7197         kvm_mmu_destroy(vcpu);
7198 fail_free_pio_data:
7199         free_page((unsigned long)vcpu->arch.pio_data);
7200 fail:
7201         return r;
7202 }
7203
7204 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7205 {
7206         int idx;
7207
7208         kvm_pmu_destroy(vcpu);
7209         kfree(vcpu->arch.mce_banks);
7210         kvm_free_lapic(vcpu);
7211         idx = srcu_read_lock(&vcpu->kvm->srcu);
7212         kvm_mmu_destroy(vcpu);
7213         srcu_read_unlock(&vcpu->kvm->srcu, idx);
7214         free_page((unsigned long)vcpu->arch.pio_data);
7215         if (!irqchip_in_kernel(vcpu->kvm))
7216                 static_key_slow_dec(&kvm_no_apic_vcpu);
7217 }
7218
7219 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7220 {
7221         kvm_x86_ops->sched_in(vcpu, cpu);
7222 }
7223
7224 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7225 {
7226         if (type)
7227                 return -EINVAL;
7228
7229         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7230         INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7231         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7232         atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7233
7234         /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7235         set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7236         /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7237         set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7238                 &kvm->arch.irq_sources_bitmap);
7239
7240         raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7241         mutex_init(&kvm->arch.apic_map_lock);
7242         spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7243
7244         pvclock_update_vm_gtod_copy(kvm);
7245
7246         INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7247         INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7248
7249         return 0;
7250 }
7251
7252 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7253 {
7254         int r;
7255         r = vcpu_load(vcpu);
7256         BUG_ON(r);
7257         kvm_mmu_unload(vcpu);
7258         vcpu_put(vcpu);
7259 }
7260
7261 static void kvm_free_vcpus(struct kvm *kvm)
7262 {
7263         unsigned int i;
7264         struct kvm_vcpu *vcpu;
7265
7266         /*
7267          * Unpin any mmu pages first.
7268          */
7269         kvm_for_each_vcpu(i, vcpu, kvm) {
7270                 kvm_clear_async_pf_completion_queue(vcpu);
7271                 kvm_unload_vcpu_mmu(vcpu);
7272         }
7273         kvm_for_each_vcpu(i, vcpu, kvm)
7274                 kvm_arch_vcpu_free(vcpu);
7275
7276         mutex_lock(&kvm->lock);
7277         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7278                 kvm->vcpus[i] = NULL;
7279
7280         atomic_set(&kvm->online_vcpus, 0);
7281         mutex_unlock(&kvm->lock);
7282 }
7283
7284 void kvm_arch_sync_events(struct kvm *kvm)
7285 {
7286         cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7287         cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7288         kvm_free_all_assigned_devices(kvm);
7289         kvm_free_pit(kvm);
7290 }
7291
7292 void kvm_arch_destroy_vm(struct kvm *kvm)
7293 {
7294         if (current->mm == kvm->mm) {
7295                 /*
7296                  * Free memory regions allocated on behalf of userspace,
7297                  * unless the the memory map has changed due to process exit
7298                  * or fd copying.
7299                  */
7300                 struct kvm_userspace_memory_region mem;
7301                 memset(&mem, 0, sizeof(mem));
7302                 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7303                 kvm_set_memory_region(kvm, &mem);
7304
7305                 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7306                 kvm_set_memory_region(kvm, &mem);
7307
7308                 mem.slot = TSS_PRIVATE_MEMSLOT;
7309                 kvm_set_memory_region(kvm, &mem);
7310         }
7311         kvm_iommu_unmap_guest(kvm);
7312         kfree(kvm->arch.vpic);
7313         kfree(kvm->arch.vioapic);
7314         kvm_free_vcpus(kvm);
7315         kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7316 }
7317
7318 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7319                            struct kvm_memory_slot *dont)
7320 {
7321         int i;
7322
7323         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7324                 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7325                         kvm_kvfree(free->arch.rmap[i]);
7326                         free->arch.rmap[i] = NULL;
7327                 }
7328                 if (i == 0)
7329                         continue;
7330
7331                 if (!dont || free->arch.lpage_info[i - 1] !=
7332                              dont->arch.lpage_info[i - 1]) {
7333                         kvm_kvfree(free->arch.lpage_info[i - 1]);
7334                         free->arch.lpage_info[i - 1] = NULL;
7335                 }
7336         }
7337 }
7338
7339 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7340                             unsigned long npages)
7341 {
7342         int i;
7343
7344         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7345                 unsigned long ugfn;
7346                 int lpages;
7347                 int level = i + 1;
7348
7349                 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7350                                       slot->base_gfn, level) + 1;
7351
7352                 slot->arch.rmap[i] =
7353                         kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7354                 if (!slot->arch.rmap[i])
7355                         goto out_free;
7356                 if (i == 0)
7357                         continue;
7358
7359                 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7360                                         sizeof(*slot->arch.lpage_info[i - 1]));
7361                 if (!slot->arch.lpage_info[i - 1])
7362                         goto out_free;
7363
7364                 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7365                         slot->arch.lpage_info[i - 1][0].write_count = 1;
7366                 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7367                         slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7368                 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7369                 /*
7370                  * If the gfn and userspace address are not aligned wrt each
7371                  * other, or if explicitly asked to, disable large page
7372                  * support for this slot
7373                  */
7374                 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7375                     !kvm_largepages_enabled()) {
7376                         unsigned long j;
7377
7378                         for (j = 0; j < lpages; ++j)
7379                                 slot->arch.lpage_info[i - 1][j].write_count = 1;
7380                 }
7381         }
7382
7383         return 0;
7384
7385 out_free:
7386         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7387                 kvm_kvfree(slot->arch.rmap[i]);
7388                 slot->arch.rmap[i] = NULL;
7389                 if (i == 0)
7390                         continue;
7391
7392                 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7393                 slot->arch.lpage_info[i - 1] = NULL;
7394         }
7395         return -ENOMEM;
7396 }
7397
7398 void kvm_arch_memslots_updated(struct kvm *kvm)
7399 {
7400         /*
7401          * memslots->generation has been incremented.
7402          * mmio generation may have reached its maximum value.
7403          */
7404         kvm_mmu_invalidate_mmio_sptes(kvm);
7405 }
7406
7407 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7408                                 struct kvm_memory_slot *memslot,
7409                                 struct kvm_userspace_memory_region *mem,
7410                                 enum kvm_mr_change change)
7411 {
7412         /*
7413          * Only private memory slots need to be mapped here since
7414          * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7415          */
7416         if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7417                 unsigned long userspace_addr;
7418
7419                 /*
7420                  * MAP_SHARED to prevent internal slot pages from being moved
7421                  * by fork()/COW.
7422                  */
7423                 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7424                                          PROT_READ | PROT_WRITE,
7425                                          MAP_SHARED | MAP_ANONYMOUS, 0);
7426
7427                 if (IS_ERR((void *)userspace_addr))
7428                         return PTR_ERR((void *)userspace_addr);
7429
7430                 memslot->userspace_addr = userspace_addr;
7431         }
7432
7433         return 0;
7434 }
7435
7436 void kvm_arch_commit_memory_region(struct kvm *kvm,
7437                                 struct kvm_userspace_memory_region *mem,
7438                                 const struct kvm_memory_slot *old,
7439                                 enum kvm_mr_change change)
7440 {
7441
7442         int nr_mmu_pages = 0;
7443
7444         if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7445                 int ret;
7446
7447                 ret = vm_munmap(old->userspace_addr,
7448                                 old->npages * PAGE_SIZE);
7449                 if (ret < 0)
7450                         printk(KERN_WARNING
7451                                "kvm_vm_ioctl_set_memory_region: "
7452                                "failed to munmap memory\n");
7453         }
7454
7455         if (!kvm->arch.n_requested_mmu_pages)
7456                 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7457
7458         if (nr_mmu_pages)
7459                 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7460         /*
7461          * Write protect all pages for dirty logging.
7462          *
7463          * All the sptes including the large sptes which point to this
7464          * slot are set to readonly. We can not create any new large
7465          * spte on this slot until the end of the logging.
7466          *
7467          * See the comments in fast_page_fault().
7468          */
7469         if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
7470                 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7471 }
7472
7473 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7474 {
7475         kvm_mmu_invalidate_zap_all_pages(kvm);
7476 }
7477
7478 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7479                                    struct kvm_memory_slot *slot)
7480 {
7481         kvm_mmu_invalidate_zap_all_pages(kvm);
7482 }
7483
7484 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7485 {
7486         if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7487                 kvm_x86_ops->check_nested_events(vcpu, false);
7488
7489         return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7490                 !vcpu->arch.apf.halted)
7491                 || !list_empty_careful(&vcpu->async_pf.done)
7492                 || kvm_apic_has_events(vcpu)
7493                 || vcpu->arch.pv.pv_unhalted
7494                 || atomic_read(&vcpu->arch.nmi_queued) ||
7495                 (kvm_arch_interrupt_allowed(vcpu) &&
7496                  kvm_cpu_has_interrupt(vcpu));
7497 }
7498
7499 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7500 {
7501         return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7502 }
7503
7504 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7505 {
7506         return kvm_x86_ops->interrupt_allowed(vcpu);
7507 }
7508
7509 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7510 {
7511         unsigned long current_rip = kvm_rip_read(vcpu) +
7512                 get_segment_base(vcpu, VCPU_SREG_CS);
7513
7514         return current_rip == linear_rip;
7515 }
7516 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7517
7518 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7519 {
7520         unsigned long rflags;
7521
7522         rflags = kvm_x86_ops->get_rflags(vcpu);
7523         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7524                 rflags &= ~X86_EFLAGS_TF;
7525         return rflags;
7526 }
7527 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7528
7529 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7530 {
7531         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7532             kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7533                 rflags |= X86_EFLAGS_TF;
7534         kvm_x86_ops->set_rflags(vcpu, rflags);
7535 }
7536
7537 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7538 {
7539         __kvm_set_rflags(vcpu, rflags);
7540         kvm_make_request(KVM_REQ_EVENT, vcpu);
7541 }
7542 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7543
7544 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7545 {
7546         int r;
7547
7548         if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7549               work->wakeup_all)
7550                 return;
7551
7552         r = kvm_mmu_reload(vcpu);
7553         if (unlikely(r))
7554                 return;
7555
7556         if (!vcpu->arch.mmu.direct_map &&
7557               work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7558                 return;
7559
7560         vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7561 }
7562
7563 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7564 {
7565         return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7566 }
7567
7568 static inline u32 kvm_async_pf_next_probe(u32 key)
7569 {
7570         return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7571 }
7572
7573 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7574 {
7575         u32 key = kvm_async_pf_hash_fn(gfn);
7576
7577         while (vcpu->arch.apf.gfns[key] != ~0)
7578                 key = kvm_async_pf_next_probe(key);
7579
7580         vcpu->arch.apf.gfns[key] = gfn;
7581 }
7582
7583 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7584 {
7585         int i;
7586         u32 key = kvm_async_pf_hash_fn(gfn);
7587
7588         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7589                      (vcpu->arch.apf.gfns[key] != gfn &&
7590                       vcpu->arch.apf.gfns[key] != ~0); i++)
7591                 key = kvm_async_pf_next_probe(key);
7592
7593         return key;
7594 }
7595
7596 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7597 {
7598         return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7599 }
7600
7601 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7602 {
7603         u32 i, j, k;
7604
7605         i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7606         while (true) {
7607                 vcpu->arch.apf.gfns[i] = ~0;
7608                 do {
7609                         j = kvm_async_pf_next_probe(j);
7610                         if (vcpu->arch.apf.gfns[j] == ~0)
7611                                 return;
7612                         k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7613                         /*
7614                          * k lies cyclically in ]i,j]
7615                          * |    i.k.j |
7616                          * |....j i.k.| or  |.k..j i...|
7617                          */
7618                 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7619                 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7620                 i = j;
7621         }
7622 }
7623
7624 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7625 {
7626
7627         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7628                                       sizeof(val));
7629 }
7630
7631 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7632                                      struct kvm_async_pf *work)
7633 {
7634         struct x86_exception fault;
7635
7636         trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7637         kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7638
7639         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7640             (vcpu->arch.apf.send_user_only &&
7641              kvm_x86_ops->get_cpl(vcpu) == 0))
7642                 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7643         else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7644                 fault.vector = PF_VECTOR;
7645                 fault.error_code_valid = true;
7646                 fault.error_code = 0;
7647                 fault.nested_page_fault = false;
7648                 fault.address = work->arch.token;
7649                 kvm_inject_page_fault(vcpu, &fault);
7650         }
7651 }
7652
7653 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7654                                  struct kvm_async_pf *work)
7655 {
7656         struct x86_exception fault;
7657
7658         trace_kvm_async_pf_ready(work->arch.token, work->gva);
7659         if (work->wakeup_all)
7660                 work->arch.token = ~0; /* broadcast wakeup */
7661         else
7662                 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7663
7664         if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7665             !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7666                 fault.vector = PF_VECTOR;
7667                 fault.error_code_valid = true;
7668                 fault.error_code = 0;
7669                 fault.nested_page_fault = false;
7670                 fault.address = work->arch.token;
7671                 kvm_inject_page_fault(vcpu, &fault);
7672         }
7673         vcpu->arch.apf.halted = false;
7674         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7675 }
7676
7677 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7678 {
7679         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7680                 return true;
7681         else
7682                 return !kvm_event_needs_reinjection(vcpu) &&
7683                         kvm_x86_ops->interrupt_allowed(vcpu);
7684 }
7685
7686 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7687 {
7688         atomic_inc(&kvm->arch.noncoherent_dma_count);
7689 }
7690 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7691
7692 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7693 {
7694         atomic_dec(&kvm->arch.noncoherent_dma_count);
7695 }
7696 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7697
7698 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7699 {
7700         return atomic_read(&kvm->arch.noncoherent_dma_count);
7701 }
7702 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7703
7704 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7705 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7706 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7707 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7708 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7709 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7710 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7711 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7712 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7713 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7714 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7715 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
7716 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7717 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);