drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 static const char *yesno(int v)
  50 {
  51         return v ? "yes" : "no";
  52 }
  53
  54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  55  * allocated we need to hook into the minor for release. */
  56 static int
  57 drm_add_fake_info_node(struct drm_minor *minor,
  58                        struct dentry *ent,
  59                        const void *key)
  60 {
  61         struct drm_info_node *node;
  62
  63         node = kmalloc(sizeof(*node), GFP_KERNEL);
  64         if (node == NULL) {
  65                 debugfs_remove(ent);
  66                 return -ENOMEM;
  67         }
  68
  69         node->minor = minor;
  70         node->dent = ent;
  71         node->info_ent = (void *) key;
  72
  73         mutex_lock(&minor->debugfs_lock);
  74         list_add(&node->list, &minor->debugfs_list);
  75         mutex_unlock(&minor->debugfs_lock);
  76
  77         return 0;
  78 }
  79
  80 static int i915_capabilities(struct seq_file *m, void *data)
  81 {
  82         struct drm_info_node *node = (struct drm_info_node *) m->private;
  83         struct drm_device *dev = node->minor->dev;
  84         const struct intel_device_info *info = INTEL_INFO(dev);
  85
  86         seq_printf(m, "gen: %d\n", info->gen);
  87         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  88 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  89 #define SEP_SEMICOLON ;
  90         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  91 #undef PRINT_FLAG
  92 #undef SEP_SEMICOLON
  93
  94         return 0;
  95 }
  96
  97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  98 {
  99         if (obj->user_pin_count > 0)
 100                 return "P";
 101         else if (obj->pin_count > 0)
 102                 return "p";
 103         else
 104                 return " ";
 105 }
 106
 107 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 108 {
 109         switch (obj->tiling_mode) {
 110         default:
 111         case I915_TILING_NONE: return " ";
 112         case I915_TILING_X: return "X";
 113         case I915_TILING_Y: return "Y";
 114         }
 115 }
 116
 117 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 118 {
 119         return obj->has_global_gtt_mapping ? "g" : " ";
 120 }
 121
 122 static void
 123 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 124 {
 125         struct i915_vma *vma;
 126         seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
 127                    &obj->base,
 128                    get_pin_flag(obj),
 129                    get_tiling_flag(obj),
 130                    get_global_flag(obj),
 131                    obj->base.size / 1024,
 132                    obj->base.read_domains,
 133                    obj->base.write_domain,
 134                    obj->last_read_seqno,
 135                    obj->last_write_seqno,
 136                    obj->last_fenced_seqno,
 137                    i915_cache_level_str(obj->cache_level),
 138                    obj->dirty ? " dirty" : "",
 139                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 140         if (obj->base.name)
 141                 seq_printf(m, " (name: %d)", obj->base.name);
 142         if (obj->pin_count)
 143                 seq_printf(m, " (pinned x %d)", obj->pin_count);
 144         if (obj->pin_display)
 145                 seq_printf(m, " (display)");
 146         if (obj->fence_reg != I915_FENCE_REG_NONE)
 147                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 148         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 149                 if (!i915_is_ggtt(vma->vm))
 150                         seq_puts(m, " (pp");
 151                 else
 152                         seq_puts(m, " (g");
 153                 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
 154                            vma->node.start, vma->node.size);
 155         }
 156         if (obj->stolen)
 157                 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
 158         if (obj->pin_mappable || obj->fault_mappable) {
 159                 char s[3], *t = s;
 160                 if (obj->pin_mappable)
 161                         *t++ = 'p';
 162                 if (obj->fault_mappable)
 163                         *t++ = 'f';
 164                 *t = '\0';
 165                 seq_printf(m, " (%s mappable)", s);
 166         }
 167         if (obj->ring != NULL)
 168                 seq_printf(m, " (%s)", obj->ring->name);
 169 }
 170
 171 static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
 172 {
 173         seq_putc(m, ctx->is_initialized ? 'I' : 'i');
 174         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 175         seq_putc(m, ' ');
 176 }
 177
 178 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 179 {
 180         struct drm_info_node *node = (struct drm_info_node *) m->private;
 181         uintptr_t list = (uintptr_t) node->info_ent->data;
 182         struct list_head *head;
 183         struct drm_device *dev = node->minor->dev;
 184         struct drm_i915_private *dev_priv = dev->dev_private;
 185         struct i915_address_space *vm = &dev_priv->gtt.base;
 186         struct i915_vma *vma;
 187         size_t total_obj_size, total_gtt_size;
 188         int count, ret;
 189
 190         ret = mutex_lock_interruptible(&dev->struct_mutex);
 191         if (ret)
 192                 return ret;
 193
 194         /* FIXME: the user of this interface might want more than just GGTT */
 195         switch (list) {
 196         case ACTIVE_LIST:
 197                 seq_puts(m, "Active:\n");
 198                 head = &vm->active_list;
 199                 break;
 200         case INACTIVE_LIST:
 201                 seq_puts(m, "Inactive:\n");
 202                 head = &vm->inactive_list;
 203                 break;
 204         default:
 205                 mutex_unlock(&dev->struct_mutex);
 206                 return -EINVAL;
 207         }
 208
 209         total_obj_size = total_gtt_size = count = 0;
 210         list_for_each_entry(vma, head, mm_list) {
 211                 seq_printf(m, "   ");
 212                 describe_obj(m, vma->obj);
 213                 seq_printf(m, "\n");
 214                 total_obj_size += vma->obj->base.size;
 215                 total_gtt_size += vma->node.size;
 216                 count++;
 217         }
 218         mutex_unlock(&dev->struct_mutex);
 219
 220         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 221                    count, total_obj_size, total_gtt_size);
 222         return 0;
 223 }
 224
 225 static int obj_rank_by_stolen(void *priv,
 226                               struct list_head *A, struct list_head *B)
 227 {
 228         struct drm_i915_gem_object *a =
 229                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 230         struct drm_i915_gem_object *b =
 231                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 232
 233         return a->stolen->start - b->stolen->start;
 234 }
 235
 236 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 237 {
 238         struct drm_info_node *node = (struct drm_info_node *) m->private;
 239         struct drm_device *dev = node->minor->dev;
 240         struct drm_i915_private *dev_priv = dev->dev_private;
 241         struct drm_i915_gem_object *obj;
 242         size_t total_obj_size, total_gtt_size;
 243         LIST_HEAD(stolen);
 244         int count, ret;
 245
 246         ret = mutex_lock_interruptible(&dev->struct_mutex);
 247         if (ret)
 248                 return ret;
 249
 250         total_obj_size = total_gtt_size = count = 0;
 251         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 252                 if (obj->stolen == NULL)
 253                         continue;
 254
 255                 list_add(&obj->obj_exec_link, &stolen);
 256
 257                 total_obj_size += obj->base.size;
 258                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 259                 count++;
 260         }
 261         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 262                 if (obj->stolen == NULL)
 263                         continue;
 264
 265                 list_add(&obj->obj_exec_link, &stolen);
 266
 267                 total_obj_size += obj->base.size;
 268                 count++;
 269         }
 270         list_sort(NULL, &stolen, obj_rank_by_stolen);
 271         seq_puts(m, "Stolen:\n");
 272         while (!list_empty(&stolen)) {
 273                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 274                 seq_puts(m, "   ");
 275                 describe_obj(m, obj);
 276                 seq_putc(m, '\n');
 277                 list_del_init(&obj->obj_exec_link);
 278         }
 279         mutex_unlock(&dev->struct_mutex);
 280
 281         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 282                    count, total_obj_size, total_gtt_size);
 283         return 0;
 284 }
 285
 286 #define count_objects(list, member) do { \
 287         list_for_each_entry(obj, list, member) { \
 288                 size += i915_gem_obj_ggtt_size(obj); \
 289                 ++count; \
 290                 if (obj->map_and_fenceable) { \
 291                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 292                         ++mappable_count; \
 293                 } \
 294         } \
 295 } while (0)
 296
 297 struct file_stats {
 298         int count;
 299         size_t total, active, inactive, unbound;
 300 };
 301
 302 static int per_file_stats(int id, void *ptr, void *data)
 303 {
 304         struct drm_i915_gem_object *obj = ptr;
 305         struct file_stats *stats = data;
 306
 307         stats->count++;
 308         stats->total += obj->base.size;
 309
 310         if (i915_gem_obj_ggtt_bound(obj)) {
 311                 if (!list_empty(&obj->ring_list))
 312                         stats->active += obj->base.size;
 313                 else
 314                         stats->inactive += obj->base.size;
 315         } else {
 316                 if (!list_empty(&obj->global_list))
 317                         stats->unbound += obj->base.size;
 318         }
 319
 320         return 0;
 321 }
 322
 323 #define count_vmas(list, member) do { \
 324         list_for_each_entry(vma, list, member) { \
 325                 size += i915_gem_obj_ggtt_size(vma->obj); \
 326                 ++count; \
 327                 if (vma->obj->map_and_fenceable) { \
 328                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 329                         ++mappable_count; \
 330                 } \
 331         } \
 332 } while (0)
 333
 334 static int i915_gem_object_info(struct seq_file *m, void* data)
 335 {
 336         struct drm_info_node *node = (struct drm_info_node *) m->private;
 337         struct drm_device *dev = node->minor->dev;
 338         struct drm_i915_private *dev_priv = dev->dev_private;
 339         u32 count, mappable_count, purgeable_count;
 340         size_t size, mappable_size, purgeable_size;
 341         struct drm_i915_gem_object *obj;
 342         struct i915_address_space *vm = &dev_priv->gtt.base;
 343         struct drm_file *file;
 344         struct i915_vma *vma;
 345         int ret;
 346
 347         ret = mutex_lock_interruptible(&dev->struct_mutex);
 348         if (ret)
 349                 return ret;
 350
 351         seq_printf(m, "%u objects, %zu bytes\n",
 352                    dev_priv->mm.object_count,
 353                    dev_priv->mm.object_memory);
 354
 355         size = count = mappable_size = mappable_count = 0;
 356         count_objects(&dev_priv->mm.bound_list, global_list);
 357         seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
 358                    count, mappable_count, size, mappable_size);
 359
 360         size = count = mappable_size = mappable_count = 0;
 361         count_vmas(&vm->active_list, mm_list);
 362         seq_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
 363                    count, mappable_count, size, mappable_size);
 364
 365         size = count = mappable_size = mappable_count = 0;
 366         count_vmas(&vm->inactive_list, mm_list);
 367         seq_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
 368                    count, mappable_count, size, mappable_size);
 369
 370         size = count = purgeable_size = purgeable_count = 0;
 371         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 372                 size += obj->base.size, ++count;
 373                 if (obj->madv == I915_MADV_DONTNEED)
 374                         purgeable_size += obj->base.size, ++purgeable_count;
 375         }
 376         seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
 377
 378         size = count = mappable_size = mappable_count = 0;
 379         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 380                 if (obj->fault_mappable) {
 381                         size += i915_gem_obj_ggtt_size(obj);
 382                         ++count;
 383                 }
 384                 if (obj->pin_mappable) {
 385                         mappable_size += i915_gem_obj_ggtt_size(obj);
 386                         ++mappable_count;
 387                 }
 388                 if (obj->madv == I915_MADV_DONTNEED) {
 389                         purgeable_size += obj->base.size;
 390                         ++purgeable_count;
 391                 }
 392         }
 393         seq_printf(m, "%u purgeable objects, %zu bytes\n",
 394                    purgeable_count, purgeable_size);
 395         seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
 396                    mappable_count, mappable_size);
 397         seq_printf(m, "%u fault mappable objects, %zu bytes\n",
 398                    count, size);
 399
 400         seq_printf(m, "%zu [%lu] gtt total\n",
 401                    dev_priv->gtt.base.total,
 402                    dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 403
 404         seq_putc(m, '\n');
 405         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 406                 struct file_stats stats;
 407                 struct task_struct *task;
 408
 409                 memset(&stats, 0, sizeof(stats));
 410                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 411                 /*
 412                  * Although we have a valid reference on file->pid, that does
 413                  * not guarantee that the task_struct who called get_pid() is
 414                  * still alive (e.g. get_pid(current) => fork() => exit()).
 415                  * Therefore, we need to protect this ->comm access using RCU.
 416                  */
 417                 rcu_read_lock();
 418                 task = pid_task(file->pid, PIDTYPE_PID);
 419                 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
 420                            task ? task->comm : "<unknown>",
 421                            stats.count,
 422                            stats.total,
 423                            stats.active,
 424                            stats.inactive,
 425                            stats.unbound);
 426                 rcu_read_unlock();
 427         }
 428
 429         mutex_unlock(&dev->struct_mutex);
 430
 431         return 0;
 432 }
 433
 434 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 435 {
 436         struct drm_info_node *node = (struct drm_info_node *) m->private;
 437         struct drm_device *dev = node->minor->dev;
 438         uintptr_t list = (uintptr_t) node->info_ent->data;
 439         struct drm_i915_private *dev_priv = dev->dev_private;
 440         struct drm_i915_gem_object *obj;
 441         size_t total_obj_size, total_gtt_size;
 442         int count, ret;
 443
 444         ret = mutex_lock_interruptible(&dev->struct_mutex);
 445         if (ret)
 446                 return ret;
 447
 448         total_obj_size = total_gtt_size = count = 0;
 449         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 450                 if (list == PINNED_LIST && obj->pin_count == 0)
 451                         continue;
 452
 453                 seq_puts(m, "   ");
 454                 describe_obj(m, obj);
 455                 seq_putc(m, '\n');
 456                 total_obj_size += obj->base.size;
 457                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 458                 count++;
 459         }
 460
 461         mutex_unlock(&dev->struct_mutex);
 462
 463         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 464                    count, total_obj_size, total_gtt_size);
 465
 466         return 0;
 467 }
 468
 469 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 470 {
 471         struct drm_info_node *node = (struct drm_info_node *) m->private;
 472         struct drm_device *dev = node->minor->dev;
 473         unsigned long flags;
 474         struct intel_crtc *crtc;
 475
 476         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
 477                 const char pipe = pipe_name(crtc->pipe);
 478                 const char plane = plane_name(crtc->plane);
 479                 struct intel_unpin_work *work;
 480
 481                 spin_lock_irqsave(&dev->event_lock, flags);
 482                 work = crtc->unpin_work;
 483                 if (work == NULL) {
 484                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 485                                    pipe, plane);
 486                 } else {
 487                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 488                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 489                                            pipe, plane);
 490                         } else {
 491                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 492                                            pipe, plane);
 493                         }
 494                         if (work->enable_stall_check)
 495                                 seq_puts(m, "Stall check enabled, ");
 496                         else
 497                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 498                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 499
 500                         if (work->old_fb_obj) {
 501                                 struct drm_i915_gem_object *obj = work->old_fb_obj;
 502                                 if (obj)
 503                                         seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
 504                                                    i915_gem_obj_ggtt_offset(obj));
 505                         }
 506                         if (work->pending_flip_obj) {
 507                                 struct drm_i915_gem_object *obj = work->pending_flip_obj;
 508                                 if (obj)
 509                                         seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
 510                                                    i915_gem_obj_ggtt_offset(obj));
 511                         }
 512                 }
 513                 spin_unlock_irqrestore(&dev->event_lock, flags);
 514         }
 515
 516         return 0;
 517 }
 518
 519 static int i915_gem_request_info(struct seq_file *m, void *data)
 520 {
 521         struct drm_info_node *node = (struct drm_info_node *) m->private;
 522         struct drm_device *dev = node->minor->dev;
 523         drm_i915_private_t *dev_priv = dev->dev_private;
 524         struct intel_ring_buffer *ring;
 525         struct drm_i915_gem_request *gem_request;
 526         int ret, count, i;
 527
 528         ret = mutex_lock_interruptible(&dev->struct_mutex);
 529         if (ret)
 530                 return ret;
 531
 532         count = 0;
 533         for_each_ring(ring, dev_priv, i) {
 534                 if (list_empty(&ring->request_list))
 535                         continue;
 536
 537                 seq_printf(m, "%s requests:\n", ring->name);
 538                 list_for_each_entry(gem_request,
 539                                     &ring->request_list,
 540                                     list) {
 541                         seq_printf(m, "    %d @ %d\n",
 542                                    gem_request->seqno,
 543                                    (int) (jiffies - gem_request->emitted_jiffies));
 544                 }
 545                 count++;
 546         }
 547         mutex_unlock(&dev->struct_mutex);
 548
 549         if (count == 0)
 550                 seq_puts(m, "No requests\n");
 551
 552         return 0;
 553 }
 554
 555 static void i915_ring_seqno_info(struct seq_file *m,
 556                                  struct intel_ring_buffer *ring)
 557 {
 558         if (ring->get_seqno) {
 559                 seq_printf(m, "Current sequence (%s): %u\n",
 560                            ring->name, ring->get_seqno(ring, false));
 561         }
 562 }
 563
 564 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 565 {
 566         struct drm_info_node *node = (struct drm_info_node *) m->private;
 567         struct drm_device *dev = node->minor->dev;
 568         drm_i915_private_t *dev_priv = dev->dev_private;
 569         struct intel_ring_buffer *ring;
 570         int ret, i;
 571
 572         ret = mutex_lock_interruptible(&dev->struct_mutex);
 573         if (ret)
 574                 return ret;
 575         intel_runtime_pm_get(dev_priv);
 576
 577         for_each_ring(ring, dev_priv, i)
 578                 i915_ring_seqno_info(m, ring);
 579
 580         intel_runtime_pm_put(dev_priv);
 581         mutex_unlock(&dev->struct_mutex);
 582
 583         return 0;
 584 }
 585
 586
 587 static int i915_interrupt_info(struct seq_file *m, void *data)
 588 {
 589         struct drm_info_node *node = (struct drm_info_node *) m->private;
 590         struct drm_device *dev = node->minor->dev;
 591         drm_i915_private_t *dev_priv = dev->dev_private;
 592         struct intel_ring_buffer *ring;
 593         int ret, i, pipe;
 594
 595         ret = mutex_lock_interruptible(&dev->struct_mutex);
 596         if (ret)
 597                 return ret;
 598         intel_runtime_pm_get(dev_priv);
 599
 600         if (INTEL_INFO(dev)->gen >= 8) {
 601                 int i;
 602                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 603                            I915_READ(GEN8_MASTER_IRQ));
 604
 605                 for (i = 0; i < 4; i++) {
 606                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 607                                    i, I915_READ(GEN8_GT_IMR(i)));
 608                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 609                                    i, I915_READ(GEN8_GT_IIR(i)));
 610                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 611                                    i, I915_READ(GEN8_GT_IER(i)));
 612                 }
 613
 614                 for_each_pipe(i) {
 615                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 616                                    pipe_name(i),
 617                                    I915_READ(GEN8_DE_PIPE_IMR(i)));
 618                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 619                                    pipe_name(i),
 620                                    I915_READ(GEN8_DE_PIPE_IIR(i)));
 621                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 622                                    pipe_name(i),
 623                                    I915_READ(GEN8_DE_PIPE_IER(i)));
 624                 }
 625
 626                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 627                            I915_READ(GEN8_DE_PORT_IMR));
 628                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 629                            I915_READ(GEN8_DE_PORT_IIR));
 630                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 631                            I915_READ(GEN8_DE_PORT_IER));
 632
 633                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 634                            I915_READ(GEN8_DE_MISC_IMR));
 635                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 636                            I915_READ(GEN8_DE_MISC_IIR));
 637                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 638                            I915_READ(GEN8_DE_MISC_IER));
 639
 640                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 641                            I915_READ(GEN8_PCU_IMR));
 642                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 643                            I915_READ(GEN8_PCU_IIR));
 644                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 645                            I915_READ(GEN8_PCU_IER));
 646         } else if (IS_VALLEYVIEW(dev)) {
 647                 seq_printf(m, "Display IER:\t%08x\n",
 648                            I915_READ(VLV_IER));
 649                 seq_printf(m, "Display IIR:\t%08x\n",
 650                            I915_READ(VLV_IIR));
 651                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 652                            I915_READ(VLV_IIR_RW));
 653                 seq_printf(m, "Display IMR:\t%08x\n",
 654                            I915_READ(VLV_IMR));
 655                 for_each_pipe(pipe)
 656                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 657                                    pipe_name(pipe),
 658                                    I915_READ(PIPESTAT(pipe)));
 659
 660                 seq_printf(m, "Master IER:\t%08x\n",
 661                            I915_READ(VLV_MASTER_IER));
 662
 663                 seq_printf(m, "Render IER:\t%08x\n",
 664                            I915_READ(GTIER));
 665                 seq_printf(m, "Render IIR:\t%08x\n",
 666                            I915_READ(GTIIR));
 667                 seq_printf(m, "Render IMR:\t%08x\n",
 668                            I915_READ(GTIMR));
 669
 670                 seq_printf(m, "PM IER:\t\t%08x\n",
 671                            I915_READ(GEN6_PMIER));
 672                 seq_printf(m, "PM IIR:\t\t%08x\n",
 673                            I915_READ(GEN6_PMIIR));
 674                 seq_printf(m, "PM IMR:\t\t%08x\n",
 675                            I915_READ(GEN6_PMIMR));
 676
 677                 seq_printf(m, "Port hotplug:\t%08x\n",
 678                            I915_READ(PORT_HOTPLUG_EN));
 679                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 680                            I915_READ(VLV_DPFLIPSTAT));
 681                 seq_printf(m, "DPINVGTT:\t%08x\n",
 682                            I915_READ(DPINVGTT));
 683
 684         } else if (!HAS_PCH_SPLIT(dev)) {
 685                 seq_printf(m, "Interrupt enable:    %08x\n",
 686                            I915_READ(IER));
 687                 seq_printf(m, "Interrupt identity:  %08x\n",
 688                            I915_READ(IIR));
 689                 seq_printf(m, "Interrupt mask:      %08x\n",
 690                            I915_READ(IMR));
 691                 for_each_pipe(pipe)
 692                         seq_printf(m, "Pipe %c stat:         %08x\n",
 693                                    pipe_name(pipe),
 694                                    I915_READ(PIPESTAT(pipe)));
 695         } else {
 696                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 697                            I915_READ(DEIER));
 698                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 699                            I915_READ(DEIIR));
 700                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 701                            I915_READ(DEIMR));
 702                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 703                            I915_READ(SDEIER));
 704                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 705                            I915_READ(SDEIIR));
 706                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 707                            I915_READ(SDEIMR));
 708                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 709                            I915_READ(GTIER));
 710                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 711                            I915_READ(GTIIR));
 712                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 713                            I915_READ(GTIMR));
 714         }
 715         seq_printf(m, "Interrupts received: %d\n",
 716                    atomic_read(&dev_priv->irq_received));
 717         for_each_ring(ring, dev_priv, i) {
 718                 if (INTEL_INFO(dev)->gen >= 6) {
 719                         seq_printf(m,
 720                                    "Graphics Interrupt mask (%s):       %08x\n",
 721                                    ring->name, I915_READ_IMR(ring));
 722                 }
 723                 i915_ring_seqno_info(m, ring);
 724         }
 725         intel_runtime_pm_put(dev_priv);
 726         mutex_unlock(&dev->struct_mutex);
 727
 728         return 0;
 729 }
 730
 731 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 732 {
 733         struct drm_info_node *node = (struct drm_info_node *) m->private;
 734         struct drm_device *dev = node->minor->dev;
 735         drm_i915_private_t *dev_priv = dev->dev_private;
 736         int i, ret;
 737
 738         ret = mutex_lock_interruptible(&dev->struct_mutex);
 739         if (ret)
 740                 return ret;
 741
 742         seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 743         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 744         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 745                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 746
 747                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 748                            i, dev_priv->fence_regs[i].pin_count);
 749                 if (obj == NULL)
 750                         seq_puts(m, "unused");
 751                 else
 752                         describe_obj(m, obj);
 753                 seq_putc(m, '\n');
 754         }
 755
 756         mutex_unlock(&dev->struct_mutex);
 757         return 0;
 758 }
 759
 760 static int i915_hws_info(struct seq_file *m, void *data)
 761 {
 762         struct drm_info_node *node = (struct drm_info_node *) m->private;
 763         struct drm_device *dev = node->minor->dev;
 764         drm_i915_private_t *dev_priv = dev->dev_private;
 765         struct intel_ring_buffer *ring;
 766         const u32 *hws;
 767         int i;
 768
 769         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 770         hws = ring->status_page.page_addr;
 771         if (hws == NULL)
 772                 return 0;
 773
 774         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 775                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 776                            i * 4,
 777                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 778         }
 779         return 0;
 780 }
 781
 782 static ssize_t
 783 i915_error_state_write(struct file *filp,
 784                        const char __user *ubuf,
 785                        size_t cnt,
 786                        loff_t *ppos)
 787 {
 788         struct i915_error_state_file_priv *error_priv = filp->private_data;
 789         struct drm_device *dev = error_priv->dev;
 790         int ret;
 791
 792         DRM_DEBUG_DRIVER("Resetting error state\n");
 793
 794         ret = mutex_lock_interruptible(&dev->struct_mutex);
 795         if (ret)
 796                 return ret;
 797
 798         i915_destroy_error_state(dev);
 799         mutex_unlock(&dev->struct_mutex);
 800
 801         return cnt;
 802 }
 803
 804 static int i915_error_state_open(struct inode *inode, struct file *file)
 805 {
 806         struct drm_device *dev = inode->i_private;
 807         struct i915_error_state_file_priv *error_priv;
 808
 809         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 810         if (!error_priv)
 811                 return -ENOMEM;
 812
 813         error_priv->dev = dev;
 814
 815         i915_error_state_get(dev, error_priv);
 816
 817         file->private_data = error_priv;
 818
 819         return 0;
 820 }
 821
 822 static int i915_error_state_release(struct inode *inode, struct file *file)
 823 {
 824         struct i915_error_state_file_priv *error_priv = file->private_data;
 825
 826         i915_error_state_put(error_priv);
 827         kfree(error_priv);
 828
 829         return 0;
 830 }
 831
 832 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
 833                                      size_t count, loff_t *pos)
 834 {
 835         struct i915_error_state_file_priv *error_priv = file->private_data;
 836         struct drm_i915_error_state_buf error_str;
 837         loff_t tmp_pos = 0;
 838         ssize_t ret_count = 0;
 839         int ret;
 840
 841         ret = i915_error_state_buf_init(&error_str, count, *pos);
 842         if (ret)
 843                 return ret;
 844
 845         ret = i915_error_state_to_str(&error_str, error_priv);
 846         if (ret)
 847                 goto out;
 848
 849         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
 850                                             error_str.buf,
 851                                             error_str.bytes);
 852
 853         if (ret_count < 0)
 854                 ret = ret_count;
 855         else
 856                 *pos = error_str.start + ret_count;
 857 out:
 858         i915_error_state_buf_release(&error_str);
 859         return ret ?: ret_count;
 860 }
 861
 862 static const struct file_operations i915_error_state_fops = {
 863         .owner = THIS_MODULE,
 864         .open = i915_error_state_open,
 865         .read = i915_error_state_read,
 866         .write = i915_error_state_write,
 867         .llseek = default_llseek,
 868         .release = i915_error_state_release,
 869 };
 870
 871 static int
 872 i915_next_seqno_get(void *data, u64 *val)
 873 {
 874         struct drm_device *dev = data;
 875         drm_i915_private_t *dev_priv = dev->dev_private;
 876         int ret;
 877
 878         ret = mutex_lock_interruptible(&dev->struct_mutex);
 879         if (ret)
 880                 return ret;
 881
 882         *val = dev_priv->next_seqno;
 883         mutex_unlock(&dev->struct_mutex);
 884
 885         return 0;
 886 }
 887
 888 static int
 889 i915_next_seqno_set(void *data, u64 val)
 890 {
 891         struct drm_device *dev = data;
 892         int ret;
 893
 894         ret = mutex_lock_interruptible(&dev->struct_mutex);
 895         if (ret)
 896                 return ret;
 897
 898         ret = i915_gem_set_seqno(dev, val);
 899         mutex_unlock(&dev->struct_mutex);
 900
 901         return ret;
 902 }
 903
 904 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
 905                         i915_next_seqno_get, i915_next_seqno_set,
 906                         "0x%llx\n");
 907
 908 static int i915_rstdby_delays(struct seq_file *m, void *unused)
 909 {
 910         struct drm_info_node *node = (struct drm_info_node *) m->private;
 911         struct drm_device *dev = node->minor->dev;
 912         drm_i915_private_t *dev_priv = dev->dev_private;
 913         u16 crstanddelay;
 914         int ret;
 915
 916         ret = mutex_lock_interruptible(&dev->struct_mutex);
 917         if (ret)
 918                 return ret;
 919         intel_runtime_pm_get(dev_priv);
 920
 921         crstanddelay = I915_READ16(CRSTANDVID);
 922
 923         intel_runtime_pm_put(dev_priv);
 924         mutex_unlock(&dev->struct_mutex);
 925
 926         seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
 927
 928         return 0;
 929 }
 930
 931 static int i915_cur_delayinfo(struct seq_file *m, void *unused)
 932 {
 933         struct drm_info_node *node = (struct drm_info_node *) m->private;
 934         struct drm_device *dev = node->minor->dev;
 935         drm_i915_private_t *dev_priv = dev->dev_private;
 936         int ret = 0;
 937
 938         intel_runtime_pm_get(dev_priv);
 939
 940         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
 941
 942         if (IS_GEN5(dev)) {
 943                 u16 rgvswctl = I915_READ16(MEMSWCTL);
 944                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
 945
 946                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
 947                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
 948                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
 949                            MEMSTAT_VID_SHIFT);
 950                 seq_printf(m, "Current P-state: %d\n",
 951                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
 952         } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
 953                 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
 954                 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
 955                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 956                 u32 rpstat, cagf, reqf;
 957                 u32 rpupei, rpcurup, rpprevup;
 958                 u32 rpdownei, rpcurdown, rpprevdown;
 959                 int max_freq;
 960
 961                 /* RPSTAT1 is in the GT power well */
 962                 ret = mutex_lock_interruptible(&dev->struct_mutex);
 963                 if (ret)
 964                         goto out;
 965
 966                 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 967
 968                 reqf = I915_READ(GEN6_RPNSWREQ);
 969                 reqf &= ~GEN6_TURBO_DISABLE;
 970                 if (IS_HASWELL(dev))
 971                         reqf >>= 24;
 972                 else
 973                         reqf >>= 25;
 974                 reqf *= GT_FREQUENCY_MULTIPLIER;
 975
 976                 rpstat = I915_READ(GEN6_RPSTAT1);
 977                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
 978                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
 979                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
 980                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
 981                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
 982                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
 983                 if (IS_HASWELL(dev))
 984                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
 985                 else
 986                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
 987                 cagf *= GT_FREQUENCY_MULTIPLIER;
 988
 989                 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 990                 mutex_unlock(&dev->struct_mutex);
 991
 992                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 993                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
 994                 seq_printf(m, "Render p-state ratio: %d\n",
 995                            (gt_perf_status & 0xff00) >> 8);
 996                 seq_printf(m, "Render p-state VID: %d\n",
 997                            gt_perf_status & 0xff);
 998                 seq_printf(m, "Render p-state limit: %d\n",
 999                            rp_state_limits & 0xff);
1000                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1001                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1002                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1003                            GEN6_CURICONT_MASK);
1004                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1005                            GEN6_CURBSYTAVG_MASK);
1006                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1007                            GEN6_CURBSYTAVG_MASK);
1008                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1009                            GEN6_CURIAVG_MASK);
1010                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1011                            GEN6_CURBSYTAVG_MASK);
1012                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1013                            GEN6_CURBSYTAVG_MASK);
1014
1015                 max_freq = (rp_state_cap & 0xff0000) >> 16;
1016                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1017                            max_freq * GT_FREQUENCY_MULTIPLIER);
1018
1019                 max_freq = (rp_state_cap & 0xff00) >> 8;
1020                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1021                            max_freq * GT_FREQUENCY_MULTIPLIER);
1022
1023                 max_freq = rp_state_cap & 0xff;
1024                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1025                            max_freq * GT_FREQUENCY_MULTIPLIER);
1026
1027                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1028                            dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
1029         } else if (IS_VALLEYVIEW(dev)) {
1030                 u32 freq_sts, val;
1031
1032                 mutex_lock(&dev_priv->rps.hw_lock);
1033                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1034                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1035                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1036
1037                 val = valleyview_rps_max_freq(dev_priv);
1038                 seq_printf(m, "max GPU freq: %d MHz\n",
1039                            vlv_gpu_freq(dev_priv, val));
1040
1041                 val = valleyview_rps_min_freq(dev_priv);
1042                 seq_printf(m, "min GPU freq: %d MHz\n",
1043                            vlv_gpu_freq(dev_priv, val));
1044
1045                 seq_printf(m, "current GPU freq: %d MHz\n",
1046                            vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1047                 mutex_unlock(&dev_priv->rps.hw_lock);
1048         } else {
1049                 seq_puts(m, "no P-state info available\n");
1050         }
1051
1052 out:
1053         intel_runtime_pm_put(dev_priv);
1054         return ret;
1055 }
1056
1057 static int i915_delayfreq_table(struct seq_file *m, void *unused)
1058 {
1059         struct drm_info_node *node = (struct drm_info_node *) m->private;
1060         struct drm_device *dev = node->minor->dev;
1061         drm_i915_private_t *dev_priv = dev->dev_private;
1062         u32 delayfreq;
1063         int ret, i;
1064
1065         ret = mutex_lock_interruptible(&dev->struct_mutex);
1066         if (ret)
1067                 return ret;
1068         intel_runtime_pm_get(dev_priv);
1069
1070         for (i = 0; i < 16; i++) {
1071                 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
1072                 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1073                            (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
1074         }
1075
1076         intel_runtime_pm_put(dev_priv);
1077
1078         mutex_unlock(&dev->struct_mutex);
1079
1080         return 0;
1081 }
1082
1083 static inline int MAP_TO_MV(int map)
1084 {
1085         return 1250 - (map * 25);
1086 }
1087
1088 static int i915_inttoext_table(struct seq_file *m, void *unused)
1089 {
1090         struct drm_info_node *node = (struct drm_info_node *) m->private;
1091         struct drm_device *dev = node->minor->dev;
1092         drm_i915_private_t *dev_priv = dev->dev_private;
1093         u32 inttoext;
1094         int ret, i;
1095
1096         ret = mutex_lock_interruptible(&dev->struct_mutex);
1097         if (ret)
1098                 return ret;
1099         intel_runtime_pm_get(dev_priv);
1100
1101         for (i = 1; i <= 32; i++) {
1102                 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1103                 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1104         }
1105
1106         intel_runtime_pm_put(dev_priv);
1107         mutex_unlock(&dev->struct_mutex);
1108
1109         return 0;
1110 }
1111
1112 static int ironlake_drpc_info(struct seq_file *m)
1113 {
1114         struct drm_info_node *node = (struct drm_info_node *) m->private;
1115         struct drm_device *dev = node->minor->dev;
1116         drm_i915_private_t *dev_priv = dev->dev_private;
1117         u32 rgvmodectl, rstdbyctl;
1118         u16 crstandvid;
1119         int ret;
1120
1121         ret = mutex_lock_interruptible(&dev->struct_mutex);
1122         if (ret)
1123                 return ret;
1124         intel_runtime_pm_get(dev_priv);
1125
1126         rgvmodectl = I915_READ(MEMMODECTL);
1127         rstdbyctl = I915_READ(RSTDBYCTL);
1128         crstandvid = I915_READ16(CRSTANDVID);
1129
1130         intel_runtime_pm_put(dev_priv);
1131         mutex_unlock(&dev->struct_mutex);
1132
1133         seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1134                    "yes" : "no");
1135         seq_printf(m, "Boost freq: %d\n",
1136                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1137                    MEMMODE_BOOST_FREQ_SHIFT);
1138         seq_printf(m, "HW control enabled: %s\n",
1139                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1140         seq_printf(m, "SW control enabled: %s\n",
1141                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1142         seq_printf(m, "Gated voltage change: %s\n",
1143                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1144         seq_printf(m, "Starting frequency: P%d\n",
1145                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1146         seq_printf(m, "Max P-state: P%d\n",
1147                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1148         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1149         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1150         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1151         seq_printf(m, "Render standby enabled: %s\n",
1152                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1153         seq_puts(m, "Current RS state: ");
1154         switch (rstdbyctl & RSX_STATUS_MASK) {
1155         case RSX_STATUS_ON:
1156                 seq_puts(m, "on\n");
1157                 break;
1158         case RSX_STATUS_RC1:
1159                 seq_puts(m, "RC1\n");
1160                 break;
1161         case RSX_STATUS_RC1E:
1162                 seq_puts(m, "RC1E\n");
1163                 break;
1164         case RSX_STATUS_RS1:
1165                 seq_puts(m, "RS1\n");
1166                 break;
1167         case RSX_STATUS_RS2:
1168                 seq_puts(m, "RS2 (RC6)\n");
1169                 break;
1170         case RSX_STATUS_RS3:
1171                 seq_puts(m, "RC3 (RC6+)\n");
1172                 break;
1173         default:
1174                 seq_puts(m, "unknown\n");
1175                 break;
1176         }
1177
1178         return 0;
1179 }
1180
1181 static int gen6_drpc_info(struct seq_file *m)
1182 {
1183
1184         struct drm_info_node *node = (struct drm_info_node *) m->private;
1185         struct drm_device *dev = node->minor->dev;
1186         struct drm_i915_private *dev_priv = dev->dev_private;
1187         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1188         unsigned forcewake_count;
1189         int count = 0, ret;
1190
1191         ret = mutex_lock_interruptible(&dev->struct_mutex);
1192         if (ret)
1193                 return ret;
1194         intel_runtime_pm_get(dev_priv);
1195
1196         spin_lock_irq(&dev_priv->uncore.lock);
1197         forcewake_count = dev_priv->uncore.forcewake_count;
1198         spin_unlock_irq(&dev_priv->uncore.lock);
1199
1200         if (forcewake_count) {
1201                 seq_puts(m, "RC information inaccurate because somebody "
1202                             "holds a forcewake reference \n");
1203         } else {
1204                 /* NB: we cannot use forcewake, else we read the wrong values */
1205                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1206                         udelay(10);
1207                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1208         }
1209
1210         gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1211         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1212
1213         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1214         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1215         mutex_unlock(&dev->struct_mutex);
1216         mutex_lock(&dev_priv->rps.hw_lock);
1217         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1218         mutex_unlock(&dev_priv->rps.hw_lock);
1219
1220         intel_runtime_pm_put(dev_priv);
1221
1222         seq_printf(m, "Video Turbo Mode: %s\n",
1223                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1224         seq_printf(m, "HW control enabled: %s\n",
1225                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1226         seq_printf(m, "SW control enabled: %s\n",
1227                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1228                           GEN6_RP_MEDIA_SW_MODE));
1229         seq_printf(m, "RC1e Enabled: %s\n",
1230                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1231         seq_printf(m, "RC6 Enabled: %s\n",
1232                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1233         seq_printf(m, "Deep RC6 Enabled: %s\n",
1234                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1235         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1236                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1237         seq_puts(m, "Current RC state: ");
1238         switch (gt_core_status & GEN6_RCn_MASK) {
1239         case GEN6_RC0:
1240                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1241                         seq_puts(m, "Core Power Down\n");
1242                 else
1243                         seq_puts(m, "on\n");
1244                 break;
1245         case GEN6_RC3:
1246                 seq_puts(m, "RC3\n");
1247                 break;
1248         case GEN6_RC6:
1249                 seq_puts(m, "RC6\n");
1250                 break;
1251         case GEN6_RC7:
1252                 seq_puts(m, "RC7\n");
1253                 break;
1254         default:
1255                 seq_puts(m, "Unknown\n");
1256                 break;
1257         }
1258
1259         seq_printf(m, "Core Power Down: %s\n",
1260                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1261
1262         /* Not exactly sure what this is */
1263         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1264                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1265         seq_printf(m, "RC6 residency since boot: %u\n",
1266                    I915_READ(GEN6_GT_GFX_RC6));
1267         seq_printf(m, "RC6+ residency since boot: %u\n",
1268                    I915_READ(GEN6_GT_GFX_RC6p));
1269         seq_printf(m, "RC6++ residency since boot: %u\n",
1270                    I915_READ(GEN6_GT_GFX_RC6pp));
1271
1272         seq_printf(m, "RC6   voltage: %dmV\n",
1273                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1274         seq_printf(m, "RC6+  voltage: %dmV\n",
1275                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1276         seq_printf(m, "RC6++ voltage: %dmV\n",
1277                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1278         return 0;
1279 }
1280
1281 static int i915_drpc_info(struct seq_file *m, void *unused)
1282 {
1283         struct drm_info_node *node = (struct drm_info_node *) m->private;
1284         struct drm_device *dev = node->minor->dev;
1285
1286         if (IS_GEN6(dev) || IS_GEN7(dev))
1287                 return gen6_drpc_info(m);
1288         else
1289                 return ironlake_drpc_info(m);
1290 }
1291
1292 static int i915_fbc_status(struct seq_file *m, void *unused)
1293 {
1294         struct drm_info_node *node = (struct drm_info_node *) m->private;
1295         struct drm_device *dev = node->minor->dev;
1296         drm_i915_private_t *dev_priv = dev->dev_private;
1297
1298         if (!I915_HAS_FBC(dev)) {
1299                 seq_puts(m, "FBC unsupported on this chipset\n");
1300                 return 0;
1301         }
1302
1303         if (intel_fbc_enabled(dev)) {
1304                 seq_puts(m, "FBC enabled\n");
1305         } else {
1306                 seq_puts(m, "FBC disabled: ");
1307                 switch (dev_priv->fbc.no_fbc_reason) {
1308                 case FBC_OK:
1309                         seq_puts(m, "FBC actived, but currently disabled in hardware");
1310                         break;
1311                 case FBC_UNSUPPORTED:
1312                         seq_puts(m, "unsupported by this chipset");
1313                         break;
1314                 case FBC_NO_OUTPUT:
1315                         seq_puts(m, "no outputs");
1316                         break;
1317                 case FBC_STOLEN_TOO_SMALL:
1318                         seq_puts(m, "not enough stolen memory");
1319                         break;
1320                 case FBC_UNSUPPORTED_MODE:
1321                         seq_puts(m, "mode not supported");
1322                         break;
1323                 case FBC_MODE_TOO_LARGE:
1324                         seq_puts(m, "mode too large");
1325                         break;
1326                 case FBC_BAD_PLANE:
1327                         seq_puts(m, "FBC unsupported on plane");
1328                         break;
1329                 case FBC_NOT_TILED:
1330                         seq_puts(m, "scanout buffer not tiled");
1331                         break;
1332                 case FBC_MULTIPLE_PIPES:
1333                         seq_puts(m, "multiple pipes are enabled");
1334                         break;
1335                 case FBC_MODULE_PARAM:
1336                         seq_puts(m, "disabled per module param (default off)");
1337                         break;
1338                 case FBC_CHIP_DEFAULT:
1339                         seq_puts(m, "disabled per chip default");
1340                         break;
1341                 default:
1342                         seq_puts(m, "unknown reason");
1343                 }
1344                 seq_putc(m, '\n');
1345         }
1346         return 0;
1347 }
1348
1349 static int i915_ips_status(struct seq_file *m, void *unused)
1350 {
1351         struct drm_info_node *node = (struct drm_info_node *) m->private;
1352         struct drm_device *dev = node->minor->dev;
1353         struct drm_i915_private *dev_priv = dev->dev_private;
1354
1355         if (!HAS_IPS(dev)) {
1356                 seq_puts(m, "not supported\n");
1357                 return 0;
1358         }
1359
1360         if (I915_READ(IPS_CTL) & IPS_ENABLE)
1361                 seq_puts(m, "enabled\n");
1362         else
1363                 seq_puts(m, "disabled\n");
1364
1365         return 0;
1366 }
1367
1368 static int i915_sr_status(struct seq_file *m, void *unused)
1369 {
1370         struct drm_info_node *node = (struct drm_info_node *) m->private;
1371         struct drm_device *dev = node->minor->dev;
1372         drm_i915_private_t *dev_priv = dev->dev_private;
1373         bool sr_enabled = false;
1374
1375         if (HAS_PCH_SPLIT(dev))
1376                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1377         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1378                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1379         else if (IS_I915GM(dev))
1380                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1381         else if (IS_PINEVIEW(dev))
1382                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1383
1384         seq_printf(m, "self-refresh: %s\n",
1385                    sr_enabled ? "enabled" : "disabled");
1386
1387         return 0;
1388 }
1389
1390 static int i915_emon_status(struct seq_file *m, void *unused)
1391 {
1392         struct drm_info_node *node = (struct drm_info_node *) m->private;
1393         struct drm_device *dev = node->minor->dev;
1394         drm_i915_private_t *dev_priv = dev->dev_private;
1395         unsigned long temp, chipset, gfx;
1396         int ret;
1397
1398         if (!IS_GEN5(dev))
1399                 return -ENODEV;
1400
1401         ret = mutex_lock_interruptible(&dev->struct_mutex);
1402         if (ret)
1403                 return ret;
1404
1405         temp = i915_mch_val(dev_priv);
1406         chipset = i915_chipset_val(dev_priv);
1407         gfx = i915_gfx_val(dev_priv);
1408         mutex_unlock(&dev->struct_mutex);
1409
1410         seq_printf(m, "GMCH temp: %ld\n", temp);
1411         seq_printf(m, "Chipset power: %ld\n", chipset);
1412         seq_printf(m, "GFX power: %ld\n", gfx);
1413         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1414
1415         return 0;
1416 }
1417
1418 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1419 {
1420         struct drm_info_node *node = (struct drm_info_node *) m->private;
1421         struct drm_device *dev = node->minor->dev;
1422         drm_i915_private_t *dev_priv = dev->dev_private;
1423         int ret;
1424         int gpu_freq, ia_freq;
1425
1426         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1427                 seq_puts(m, "unsupported on this chipset\n");
1428                 return 0;
1429         }
1430
1431         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1432
1433         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1434         if (ret)
1435                 return ret;
1436         intel_runtime_pm_get(dev_priv);
1437
1438         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1439
1440         for (gpu_freq = dev_priv->rps.min_delay;
1441              gpu_freq <= dev_priv->rps.max_delay;
1442              gpu_freq++) {
1443                 ia_freq = gpu_freq;
1444                 sandybridge_pcode_read(dev_priv,
1445                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1446                                        &ia_freq);
1447                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1448                            gpu_freq * GT_FREQUENCY_MULTIPLIER,
1449                            ((ia_freq >> 0) & 0xff) * 100,
1450                            ((ia_freq >> 8) & 0xff) * 100);
1451         }
1452
1453         intel_runtime_pm_put(dev_priv);
1454         mutex_unlock(&dev_priv->rps.hw_lock);
1455
1456         return 0;
1457 }
1458
1459 static int i915_gfxec(struct seq_file *m, void *unused)
1460 {
1461         struct drm_info_node *node = (struct drm_info_node *) m->private;
1462         struct drm_device *dev = node->minor->dev;
1463         drm_i915_private_t *dev_priv = dev->dev_private;
1464         int ret;
1465
1466         ret = mutex_lock_interruptible(&dev->struct_mutex);
1467         if (ret)
1468                 return ret;
1469         intel_runtime_pm_get(dev_priv);
1470
1471         seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1472         intel_runtime_pm_put(dev_priv);
1473
1474         mutex_unlock(&dev->struct_mutex);
1475
1476         return 0;
1477 }
1478
1479 static int i915_opregion(struct seq_file *m, void *unused)
1480 {
1481         struct drm_info_node *node = (struct drm_info_node *) m->private;
1482         struct drm_device *dev = node->minor->dev;
1483         drm_i915_private_t *dev_priv = dev->dev_private;
1484         struct intel_opregion *opregion = &dev_priv->opregion;
1485         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1486         int ret;
1487
1488         if (data == NULL)
1489                 return -ENOMEM;
1490
1491         ret = mutex_lock_interruptible(&dev->struct_mutex);
1492         if (ret)
1493                 goto out;
1494
1495         if (opregion->header) {
1496                 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1497                 seq_write(m, data, OPREGION_SIZE);
1498         }
1499
1500         mutex_unlock(&dev->struct_mutex);
1501
1502 out:
1503         kfree(data);
1504         return 0;
1505 }
1506
1507 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1508 {
1509         struct drm_info_node *node = (struct drm_info_node *) m->private;
1510         struct drm_device *dev = node->minor->dev;
1511         struct intel_fbdev *ifbdev = NULL;
1512         struct intel_framebuffer *fb;
1513
1514 #ifdef CONFIG_DRM_I915_FBDEV
1515         struct drm_i915_private *dev_priv = dev->dev_private;
1516         int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1517         if (ret)
1518                 return ret;
1519
1520         ifbdev = dev_priv->fbdev;
1521         fb = to_intel_framebuffer(ifbdev->helper.fb);
1522
1523         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1524                    fb->base.width,
1525                    fb->base.height,
1526                    fb->base.depth,
1527                    fb->base.bits_per_pixel,
1528                    atomic_read(&fb->base.refcount.refcount));
1529         describe_obj(m, fb->obj);
1530         seq_putc(m, '\n');
1531         mutex_unlock(&dev->mode_config.mutex);
1532 #endif
1533
1534         mutex_lock(&dev->mode_config.fb_lock);
1535         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1536                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1537                         continue;
1538
1539                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1540                            fb->base.width,
1541                            fb->base.height,
1542                            fb->base.depth,
1543                            fb->base.bits_per_pixel,
1544                            atomic_read(&fb->base.refcount.refcount));
1545                 describe_obj(m, fb->obj);
1546                 seq_putc(m, '\n');
1547         }
1548         mutex_unlock(&dev->mode_config.fb_lock);
1549
1550         return 0;
1551 }
1552
1553 static int i915_context_status(struct seq_file *m, void *unused)
1554 {
1555         struct drm_info_node *node = (struct drm_info_node *) m->private;
1556         struct drm_device *dev = node->minor->dev;
1557         drm_i915_private_t *dev_priv = dev->dev_private;
1558         struct intel_ring_buffer *ring;
1559         struct i915_hw_context *ctx;
1560         int ret, i;
1561
1562         ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1563         if (ret)
1564                 return ret;
1565
1566         if (dev_priv->ips.pwrctx) {
1567                 seq_puts(m, "power context ");
1568                 describe_obj(m, dev_priv->ips.pwrctx);
1569                 seq_putc(m, '\n');
1570         }
1571
1572         if (dev_priv->ips.renderctx) {
1573                 seq_puts(m, "render context ");
1574                 describe_obj(m, dev_priv->ips.renderctx);
1575                 seq_putc(m, '\n');
1576         }
1577
1578         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1579                 seq_puts(m, "HW context ");
1580                 describe_ctx(m, ctx);
1581                 for_each_ring(ring, dev_priv, i)
1582                         if (ring->default_context == ctx)
1583                                 seq_printf(m, "(default context %s) ", ring->name);
1584
1585                 describe_obj(m, ctx->obj);
1586                 seq_putc(m, '\n');
1587         }
1588
1589         mutex_unlock(&dev->mode_config.mutex);
1590
1591         return 0;
1592 }
1593
1594 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1595 {
1596         struct drm_info_node *node = (struct drm_info_node *) m->private;
1597         struct drm_device *dev = node->minor->dev;
1598         struct drm_i915_private *dev_priv = dev->dev_private;
1599         unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1600
1601         spin_lock_irq(&dev_priv->uncore.lock);
1602         if (IS_VALLEYVIEW(dev)) {
1603                 fw_rendercount = dev_priv->uncore.fw_rendercount;
1604                 fw_mediacount = dev_priv->uncore.fw_mediacount;
1605         } else
1606                 forcewake_count = dev_priv->uncore.forcewake_count;
1607         spin_unlock_irq(&dev_priv->uncore.lock);
1608
1609         if (IS_VALLEYVIEW(dev)) {
1610                 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1611                 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1612         } else
1613                 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1614
1615         return 0;
1616 }
1617
1618 static const char *swizzle_string(unsigned swizzle)
1619 {
1620         switch (swizzle) {
1621         case I915_BIT_6_SWIZZLE_NONE:
1622                 return "none";
1623         case I915_BIT_6_SWIZZLE_9:
1624                 return "bit9";
1625         case I915_BIT_6_SWIZZLE_9_10:
1626                 return "bit9/bit10";
1627         case I915_BIT_6_SWIZZLE_9_11:
1628                 return "bit9/bit11";
1629         case I915_BIT_6_SWIZZLE_9_10_11:
1630                 return "bit9/bit10/bit11";
1631         case I915_BIT_6_SWIZZLE_9_17:
1632                 return "bit9/bit17";
1633         case I915_BIT_6_SWIZZLE_9_10_17:
1634                 return "bit9/bit10/bit17";
1635         case I915_BIT_6_SWIZZLE_UNKNOWN:
1636                 return "unknown";
1637         }
1638
1639         return "bug";
1640 }
1641
1642 static int i915_swizzle_info(struct seq_file *m, void *data)
1643 {
1644         struct drm_info_node *node = (struct drm_info_node *) m->private;
1645         struct drm_device *dev = node->minor->dev;
1646         struct drm_i915_private *dev_priv = dev->dev_private;
1647         int ret;
1648
1649         ret = mutex_lock_interruptible(&dev->struct_mutex);
1650         if (ret)
1651                 return ret;
1652         intel_runtime_pm_get(dev_priv);
1653
1654         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1655                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1656         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1657                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1658
1659         if (IS_GEN3(dev) || IS_GEN4(dev)) {
1660                 seq_printf(m, "DDC = 0x%08x\n",
1661                            I915_READ(DCC));
1662                 seq_printf(m, "C0DRB3 = 0x%04x\n",
1663                            I915_READ16(C0DRB3));
1664                 seq_printf(m, "C1DRB3 = 0x%04x\n",
1665                            I915_READ16(C1DRB3));
1666         } else if (INTEL_INFO(dev)->gen >= 6) {
1667                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1668                            I915_READ(MAD_DIMM_C0));
1669                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1670                            I915_READ(MAD_DIMM_C1));
1671                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1672                            I915_READ(MAD_DIMM_C2));
1673                 seq_printf(m, "TILECTL = 0x%08x\n",
1674                            I915_READ(TILECTL));
1675                 if (IS_GEN8(dev))
1676                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1677                                    I915_READ(GAMTARBMODE));
1678                 else
1679                         seq_printf(m, "ARB_MODE = 0x%08x\n",
1680                                    I915_READ(ARB_MODE));
1681                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1682                            I915_READ(DISP_ARB_CTL));
1683         }
1684         intel_runtime_pm_put(dev_priv);
1685         mutex_unlock(&dev->struct_mutex);
1686
1687         return 0;
1688 }
1689
1690 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1691 {
1692         struct drm_i915_private *dev_priv = dev->dev_private;
1693         struct intel_ring_buffer *ring;
1694         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1695         int unused, i;
1696
1697         if (!ppgtt)
1698                 return;
1699
1700         seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
1701         seq_printf(m, "Page tables: %d\n", ppgtt->num_pt_pages);
1702         for_each_ring(ring, dev_priv, unused) {
1703                 seq_printf(m, "%s\n", ring->name);
1704                 for (i = 0; i < 4; i++) {
1705                         u32 offset = 0x270 + i * 8;
1706                         u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1707                         pdp <<= 32;
1708                         pdp |= I915_READ(ring->mmio_base + offset);
1709                         for (i = 0; i < 4; i++)
1710                                 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1711                 }
1712         }
1713 }
1714
1715 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1716 {
1717         struct drm_i915_private *dev_priv = dev->dev_private;
1718         struct intel_ring_buffer *ring;
1719         int i;
1720
1721         if (INTEL_INFO(dev)->gen == 6)
1722                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1723
1724         for_each_ring(ring, dev_priv, i) {
1725                 seq_printf(m, "%s\n", ring->name);
1726                 if (INTEL_INFO(dev)->gen == 7)
1727                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1728                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1729                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1730                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1731         }
1732         if (dev_priv->mm.aliasing_ppgtt) {
1733                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1734
1735                 seq_puts(m, "aliasing PPGTT:\n");
1736                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1737         }
1738         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1739 }
1740
1741 static int i915_ppgtt_info(struct seq_file *m, void *data)
1742 {
1743         struct drm_info_node *node = (struct drm_info_node *) m->private;
1744         struct drm_device *dev = node->minor->dev;
1745         struct drm_i915_private *dev_priv = dev->dev_private;
1746
1747         int ret = mutex_lock_interruptible(&dev->struct_mutex);
1748         if (ret)
1749                 return ret;
1750         intel_runtime_pm_get(dev_priv);
1751
1752         if (INTEL_INFO(dev)->gen >= 8)
1753                 gen8_ppgtt_info(m, dev);
1754         else if (INTEL_INFO(dev)->gen >= 6)
1755                 gen6_ppgtt_info(m, dev);
1756
1757         intel_runtime_pm_put(dev_priv);
1758         mutex_unlock(&dev->struct_mutex);
1759
1760         return 0;
1761 }
1762
1763 static int i915_dpio_info(struct seq_file *m, void *data)
1764 {
1765         struct drm_info_node *node = (struct drm_info_node *) m->private;
1766         struct drm_device *dev = node->minor->dev;
1767         struct drm_i915_private *dev_priv = dev->dev_private;
1768         int ret;
1769
1770
1771         if (!IS_VALLEYVIEW(dev)) {
1772                 seq_puts(m, "unsupported\n");
1773                 return 0;
1774         }
1775
1776         ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
1777         if (ret)
1778                 return ret;
1779
1780         seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1781
1782         seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n",
1783                    vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0)));
1784         seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n",
1785                    vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1)));
1786
1787         seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n",
1788                    vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0)));
1789         seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n",
1790                    vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1)));
1791
1792         seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n",
1793                    vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0)));
1794         seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n",
1795                    vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1)));
1796
1797         seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n",
1798                    vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0)));
1799         seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n",
1800                    vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1)));
1801
1802         seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1803                    vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0));
1804
1805         mutex_unlock(&dev_priv->dpio_lock);
1806
1807         return 0;
1808 }
1809
1810 static int i915_llc(struct seq_file *m, void *data)
1811 {
1812         struct drm_info_node *node = (struct drm_info_node *) m->private;
1813         struct drm_device *dev = node->minor->dev;
1814         struct drm_i915_private *dev_priv = dev->dev_private;
1815
1816         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1817         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1818         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1819
1820         return 0;
1821 }
1822
1823 static int i915_edp_psr_status(struct seq_file *m, void *data)
1824 {
1825         struct drm_info_node *node = m->private;
1826         struct drm_device *dev = node->minor->dev;
1827         struct drm_i915_private *dev_priv = dev->dev_private;
1828         u32 psrperf = 0;
1829         bool enabled = false;
1830
1831         intel_runtime_pm_get(dev_priv);
1832
1833         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1834         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
1835
1836         enabled = HAS_PSR(dev) &&
1837                 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1838         seq_printf(m, "Enabled: %s\n", yesno(enabled));
1839
1840         if (HAS_PSR(dev))
1841                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1842                         EDP_PSR_PERF_CNT_MASK;
1843         seq_printf(m, "Performance_Counter: %u\n", psrperf);
1844
1845         intel_runtime_pm_put(dev_priv);
1846         return 0;
1847 }
1848
1849 static int i915_energy_uJ(struct seq_file *m, void *data)
1850 {
1851         struct drm_info_node *node = m->private;
1852         struct drm_device *dev = node->minor->dev;
1853         struct drm_i915_private *dev_priv = dev->dev_private;
1854         u64 power;
1855         u32 units;
1856
1857         if (INTEL_INFO(dev)->gen < 6)
1858                 return -ENODEV;
1859
1860         rdmsrl(MSR_RAPL_POWER_UNIT, power);
1861         power = (power & 0x1f00) >> 8;
1862         units = 1000000 / (1 << power); /* convert to uJ */
1863         power = I915_READ(MCH_SECP_NRG_STTS);
1864         power *= units;
1865
1866         seq_printf(m, "%llu", (long long unsigned)power);
1867
1868         return 0;
1869 }
1870
1871 static int i915_pc8_status(struct seq_file *m, void *unused)
1872 {
1873         struct drm_info_node *node = (struct drm_info_node *) m->private;
1874         struct drm_device *dev = node->minor->dev;
1875         struct drm_i915_private *dev_priv = dev->dev_private;
1876
1877         if (!IS_HASWELL(dev)) {
1878                 seq_puts(m, "not supported\n");
1879                 return 0;
1880         }
1881
1882         mutex_lock(&dev_priv->pc8.lock);
1883         seq_printf(m, "Requirements met: %s\n",
1884                    yesno(dev_priv->pc8.requirements_met));
1885         seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle));
1886         seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count);
1887         seq_printf(m, "IRQs disabled: %s\n",
1888                    yesno(dev_priv->pc8.irqs_disabled));
1889         seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
1890         mutex_unlock(&dev_priv->pc8.lock);
1891
1892         return 0;
1893 }
1894
1895 static const char *power_domain_str(enum intel_display_power_domain domain)
1896 {
1897         switch (domain) {
1898         case POWER_DOMAIN_PIPE_A:
1899                 return "PIPE_A";
1900         case POWER_DOMAIN_PIPE_B:
1901                 return "PIPE_B";
1902         case POWER_DOMAIN_PIPE_C:
1903                 return "PIPE_C";
1904         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
1905                 return "PIPE_A_PANEL_FITTER";
1906         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
1907                 return "PIPE_B_PANEL_FITTER";
1908         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
1909                 return "PIPE_C_PANEL_FITTER";
1910         case POWER_DOMAIN_TRANSCODER_A:
1911                 return "TRANSCODER_A";
1912         case POWER_DOMAIN_TRANSCODER_B:
1913                 return "TRANSCODER_B";
1914         case POWER_DOMAIN_TRANSCODER_C:
1915                 return "TRANSCODER_C";
1916         case POWER_DOMAIN_TRANSCODER_EDP:
1917                 return "TRANSCODER_EDP";
1918         case POWER_DOMAIN_VGA:
1919                 return "VGA";
1920         case POWER_DOMAIN_AUDIO:
1921                 return "AUDIO";
1922         case POWER_DOMAIN_INIT:
1923                 return "INIT";
1924         default:
1925                 WARN_ON(1);
1926                 return "?";
1927         }
1928 }
1929
1930 static int i915_power_domain_info(struct seq_file *m, void *unused)
1931 {
1932         struct drm_info_node *node = (struct drm_info_node *) m->private;
1933         struct drm_device *dev = node->minor->dev;
1934         struct drm_i915_private *dev_priv = dev->dev_private;
1935         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1936         int i;
1937
1938         mutex_lock(&power_domains->lock);
1939
1940         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
1941         for (i = 0; i < power_domains->power_well_count; i++) {
1942                 struct i915_power_well *power_well;
1943                 enum intel_display_power_domain power_domain;
1944
1945                 power_well = &power_domains->power_wells[i];
1946                 seq_printf(m, "%-25s %d\n", power_well->name,
1947                            power_well->count);
1948
1949                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
1950                      power_domain++) {
1951                         if (!(BIT(power_domain) & power_well->domains))
1952                                 continue;
1953
1954                         seq_printf(m, "  %-23s %d\n",
1955                                  power_domain_str(power_domain),
1956                                  power_domains->domain_use_count[power_domain]);
1957                 }
1958         }
1959
1960         mutex_unlock(&power_domains->lock);
1961
1962         return 0;
1963 }
1964
1965 struct pipe_crc_info {
1966         const char *name;
1967         struct drm_device *dev;
1968         enum pipe pipe;
1969 };
1970
1971 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
1972 {
1973         struct pipe_crc_info *info = inode->i_private;
1974         struct drm_i915_private *dev_priv = info->dev->dev_private;
1975         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1976
1977         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
1978                 return -ENODEV;
1979
1980         spin_lock_irq(&pipe_crc->lock);
1981
1982         if (pipe_crc->opened) {
1983                 spin_unlock_irq(&pipe_crc->lock);
1984                 return -EBUSY; /* already open */
1985         }
1986
1987         pipe_crc->opened = true;
1988         filep->private_data = inode->i_private;
1989
1990         spin_unlock_irq(&pipe_crc->lock);
1991
1992         return 0;
1993 }
1994
1995 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
1996 {
1997         struct pipe_crc_info *info = inode->i_private;
1998         struct drm_i915_private *dev_priv = info->dev->dev_private;
1999         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2000
2001         spin_lock_irq(&pipe_crc->lock);
2002         pipe_crc->opened = false;
2003         spin_unlock_irq(&pipe_crc->lock);
2004
2005         return 0;
2006 }
2007
2008 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2009 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
2010 /* account for \'0' */
2011 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
2012
2013 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2014 {
2015         assert_spin_locked(&pipe_crc->lock);
2016         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2017                         INTEL_PIPE_CRC_ENTRIES_NR);
2018 }
2019
2020 static ssize_t
2021 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2022                    loff_t *pos)
2023 {
2024         struct pipe_crc_info *info = filep->private_data;
2025         struct drm_device *dev = info->dev;
2026         struct drm_i915_private *dev_priv = dev->dev_private;
2027         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2028         char buf[PIPE_CRC_BUFFER_LEN];
2029         int head, tail, n_entries, n;
2030         ssize_t bytes_read;
2031
2032         /*
2033          * Don't allow user space to provide buffers not big enough to hold
2034          * a line of data.
2035          */
2036         if (count < PIPE_CRC_LINE_LEN)
2037                 return -EINVAL;
2038
2039         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2040                 return 0;
2041
2042         /* nothing to read */
2043         spin_lock_irq(&pipe_crc->lock);
2044         while (pipe_crc_data_count(pipe_crc) == 0) {
2045                 int ret;
2046
2047                 if (filep->f_flags & O_NONBLOCK) {
2048                         spin_unlock_irq(&pipe_crc->lock);
2049                         return -EAGAIN;
2050                 }
2051
2052                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2053                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2054                 if (ret) {
2055                         spin_unlock_irq(&pipe_crc->lock);
2056                         return ret;
2057                 }
2058         }
2059
2060         /* We now have one or more entries to read */
2061         head = pipe_crc->head;
2062         tail = pipe_crc->tail;
2063         n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2064                         count / PIPE_CRC_LINE_LEN);
2065         spin_unlock_irq(&pipe_crc->lock);
2066
2067         bytes_read = 0;
2068         n = 0;
2069         do {
2070                 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
2071                 int ret;
2072
2073                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2074                                        "%8u %8x %8x %8x %8x %8x\n",
2075                                        entry->frame, entry->crc[0],
2076                                        entry->crc[1], entry->crc[2],
2077                                        entry->crc[3], entry->crc[4]);
2078
2079                 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2080                                    buf, PIPE_CRC_LINE_LEN);
2081                 if (ret == PIPE_CRC_LINE_LEN)
2082                         return -EFAULT;
2083
2084                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2085                 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2086                 n++;
2087         } while (--n_entries);
2088
2089         spin_lock_irq(&pipe_crc->lock);
2090         pipe_crc->tail = tail;
2091         spin_unlock_irq(&pipe_crc->lock);
2092
2093         return bytes_read;
2094 }
2095
2096 static const struct file_operations i915_pipe_crc_fops = {
2097         .owner = THIS_MODULE,
2098         .open = i915_pipe_crc_open,
2099         .read = i915_pipe_crc_read,
2100         .release = i915_pipe_crc_release,
2101 };
2102
2103 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2104         {
2105                 .name = "i915_pipe_A_crc",
2106                 .pipe = PIPE_A,
2107         },
2108         {
2109                 .name = "i915_pipe_B_crc",
2110                 .pipe = PIPE_B,
2111         },
2112         {
2113                 .name = "i915_pipe_C_crc",
2114                 .pipe = PIPE_C,
2115         },
2116 };
2117
2118 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2119                                 enum pipe pipe)
2120 {
2121         struct drm_device *dev = minor->dev;
2122         struct dentry *ent;
2123         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2124
2125         info->dev = dev;
2126         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2127                                   &i915_pipe_crc_fops);
2128         if (!ent)
2129                 return -ENOMEM;
2130
2131         return drm_add_fake_info_node(minor, ent, info);
2132 }
2133
2134 static const char * const pipe_crc_sources[] = {
2135         "none",
2136         "plane1",
2137         "plane2",
2138         "pf",
2139         "pipe",
2140         "TV",
2141         "DP-B",
2142         "DP-C",
2143         "DP-D",
2144         "auto",
2145 };
2146
2147 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2148 {
2149         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2150         return pipe_crc_sources[source];
2151 }
2152
2153 static int display_crc_ctl_show(struct seq_file *m, void *data)
2154 {
2155         struct drm_device *dev = m->private;
2156         struct drm_i915_private *dev_priv = dev->dev_private;
2157         int i;
2158
2159         for (i = 0; i < I915_MAX_PIPES; i++)
2160                 seq_printf(m, "%c %s\n", pipe_name(i),
2161                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2162
2163         return 0;
2164 }
2165
2166 static int display_crc_ctl_open(struct inode *inode, struct file *file)
2167 {
2168         struct drm_device *dev = inode->i_private;
2169
2170         return single_open(file, display_crc_ctl_show, dev);
2171 }
2172
2173 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2174                                  uint32_t *val)
2175 {
2176         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2177                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2178
2179         switch (*source) {
2180         case INTEL_PIPE_CRC_SOURCE_PIPE:
2181                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2182                 break;
2183         case INTEL_PIPE_CRC_SOURCE_NONE:
2184                 *val = 0;
2185                 break;
2186         default:
2187                 return -EINVAL;
2188         }
2189
2190         return 0;
2191 }
2192
2193 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2194                                      enum intel_pipe_crc_source *source)
2195 {
2196         struct intel_encoder *encoder;
2197         struct intel_crtc *crtc;
2198         struct intel_digital_port *dig_port;
2199         int ret = 0;
2200
2201         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2202
2203         mutex_lock(&dev->mode_config.mutex);
2204         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2205                             base.head) {
2206                 if (!encoder->base.crtc)
2207                         continue;
2208
2209                 crtc = to_intel_crtc(encoder->base.crtc);
2210
2211                 if (crtc->pipe != pipe)
2212                         continue;
2213
2214                 switch (encoder->type) {
2215                 case INTEL_OUTPUT_TVOUT:
2216                         *source = INTEL_PIPE_CRC_SOURCE_TV;
2217                         break;
2218                 case INTEL_OUTPUT_DISPLAYPORT:
2219                 case INTEL_OUTPUT_EDP:
2220                         dig_port = enc_to_dig_port(&encoder->base);
2221                         switch (dig_port->port) {
2222                         case PORT_B:
2223                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2224                                 break;
2225                         case PORT_C:
2226                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2227                                 break;
2228                         case PORT_D:
2229                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2230                                 break;
2231                         default:
2232                                 WARN(1, "nonexisting DP port %c\n",
2233                                      port_name(dig_port->port));
2234                                 break;
2235                         }
2236                         break;
2237                 }
2238         }
2239         mutex_unlock(&dev->mode_config.mutex);
2240
2241         return ret;
2242 }
2243
2244 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2245                                 enum pipe pipe,
2246                                 enum intel_pipe_crc_source *source,
2247                                 uint32_t *val)
2248 {
2249         struct drm_i915_private *dev_priv = dev->dev_private;
2250         bool need_stable_symbols = false;
2251
2252         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2253                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2254                 if (ret)
2255                         return ret;
2256         }
2257
2258         switch (*source) {
2259         case INTEL_PIPE_CRC_SOURCE_PIPE:
2260                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2261                 break;
2262         case INTEL_PIPE_CRC_SOURCE_DP_B:
2263                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
2264                 need_stable_symbols = true;
2265                 break;
2266         case INTEL_PIPE_CRC_SOURCE_DP_C:
2267                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
2268                 need_stable_symbols = true;
2269                 break;
2270         case INTEL_PIPE_CRC_SOURCE_NONE:
2271                 *val = 0;
2272                 break;
2273         default:
2274                 return -EINVAL;
2275         }
2276
2277         /*
2278          * When the pipe CRC tap point is after the transcoders we need
2279          * to tweak symbol-level features to produce a deterministic series of
2280          * symbols for a given frame. We need to reset those features only once
2281          * a frame (instead of every nth symbol):
2282          *   - DC-balance: used to ensure a better clock recovery from the data
2283          *     link (SDVO)
2284          *   - DisplayPort scrambling: used for EMI reduction
2285          */
2286         if (need_stable_symbols) {
2287                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2288
2289                 WARN_ON(!IS_G4X(dev));
2290
2291                 tmp |= DC_BALANCE_RESET_VLV;
2292                 if (pipe == PIPE_A)
2293                         tmp |= PIPE_A_SCRAMBLE_RESET;
2294                 else
2295                         tmp |= PIPE_B_SCRAMBLE_RESET;
2296
2297                 I915_WRITE(PORT_DFT2_G4X, tmp);
2298         }
2299
2300         return 0;
2301 }
2302
2303 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
2304                                  enum pipe pipe,
2305                                  enum intel_pipe_crc_source *source,
2306                                  uint32_t *val)
2307 {
2308         struct drm_i915_private *dev_priv = dev->dev_private;
2309         bool need_stable_symbols = false;
2310
2311         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2312                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2313                 if (ret)
2314                         return ret;
2315         }
2316
2317         switch (*source) {
2318         case INTEL_PIPE_CRC_SOURCE_PIPE:
2319                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2320                 break;
2321         case INTEL_PIPE_CRC_SOURCE_TV:
2322                 if (!SUPPORTS_TV(dev))
2323                         return -EINVAL;
2324                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2325                 break;
2326         case INTEL_PIPE_CRC_SOURCE_DP_B:
2327                 if (!IS_G4X(dev))
2328                         return -EINVAL;
2329                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
2330                 need_stable_symbols = true;
2331                 break;
2332         case INTEL_PIPE_CRC_SOURCE_DP_C:
2333                 if (!IS_G4X(dev))
2334                         return -EINVAL;
2335                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
2336                 need_stable_symbols = true;
2337                 break;
2338         case INTEL_PIPE_CRC_SOURCE_DP_D:
2339                 if (!IS_G4X(dev))
2340                         return -EINVAL;
2341                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
2342                 need_stable_symbols = true;
2343                 break;
2344         case INTEL_PIPE_CRC_SOURCE_NONE:
2345                 *val = 0;
2346                 break;
2347         default:
2348                 return -EINVAL;
2349         }
2350
2351         /*
2352          * When the pipe CRC tap point is after the transcoders we need
2353          * to tweak symbol-level features to produce a deterministic series of
2354          * symbols for a given frame. We need to reset those features only once
2355          * a frame (instead of every nth symbol):
2356          *   - DC-balance: used to ensure a better clock recovery from the data
2357          *     link (SDVO)
2358          *   - DisplayPort scrambling: used for EMI reduction
2359          */
2360         if (need_stable_symbols) {
2361                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2362
2363                 WARN_ON(!IS_G4X(dev));
2364
2365                 I915_WRITE(PORT_DFT_I9XX,
2366                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2367
2368                 if (pipe == PIPE_A)
2369                         tmp |= PIPE_A_SCRAMBLE_RESET;
2370                 else
2371                         tmp |= PIPE_B_SCRAMBLE_RESET;
2372
2373                 I915_WRITE(PORT_DFT2_G4X, tmp);
2374         }
2375
2376         return 0;
2377 }
2378
2379 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2380                                          enum pipe pipe)
2381 {
2382         struct drm_i915_private *dev_priv = dev->dev_private;
2383         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2384
2385         if (pipe == PIPE_A)
2386                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2387         else
2388                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2389         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2390                 tmp &= ~DC_BALANCE_RESET_VLV;
2391         I915_WRITE(PORT_DFT2_G4X, tmp);
2392
2393 }
2394
2395 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2396                                          enum pipe pipe)
2397 {
2398         struct drm_i915_private *dev_priv = dev->dev_private;
2399         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2400
2401         if (pipe == PIPE_A)
2402                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2403         else
2404                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2405         I915_WRITE(PORT_DFT2_G4X, tmp);
2406
2407         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2408                 I915_WRITE(PORT_DFT_I9XX,
2409                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2410         }
2411 }
2412
2413 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2414                                 uint32_t *val)
2415 {
2416         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2417                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2418
2419         switch (*source) {
2420         case INTEL_PIPE_CRC_SOURCE_PLANE1:
2421                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2422                 break;
2423         case INTEL_PIPE_CRC_SOURCE_PLANE2:
2424                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2425                 break;
2426         case INTEL_PIPE_CRC_SOURCE_PIPE:
2427                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2428                 break;
2429         case INTEL_PIPE_CRC_SOURCE_NONE:
2430                 *val = 0;
2431                 break;
2432         default:
2433                 return -EINVAL;
2434         }
2435
2436         return 0;
2437 }
2438
2439 static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2440                                 uint32_t *val)
2441 {
2442         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2443                 *source = INTEL_PIPE_CRC_SOURCE_PF;
2444
2445         switch (*source) {
2446         case INTEL_PIPE_CRC_SOURCE_PLANE1:
2447                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2448                 break;
2449         case INTEL_PIPE_CRC_SOURCE_PLANE2:
2450                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2451                 break;
2452         case INTEL_PIPE_CRC_SOURCE_PF:
2453                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2454                 break;
2455         case INTEL_PIPE_CRC_SOURCE_NONE:
2456                 *val = 0;
2457                 break;
2458         default:
2459                 return -EINVAL;
2460         }
2461
2462         return 0;
2463 }
2464
2465 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2466                                enum intel_pipe_crc_source source)
2467 {
2468         struct drm_i915_private *dev_priv = dev->dev_private;
2469         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
2470         u32 val = 0; /* shut up gcc */
2471         int ret;
2472
2473         if (pipe_crc->source == source)
2474                 return 0;
2475
2476         /* forbid changing the source without going back to 'none' */
2477         if (pipe_crc->source && source)
2478                 return -EINVAL;
2479
2480         if (IS_GEN2(dev))
2481                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
2482         else if (INTEL_INFO(dev)->gen < 5)
2483                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2484         else if (IS_VALLEYVIEW(dev))
2485                 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
2486         else if (IS_GEN5(dev) || IS_GEN6(dev))
2487                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
2488         else
2489                 ret = ivb_pipe_crc_ctl_reg(&source, &val);
2490
2491         if (ret != 0)
2492                 return ret;
2493
2494         /* none -> real source transition */
2495         if (source) {
2496                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2497                                  pipe_name(pipe), pipe_crc_source_name(source));
2498
2499                 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2500                                             INTEL_PIPE_CRC_ENTRIES_NR,
2501                                             GFP_KERNEL);
2502                 if (!pipe_crc->entries)
2503                         return -ENOMEM;
2504
2505                 spin_lock_irq(&pipe_crc->lock);
2506                 pipe_crc->head = 0;
2507                 pipe_crc->tail = 0;
2508                 spin_unlock_irq(&pipe_crc->lock);
2509         }
2510
2511         pipe_crc->source = source;
2512
2513         I915_WRITE(PIPE_CRC_CTL(pipe), val);
2514         POSTING_READ(PIPE_CRC_CTL(pipe));
2515
2516         /* real source -> none transition */
2517         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
2518                 struct intel_pipe_crc_entry *entries;
2519
2520                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2521                                  pipe_name(pipe));
2522
2523                 intel_wait_for_vblank(dev, pipe);
2524
2525                 spin_lock_irq(&pipe_crc->lock);
2526                 entries = pipe_crc->entries;
2527                 pipe_crc->entries = NULL;
2528                 spin_unlock_irq(&pipe_crc->lock);
2529
2530                 kfree(entries);
2531
2532                 if (IS_G4X(dev))
2533                         g4x_undo_pipe_scramble_reset(dev, pipe);
2534                 else if (IS_VALLEYVIEW(dev))
2535                         vlv_undo_pipe_scramble_reset(dev, pipe);
2536         }
2537
2538         return 0;
2539 }
2540
2541 /*
2542  * Parse pipe CRC command strings:
2543  *   command: wsp* object wsp+ name wsp+ source wsp*
2544  *   object: 'pipe'
2545  *   name: (A | B | C)
2546  *   source: (none | plane1 | plane2 | pf)
2547  *   wsp: (#0x20 | #0x9 | #0xA)+
2548  *
2549  * eg.:
2550  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
2551  *  "pipe A none"    ->  Stop CRC
2552  */
2553 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
2554 {
2555         int n_words = 0;
2556
2557         while (*buf) {
2558                 char *end;
2559
2560                 /* skip leading white space */
2561                 buf = skip_spaces(buf);
2562                 if (!*buf)
2563                         break;  /* end of buffer */
2564
2565                 /* find end of word */
2566                 for (end = buf; *end && !isspace(*end); end++)
2567                         ;
2568
2569                 if (n_words == max_words) {
2570                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2571                                          max_words);
2572                         return -EINVAL; /* ran out of words[] before bytes */
2573                 }
2574
2575                 if (*end)
2576                         *end++ = '\0';
2577                 words[n_words++] = buf;
2578                 buf = end;
2579         }
2580
2581         return n_words;
2582 }
2583
2584 enum intel_pipe_crc_object {
2585         PIPE_CRC_OBJECT_PIPE,
2586 };
2587
2588 static const char * const pipe_crc_objects[] = {
2589         "pipe",
2590 };
2591
2592 static int
2593 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
2594 {
2595         int i;
2596
2597         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
2598                 if (!strcmp(buf, pipe_crc_objects[i])) {
2599                         *o = i;
2600                         return 0;
2601                     }
2602
2603         return -EINVAL;
2604 }
2605
2606 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
2607 {
2608         const char name = buf[0];
2609
2610         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
2611                 return -EINVAL;
2612
2613         *pipe = name - 'A';
2614
2615         return 0;
2616 }
2617
2618 static int
2619 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
2620 {
2621         int i;
2622
2623         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
2624                 if (!strcmp(buf, pipe_crc_sources[i])) {
2625                         *s = i;
2626                         return 0;
2627                     }
2628
2629         return -EINVAL;
2630 }
2631
2632 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
2633 {
2634 #define N_WORDS 3
2635         int n_words;
2636         char *words[N_WORDS];
2637         enum pipe pipe;
2638         enum intel_pipe_crc_object object;
2639         enum intel_pipe_crc_source source;
2640
2641         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
2642         if (n_words != N_WORDS) {
2643                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
2644                                  N_WORDS);
2645                 return -EINVAL;
2646         }
2647
2648         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
2649                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
2650                 return -EINVAL;
2651         }
2652
2653         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
2654                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
2655                 return -EINVAL;
2656         }
2657
2658         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
2659                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
2660                 return -EINVAL;
2661         }
2662
2663         return pipe_crc_set_source(dev, pipe, source);
2664 }
2665
2666 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
2667                                      size_t len, loff_t *offp)
2668 {
2669         struct seq_file *m = file->private_data;
2670         struct drm_device *dev = m->private;
2671         char *tmpbuf;
2672         int ret;
2673
2674         if (len == 0)
2675                 return 0;
2676
2677         if (len > PAGE_SIZE - 1) {
2678                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
2679                                  PAGE_SIZE);
2680                 return -E2BIG;
2681         }
2682
2683         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
2684         if (!tmpbuf)
2685                 return -ENOMEM;
2686
2687         if (copy_from_user(tmpbuf, ubuf, len)) {
2688                 ret = -EFAULT;
2689                 goto out;
2690         }
2691         tmpbuf[len] = '\0';
2692
2693         ret = display_crc_ctl_parse(dev, tmpbuf, len);
2694
2695 out:
2696         kfree(tmpbuf);
2697         if (ret < 0)
2698                 return ret;
2699
2700         *offp += len;
2701         return len;
2702 }
2703
2704 static const struct file_operations i915_display_crc_ctl_fops = {
2705         .owner = THIS_MODULE,
2706         .open = display_crc_ctl_open,
2707         .read = seq_read,
2708         .llseek = seq_lseek,
2709         .release = single_release,
2710         .write = display_crc_ctl_write
2711 };
2712
2713 static int
2714 i915_wedged_get(void *data, u64 *val)
2715 {
2716         struct drm_device *dev = data;
2717         drm_i915_private_t *dev_priv = dev->dev_private;
2718
2719         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
2720
2721         return 0;
2722 }
2723
2724 static int
2725 i915_wedged_set(void *data, u64 val)
2726 {
2727         struct drm_device *dev = data;
2728
2729         DRM_INFO("Manually setting wedged to %llu\n", val);
2730         i915_handle_error(dev, val);
2731
2732         return 0;
2733 }
2734
2735 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
2736                         i915_wedged_get, i915_wedged_set,
2737                         "%llu\n");
2738
2739 static int
2740 i915_ring_stop_get(void *data, u64 *val)
2741 {
2742         struct drm_device *dev = data;
2743         drm_i915_private_t *dev_priv = dev->dev_private;
2744
2745         *val = dev_priv->gpu_error.stop_rings;
2746
2747         return 0;
2748 }
2749
2750 static int
2751 i915_ring_stop_set(void *data, u64 val)
2752 {
2753         struct drm_device *dev = data;
2754         struct drm_i915_private *dev_priv = dev->dev_private;
2755         int ret;
2756
2757         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
2758
2759         ret = mutex_lock_interruptible(&dev->struct_mutex);
2760         if (ret)
2761                 return ret;
2762
2763         dev_priv->gpu_error.stop_rings = val;
2764         mutex_unlock(&dev->struct_mutex);
2765
2766         return 0;
2767 }
2768
2769 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
2770                         i915_ring_stop_get, i915_ring_stop_set,
2771                         "0x%08llx\n");
2772
2773 static int
2774 i915_ring_missed_irq_get(void *data, u64 *val)
2775 {
2776         struct drm_device *dev = data;
2777         struct drm_i915_private *dev_priv = dev->dev_private;
2778
2779         *val = dev_priv->gpu_error.missed_irq_rings;
2780         return 0;
2781 }
2782
2783 static int
2784 i915_ring_missed_irq_set(void *data, u64 val)
2785 {
2786         struct drm_device *dev = data;
2787         struct drm_i915_private *dev_priv = dev->dev_private;
2788         int ret;
2789
2790         /* Lock against concurrent debugfs callers */
2791         ret = mutex_lock_interruptible(&dev->struct_mutex);
2792         if (ret)
2793                 return ret;
2794         dev_priv->gpu_error.missed_irq_rings = val;
2795         mutex_unlock(&dev->struct_mutex);
2796
2797         return 0;
2798 }
2799
2800 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
2801                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
2802                         "0x%08llx\n");
2803
2804 static int
2805 i915_ring_test_irq_get(void *data, u64 *val)
2806 {
2807         struct drm_device *dev = data;
2808         struct drm_i915_private *dev_priv = dev->dev_private;
2809
2810         *val = dev_priv->gpu_error.test_irq_rings;
2811
2812         return 0;
2813 }
2814
2815 static int
2816 i915_ring_test_irq_set(void *data, u64 val)
2817 {
2818         struct drm_device *dev = data;
2819         struct drm_i915_private *dev_priv = dev->dev_private;
2820         int ret;
2821
2822         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
2823
2824         /* Lock against concurrent debugfs callers */
2825         ret = mutex_lock_interruptible(&dev->struct_mutex);
2826         if (ret)
2827                 return ret;
2828
2829         dev_priv->gpu_error.test_irq_rings = val;
2830         mutex_unlock(&dev->struct_mutex);
2831
2832         return 0;
2833 }
2834
2835 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
2836                         i915_ring_test_irq_get, i915_ring_test_irq_set,
2837                         "0x%08llx\n");
2838
2839 #define DROP_UNBOUND 0x1
2840 #define DROP_BOUND 0x2
2841 #define DROP_RETIRE 0x4
2842 #define DROP_ACTIVE 0x8
2843 #define DROP_ALL (DROP_UNBOUND | \
2844                   DROP_BOUND | \
2845                   DROP_RETIRE | \
2846                   DROP_ACTIVE)
2847 static int
2848 i915_drop_caches_get(void *data, u64 *val)
2849 {
2850         *val = DROP_ALL;
2851
2852         return 0;
2853 }
2854
2855 static int
2856 i915_drop_caches_set(void *data, u64 val)
2857 {
2858         struct drm_device *dev = data;
2859         struct drm_i915_private *dev_priv = dev->dev_private;
2860         struct drm_i915_gem_object *obj, *next;
2861         struct i915_address_space *vm;
2862         struct i915_vma *vma, *x;
2863         int ret;
2864
2865         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
2866
2867         /* No need to check and wait for gpu resets, only libdrm auto-restarts
2868          * on ioctls on -EAGAIN. */
2869         ret = mutex_lock_interruptible(&dev->struct_mutex);
2870         if (ret)
2871                 return ret;
2872
2873         if (val & DROP_ACTIVE) {
2874                 ret = i915_gpu_idle(dev);
2875                 if (ret)
2876                         goto unlock;
2877         }
2878
2879         if (val & (DROP_RETIRE | DROP_ACTIVE))
2880                 i915_gem_retire_requests(dev);
2881
2882         if (val & DROP_BOUND) {
2883                 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2884                         list_for_each_entry_safe(vma, x, &vm->inactive_list,
2885                                                  mm_list) {
2886                                 if (vma->obj->pin_count)
2887                                         continue;
2888
2889                                 ret = i915_vma_unbind(vma);
2890                                 if (ret)
2891                                         goto unlock;
2892                         }
2893                 }
2894         }
2895
2896         if (val & DROP_UNBOUND) {
2897                 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
2898                                          global_list)
2899                         if (obj->pages_pin_count == 0) {
2900                                 ret = i915_gem_object_put_pages(obj);
2901                                 if (ret)
2902                                         goto unlock;
2903                         }
2904         }
2905
2906 unlock:
2907         mutex_unlock(&dev->struct_mutex);
2908
2909         return ret;
2910 }
2911
2912 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
2913                         i915_drop_caches_get, i915_drop_caches_set,
2914                         "0x%08llx\n");
2915
2916 static int
2917 i915_max_freq_get(void *data, u64 *val)
2918 {
2919         struct drm_device *dev = data;
2920         drm_i915_private_t *dev_priv = dev->dev_private;
2921         int ret;
2922
2923         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2924                 return -ENODEV;
2925
2926         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2927
2928         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2929         if (ret)
2930                 return ret;
2931
2932         if (IS_VALLEYVIEW(dev))
2933                 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);
2934         else
2935                 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
2936         mutex_unlock(&dev_priv->rps.hw_lock);
2937
2938         return 0;
2939 }
2940
2941 static int
2942 i915_max_freq_set(void *data, u64 val)
2943 {
2944         struct drm_device *dev = data;
2945         struct drm_i915_private *dev_priv = dev->dev_private;
2946         int ret;
2947
2948         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2949                 return -ENODEV;
2950
2951         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2952
2953         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
2954
2955         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2956         if (ret)
2957                 return ret;
2958
2959         /*
2960          * Turbo will still be enabled, but won't go above the set value.
2961          */
2962         if (IS_VALLEYVIEW(dev)) {
2963                 val = vlv_freq_opcode(dev_priv, val);
2964                 dev_priv->rps.max_delay = val;
2965                 valleyview_set_rps(dev, val);
2966         } else {
2967                 do_div(val, GT_FREQUENCY_MULTIPLIER);
2968                 dev_priv->rps.max_delay = val;
2969                 gen6_set_rps(dev, val);
2970         }
2971
2972         mutex_unlock(&dev_priv->rps.hw_lock);
2973
2974         return 0;
2975 }
2976
2977 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
2978                         i915_max_freq_get, i915_max_freq_set,
2979                         "%llu\n");
2980
2981 static int
2982 i915_min_freq_get(void *data, u64 *val)
2983 {
2984         struct drm_device *dev = data;
2985         drm_i915_private_t *dev_priv = dev->dev_private;
2986         int ret;
2987
2988         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2989                 return -ENODEV;
2990
2991         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2992
2993         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2994         if (ret)
2995                 return ret;
2996
2997         if (IS_VALLEYVIEW(dev))
2998                 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);
2999         else
3000                 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
3001         mutex_unlock(&dev_priv->rps.hw_lock);
3002
3003         return 0;
3004 }
3005
3006 static int
3007 i915_min_freq_set(void *data, u64 val)
3008 {
3009         struct drm_device *dev = data;
3010         struct drm_i915_private *dev_priv = dev->dev_private;
3011         int ret;
3012
3013         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3014                 return -ENODEV;
3015
3016         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3017
3018         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
3019
3020         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3021         if (ret)
3022                 return ret;
3023
3024         /*
3025          * Turbo will still be enabled, but won't go below the set value.
3026          */
3027         if (IS_VALLEYVIEW(dev)) {
3028                 val = vlv_freq_opcode(dev_priv, val);
3029                 dev_priv->rps.min_delay = val;
3030                 valleyview_set_rps(dev, val);
3031         } else {
3032                 do_div(val, GT_FREQUENCY_MULTIPLIER);
3033                 dev_priv->rps.min_delay = val;
3034                 gen6_set_rps(dev, val);
3035         }
3036         mutex_unlock(&dev_priv->rps.hw_lock);
3037
3038         return 0;
3039 }
3040
3041 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3042                         i915_min_freq_get, i915_min_freq_set,
3043                         "%llu\n");
3044
3045 static int
3046 i915_cache_sharing_get(void *data, u64 *val)
3047 {
3048         struct drm_device *dev = data;
3049         drm_i915_private_t *dev_priv = dev->dev_private;
3050         u32 snpcr;
3051         int ret;
3052
3053         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3054                 return -ENODEV;
3055
3056         ret = mutex_lock_interruptible(&dev->struct_mutex);
3057         if (ret)
3058                 return ret;
3059         intel_runtime_pm_get(dev_priv);
3060
3061         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3062
3063         intel_runtime_pm_put(dev_priv);
3064         mutex_unlock(&dev_priv->dev->struct_mutex);
3065
3066         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
3067
3068         return 0;
3069 }
3070
3071 static int
3072 i915_cache_sharing_set(void *data, u64 val)
3073 {
3074         struct drm_device *dev = data;
3075         struct drm_i915_private *dev_priv = dev->dev_private;
3076         u32 snpcr;
3077
3078         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3079                 return -ENODEV;
3080
3081         if (val > 3)
3082                 return -EINVAL;
3083
3084         intel_runtime_pm_get(dev_priv);
3085         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
3086
3087         /* Update the cache sharing policy here as well */
3088         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3089         snpcr &= ~GEN6_MBC_SNPCR_MASK;
3090         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3091         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3092
3093         intel_runtime_pm_put(dev_priv);
3094         return 0;
3095 }
3096
3097 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3098                         i915_cache_sharing_get, i915_cache_sharing_set,
3099                         "%llu\n");
3100
3101 static int i915_forcewake_open(struct inode *inode, struct file *file)
3102 {
3103         struct drm_device *dev = inode->i_private;
3104         struct drm_i915_private *dev_priv = dev->dev_private;
3105
3106         if (INTEL_INFO(dev)->gen < 6)
3107                 return 0;
3108
3109         intel_runtime_pm_get(dev_priv);
3110         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3111
3112         return 0;
3113 }
3114
3115 static int i915_forcewake_release(struct inode *inode, struct file *file)
3116 {
3117         struct drm_device *dev = inode->i_private;
3118         struct drm_i915_private *dev_priv = dev->dev_private;
3119
3120         if (INTEL_INFO(dev)->gen < 6)
3121                 return 0;
3122
3123         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3124         intel_runtime_pm_put(dev_priv);
3125
3126         return 0;
3127 }
3128
3129 static const struct file_operations i915_forcewake_fops = {
3130         .owner = THIS_MODULE,
3131         .open = i915_forcewake_open,
3132         .release = i915_forcewake_release,
3133 };
3134
3135 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3136 {
3137         struct drm_device *dev = minor->dev;
3138         struct dentry *ent;
3139
3140         ent = debugfs_create_file("i915_forcewake_user",
3141                                   S_IRUSR,
3142                                   root, dev,
3143                                   &i915_forcewake_fops);
3144         if (!ent)
3145                 return -ENOMEM;
3146
3147         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
3148 }
3149
3150 static int i915_debugfs_create(struct dentry *root,
3151                                struct drm_minor *minor,
3152                                const char *name,
3153                                const struct file_operations *fops)
3154 {
3155         struct drm_device *dev = minor->dev;
3156         struct dentry *ent;
3157
3158         ent = debugfs_create_file(name,
3159                                   S_IRUGO | S_IWUSR,
3160                                   root, dev,
3161                                   fops);
3162         if (!ent)
3163                 return -ENOMEM;
3164
3165         return drm_add_fake_info_node(minor, ent, fops);
3166 }
3167
3168 static const struct drm_info_list i915_debugfs_list[] = {
3169         {"i915_capabilities", i915_capabilities, 0},
3170         {"i915_gem_objects", i915_gem_object_info, 0},
3171         {"i915_gem_gtt", i915_gem_gtt_info, 0},
3172         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
3173         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
3174         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
3175         {"i915_gem_stolen", i915_gem_stolen_list_info },
3176         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
3177         {"i915_gem_request", i915_gem_request_info, 0},
3178         {"i915_gem_seqno", i915_gem_seqno_info, 0},
3179         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
3180         {"i915_gem_interrupt", i915_interrupt_info, 0},
3181         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3182         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3183         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
3184         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
3185         {"i915_rstdby_delays", i915_rstdby_delays, 0},
3186         {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
3187         {"i915_delayfreq_table", i915_delayfreq_table, 0},
3188         {"i915_inttoext_table", i915_inttoext_table, 0},
3189         {"i915_drpc_info", i915_drpc_info, 0},
3190         {"i915_emon_status", i915_emon_status, 0},
3191         {"i915_ring_freq_table", i915_ring_freq_table, 0},
3192         {"i915_gfxec", i915_gfxec, 0},
3193         {"i915_fbc_status", i915_fbc_status, 0},
3194         {"i915_ips_status", i915_ips_status, 0},
3195         {"i915_sr_status", i915_sr_status, 0},
3196         {"i915_opregion", i915_opregion, 0},
3197         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
3198         {"i915_context_status", i915_context_status, 0},
3199         {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
3200         {"i915_swizzle_info", i915_swizzle_info, 0},
3201         {"i915_ppgtt_info", i915_ppgtt_info, 0},
3202         {"i915_dpio", i915_dpio_info, 0},
3203         {"i915_llc", i915_llc, 0},
3204         {"i915_edp_psr_status", i915_edp_psr_status, 0},
3205         {"i915_energy_uJ", i915_energy_uJ, 0},
3206         {"i915_pc8_status", i915_pc8_status, 0},
3207         {"i915_power_domain_info", i915_power_domain_info, 0},
3208 };
3209 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
3210
3211 static const struct i915_debugfs_files {
3212         const char *name;
3213         const struct file_operations *fops;
3214 } i915_debugfs_files[] = {
3215         {"i915_wedged", &i915_wedged_fops},
3216         {"i915_max_freq", &i915_max_freq_fops},
3217         {"i915_min_freq", &i915_min_freq_fops},
3218         {"i915_cache_sharing", &i915_cache_sharing_fops},
3219         {"i915_ring_stop", &i915_ring_stop_fops},
3220         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3221         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
3222         {"i915_gem_drop_caches", &i915_drop_caches_fops},
3223         {"i915_error_state", &i915_error_state_fops},
3224         {"i915_next_seqno", &i915_next_seqno_fops},
3225         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
3226 };
3227
3228 void intel_display_crc_init(struct drm_device *dev)
3229 {
3230         struct drm_i915_private *dev_priv = dev->dev_private;
3231         enum pipe pipe;
3232
3233         for_each_pipe(pipe) {
3234                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3235
3236                 pipe_crc->opened = false;
3237                 spin_lock_init(&pipe_crc->lock);
3238                 init_waitqueue_head(&pipe_crc->wq);
3239         }
3240 }
3241
3242 int i915_debugfs_init(struct drm_minor *minor)
3243 {
3244         int ret, i;
3245
3246         ret = i915_forcewake_create(minor->debugfs_root, minor);
3247         if (ret)
3248                 return ret;
3249
3250         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3251                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3252                 if (ret)
3253                         return ret;
3254         }
3255
3256         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3257                 ret = i915_debugfs_create(minor->debugfs_root, minor,
3258                                           i915_debugfs_files[i].name,
3259                                           i915_debugfs_files[i].fops);
3260                 if (ret)
3261                         return ret;
3262         }
3263
3264         return drm_debugfs_create_files(i915_debugfs_list,
3265                                         I915_DEBUGFS_ENTRIES,
3266                                         minor->debugfs_root, minor);
3267 }
3268
3269 void i915_debugfs_cleanup(struct drm_minor *minor)
3270 {
3271         int i;
3272
3273         drm_debugfs_remove_files(i915_debugfs_list,
3274                                  I915_DEBUGFS_ENTRIES, minor);
3275
3276         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3277                                  1, minor);
3278
3279         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3280                 struct drm_info_list *info_list =
3281                         (struct drm_info_list *)&i915_pipe_crc_data[i];
3282
3283                 drm_debugfs_remove_files(info_list, 1, minor);
3284         }
3285
3286         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3287                 struct drm_info_list *info_list =
3288                         (struct drm_info_list *) i915_debugfs_files[i].fops;
3289
3290                 drm_debugfs_remove_files(info_list, 1, minor);
3291         }
3292 }