drivers/gpu/drm/nouveau/core/engine/device/nvc0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <subdev/bios.h>
  26 #include <subdev/bus.h>
  27 #include <subdev/gpio.h>
  28 #include <subdev/i2c.h>
  29 #include <subdev/clock.h>
  30 #include <subdev/therm.h>
  31 #include <subdev/mxm.h>
  32 #include <subdev/devinit.h>
  33 #include <subdev/mc.h>
  34 #include <subdev/timer.h>
  35 #include <subdev/fb.h>
  36 #include <subdev/ltcg.h>
  37 #include <subdev/ibus.h>
  38 #include <subdev/instmem.h>
  39 #include <subdev/vm.h>
  40 #include <subdev/bar.h>
  41
  42 #include <engine/device.h>
  43 #include <engine/dmaobj.h>
  44 #include <engine/fifo.h>
  45 #include <engine/software.h>
  46 #include <engine/graph.h>
  47 #include <engine/vp.h>
  48 #include <engine/bsp.h>
  49 #include <engine/ppp.h>
  50 #include <engine/copy.h>
  51 #include <engine/disp.h>
  52
  53 int
  54 nvc0_identify(struct nouveau_device *device)
  55 {
  56         switch (device->chipset) {
  57         case 0xc0:
  58                 device->cname = "GF100";
  59                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  60                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
  61                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
  62                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
  63                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
  64                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
  65                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
  66                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
  67                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
  68                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
  69                 device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
  70                 device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
  71                 device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
  72                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
  73                 device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
  74                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
  75                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
  76                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
  77                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
  78                 device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
  79                 device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
  80                 device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
  81                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
  82                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
  83                 device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
  84                 device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
  85                 break;
  86         case 0xc4:
  87                 device->cname = "GF104";
  88                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  89                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
  90                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
  91                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
  92                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
  93                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
  94                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
  95                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
  96                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
  97                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
  98                 device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
  99                 device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
 100                 device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
 101                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 102                 device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
 103                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 104                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
 105                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
 106                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
 107                 device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
 108                 device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 109                 device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
 110                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
 111                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
 112                 device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
 113                 device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
 114                 break;
 115         case 0xc3:
 116                 device->cname = "GF106";
 117                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 118                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 119                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
 120                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
 121                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
 122                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 123                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 124                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
 125                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
 126                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 127                 device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
 128                 device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
 129                 device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
 130                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 131                 device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
 132                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 133                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
 134                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
 135                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
 136                 device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
 137                 device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 138                 device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
 139                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
 140                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
 141                 device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
 142                 break;
 143         case 0xce:
 144                 device->cname = "GF114";
 145                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 146                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 147                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
 148                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
 149                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
 150                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 151                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 152                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
 153                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
 154                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 155                 device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
 156                 device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
 157                 device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
 158                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 159                 device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
 160                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 161                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
 162                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
 163                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
 164                 device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
 165                 device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 166                 device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
 167                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
 168                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
 169                 device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
 170                 device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
 171                 break;
 172         case 0xcf:
 173                 device->cname = "GF116";
 174                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 175                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 176                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
 177                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
 178                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
 179                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 180                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 181                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
 182                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
 183                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 184                 device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
 185                 device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
 186                 device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
 187                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 188                 device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
 189                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 190                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
 191                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
 192                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
 193                 device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
 194                 device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 195                 device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
 196                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
 197                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
 198                 device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
 199                 device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
 200                 break;
 201         case 0xc1:
 202                 device->cname = "GF108";
 203                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 204                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 205                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
 206                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
 207                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
 208                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 209                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 210                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
 211                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
 212                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 213                 device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
 214                 device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
 215                 device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
 216                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 217                 device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
 218                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 219                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
 220                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
 221                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
 222                 device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
 223                 device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 224                 device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
 225                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
 226                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
 227                 device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
 228                 break;
 229         case 0xc8:
 230                 device->cname = "GF110";
 231                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 232                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
 233                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
 234                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
 235                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
 236                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 237                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 238                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
 239                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
 240                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 241                 device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
 242                 device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
 243                 device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
 244                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 245                 device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
 246                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 247                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
 248                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
 249                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
 250                 device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
 251                 device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 252                 device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
 253                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
 254                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
 255                 device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
 256                 device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
 257                 break;
 258         case 0xd9:
 259                 device->cname = "GF119";
 260                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 261                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nvd0_gpio_oclass;
 262                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
 263                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
 264                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
 265                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 266                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 267                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
 268                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
 269                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 270                 device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
 271                 device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
 272                 device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
 273                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 274                 device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
 275                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 276                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
 277                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
 278                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
 279                 device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
 280                 device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 281                 device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
 282                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
 283                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
 284                 device->oclass[NVDEV_ENGINE_DISP   ] = &nvd0_disp_oclass;
 285                 break;
 286         case 0xd7:
 287                 device->cname = "GF117";
 288                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 289                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nvd0_gpio_oclass;
 290                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
 291                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
 292                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
 293                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
 294                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
 295                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
 296                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
 297                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 298                 device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
 299                 device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
 300                 device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
 301                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
 302                 device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
 303                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
 304                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
 305                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
 306                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
 307                 device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
 308                 device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
 309                 device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
 310                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
 311                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
 312                 device->oclass[NVDEV_ENGINE_DISP   ] = &nvd0_disp_oclass;
 313                 break;
 314         default:
 315                 nv_fatal(device, "unknown Fermi chipset\n");
 316                 return -EINVAL;
 317         }
 318
 319         return 0;
 320         }