drivers/media/i2c/s5k5baf.c

   1 /*
   2  * Driver for Samsung S5K5BAF UXGA 1/5" 2M CMOS Image Sensor
   3  * with embedded SoC ISP.
   4  *
   5  * Copyright (C) 2013, Samsung Electronics Co., Ltd.
   6  * Andrzej Hajda <a.hajda@samsung.com>
   7  *
   8  * Based on S5K6AA driver authored by Sylwester Nawrocki
   9  * Copyright (C) 2013, Samsung Electronics Co., Ltd.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/firmware.h>
  19 #include <linux/gpio.h>
  20 #include <linux/i2c.h>
  21 #include <linux/media.h>
  22 #include <linux/module.h>
  23 #include <linux/of_gpio.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/slab.h>
  26
  27 #include <media/media-entity.h>
  28 #include <media/v4l2-ctrls.h>
  29 #include <media/v4l2-device.h>
  30 #include <media/v4l2-subdev.h>
  31 #include <media/v4l2-mediabus.h>
  32 #include <media/v4l2-of.h>
  33
  34 static int debug;
  35 module_param(debug, int, 0644);
  36
  37 #define S5K5BAF_DRIVER_NAME             "s5k5baf"
  38 #define S5K5BAF_DEFAULT_MCLK_FREQ       24000000U
  39 #define S5K5BAF_CLK_NAME                "mclk"
  40
  41 #define S5K5BAF_FW_FILENAME             "s5k5baf-cfg.bin"
  42 #define S5K5BAF_FW_TAG                  "SF00"
  43 #define S5K5BAG_FW_TAG_LEN              2
  44 #define S5K5BAG_FW_MAX_COUNT            16
  45
  46 #define S5K5BAF_CIS_WIDTH               1600
  47 #define S5K5BAF_CIS_HEIGHT              1200
  48 #define S5K5BAF_WIN_WIDTH_MIN           8
  49 #define S5K5BAF_WIN_HEIGHT_MIN          8
  50 #define S5K5BAF_GAIN_RED_DEF            127
  51 #define S5K5BAF_GAIN_GREEN_DEF          95
  52 #define S5K5BAF_GAIN_BLUE_DEF           180
  53 /* Default number of MIPI CSI-2 data lanes used */
  54 #define S5K5BAF_DEF_NUM_LANES           1
  55
  56 #define AHB_MSB_ADDR_PTR                0xfcfc
  57
  58 /*
  59  * Register interface pages (the most significant word of the address)
  60  */
  61 #define PAGE_IF_HW                      0xd000
  62 #define PAGE_IF_SW                      0x7000
  63
  64 /*
  65  * H/W register Interface (PAGE_IF_HW)
  66  */
  67 #define REG_SW_LOAD_COMPLETE            0x0014
  68 #define REG_CMDWR_PAGE                  0x0028
  69 #define REG_CMDWR_ADDR                  0x002a
  70 #define REG_CMDRD_PAGE                  0x002c
  71 #define REG_CMDRD_ADDR                  0x002e
  72 #define REG_CMD_BUF                     0x0f12
  73 #define REG_SET_HOST_INT                0x1000
  74 #define REG_CLEAR_HOST_INT              0x1030
  75 #define REG_PATTERN_SET                 0x3100
  76 #define REG_PATTERN_WIDTH               0x3118
  77 #define REG_PATTERN_HEIGHT              0x311a
  78 #define REG_PATTERN_PARAM               0x311c
  79
  80 /*
  81  * S/W register interface (PAGE_IF_SW)
  82  */
  83
  84 /* Firmware revision information */
  85 #define REG_FW_APIVER                   0x012e
  86 #define  S5K5BAF_FW_APIVER              0x0001
  87 #define REG_FW_REVISION                 0x0130
  88 #define REG_FW_SENSOR_ID                0x0152
  89
  90 /* Initialization parameters */
  91 /* Master clock frequency in KHz */
  92 #define REG_I_INCLK_FREQ_L              0x01b8
  93 #define REG_I_INCLK_FREQ_H              0x01ba
  94 #define  MIN_MCLK_FREQ_KHZ              6000U
  95 #define  MAX_MCLK_FREQ_KHZ              48000U
  96 #define REG_I_USE_NPVI_CLOCKS           0x01c6
  97 #define  NPVI_CLOCKS                    1
  98 #define REG_I_USE_NMIPI_CLOCKS          0x01c8
  99 #define  NMIPI_CLOCKS                   1
 100 #define REG_I_BLOCK_INTERNAL_PLL_CALC   0x01ca
 101
 102 /* Clock configurations, n = 0..2. REG_I_* frequency unit is 4 kHz. */
 103 #define REG_I_OPCLK_4KHZ(n)             ((n) * 6 + 0x01cc)
 104 #define REG_I_MIN_OUTRATE_4KHZ(n)       ((n) * 6 + 0x01ce)
 105 #define REG_I_MAX_OUTRATE_4KHZ(n)       ((n) * 6 + 0x01d0)
 106 #define  SCLK_PVI_FREQ                  24000
 107 #define  SCLK_MIPI_FREQ                 48000
 108 #define  PCLK_MIN_FREQ                  6000
 109 #define  PCLK_MAX_FREQ                  48000
 110 #define REG_I_USE_REGS_API              0x01de
 111 #define REG_I_INIT_PARAMS_UPDATED       0x01e0
 112 #define REG_I_ERROR_INFO                0x01e2
 113
 114 /* General purpose parameters */
 115 #define REG_USER_BRIGHTNESS             0x01e4
 116 #define REG_USER_CONTRAST               0x01e6
 117 #define REG_USER_SATURATION             0x01e8
 118 #define REG_USER_SHARPBLUR              0x01ea
 119
 120 #define REG_G_SPEC_EFFECTS              0x01ee
 121 #define REG_G_ENABLE_PREV               0x01f0
 122 #define REG_G_ENABLE_PREV_CHG           0x01f2
 123 #define REG_G_NEW_CFG_SYNC              0x01f8
 124 #define REG_G_PREVREQ_IN_WIDTH          0x01fa
 125 #define REG_G_PREVREQ_IN_HEIGHT         0x01fc
 126 #define REG_G_PREVREQ_IN_XOFFS          0x01fe
 127 #define REG_G_PREVREQ_IN_YOFFS          0x0200
 128 #define REG_G_PREVZOOM_IN_WIDTH         0x020a
 129 #define REG_G_PREVZOOM_IN_HEIGHT        0x020c
 130 #define REG_G_PREVZOOM_IN_XOFFS         0x020e
 131 #define REG_G_PREVZOOM_IN_YOFFS         0x0210
 132 #define REG_G_INPUTS_CHANGE_REQ         0x021a
 133 #define REG_G_ACTIVE_PREV_CFG           0x021c
 134 #define REG_G_PREV_CFG_CHG              0x021e
 135 #define REG_G_PREV_OPEN_AFTER_CH        0x0220
 136 #define REG_G_PREV_CFG_ERROR            0x0222
 137 #define  CFG_ERROR_RANGE                0x0b
 138 #define REG_G_PREV_CFG_BYPASS_CHANGED   0x022a
 139 #define REG_G_ACTUAL_P_FR_TIME          0x023a
 140 #define REG_G_ACTUAL_P_OUT_RATE         0x023c
 141 #define REG_G_ACTUAL_C_FR_TIME          0x023e
 142 #define REG_G_ACTUAL_C_OUT_RATE         0x0240
 143
 144 /* Preview control section. n = 0...4. */
 145 #define PREG(n, x)                      ((n) * 0x26 + x)
 146 #define REG_P_OUT_WIDTH(n)              PREG(n, 0x0242)
 147 #define REG_P_OUT_HEIGHT(n)             PREG(n, 0x0244)
 148 #define REG_P_FMT(n)                    PREG(n, 0x0246)
 149 #define REG_P_MAX_OUT_RATE(n)           PREG(n, 0x0248)
 150 #define REG_P_MIN_OUT_RATE(n)           PREG(n, 0x024a)
 151 #define REG_P_PVI_MASK(n)               PREG(n, 0x024c)
 152 #define  PVI_MASK_MIPI                  0x52
 153 #define REG_P_CLK_INDEX(n)              PREG(n, 0x024e)
 154 #define  CLK_PVI_INDEX                  0
 155 #define  CLK_MIPI_INDEX                 NPVI_CLOCKS
 156 #define REG_P_FR_RATE_TYPE(n)           PREG(n, 0x0250)
 157 #define  FR_RATE_DYNAMIC                0
 158 #define  FR_RATE_FIXED                  1
 159 #define  FR_RATE_FIXED_ACCURATE         2
 160 #define REG_P_FR_RATE_Q_TYPE(n)         PREG(n, 0x0252)
 161 #define  FR_RATE_Q_DYNAMIC              0
 162 #define  FR_RATE_Q_BEST_FRRATE          1 /* Binning enabled */
 163 #define  FR_RATE_Q_BEST_QUALITY         2 /* Binning disabled */
 164 /* Frame period in 0.1 ms units */
 165 #define REG_P_MAX_FR_TIME(n)            PREG(n, 0x0254)
 166 #define REG_P_MIN_FR_TIME(n)            PREG(n, 0x0256)
 167 #define  S5K5BAF_MIN_FR_TIME            333  /* x100 us */
 168 #define  S5K5BAF_MAX_FR_TIME            6500 /* x100 us */
 169 /* The below 5 registers are for "device correction" values */
 170 #define REG_P_SATURATION(n)             PREG(n, 0x0258)
 171 #define REG_P_SHARP_BLUR(n)             PREG(n, 0x025a)
 172 #define REG_P_GLAMOUR(n)                PREG(n, 0x025c)
 173 #define REG_P_COLORTEMP(n)              PREG(n, 0x025e)
 174 #define REG_P_GAMMA_INDEX(n)            PREG(n, 0x0260)
 175 #define REG_P_PREV_MIRROR(n)            PREG(n, 0x0262)
 176 #define REG_P_CAP_MIRROR(n)             PREG(n, 0x0264)
 177 #define REG_P_CAP_ROTATION(n)           PREG(n, 0x0266)
 178
 179 /* Extended image property controls */
 180 /* Exposure time in 10 us units */
 181 #define REG_SF_USR_EXPOSURE_L           0x03bc
 182 #define REG_SF_USR_EXPOSURE_H           0x03be
 183 #define REG_SF_USR_EXPOSURE_CHG         0x03c0
 184 #define REG_SF_USR_TOT_GAIN             0x03c2
 185 #define REG_SF_USR_TOT_GAIN_CHG         0x03c4
 186 #define REG_SF_RGAIN                    0x03c6
 187 #define REG_SF_RGAIN_CHG                0x03c8
 188 #define REG_SF_GGAIN                    0x03ca
 189 #define REG_SF_GGAIN_CHG                0x03cc
 190 #define REG_SF_BGAIN                    0x03ce
 191 #define REG_SF_BGAIN_CHG                0x03d0
 192 #define REG_SF_WBGAIN_CHG               0x03d2
 193 #define REG_SF_FLICKER_QUANT            0x03d4
 194 #define REG_SF_FLICKER_QUANT_CHG        0x03d6
 195
 196 /* Output interface (parallel/MIPI) setup */
 197 #define REG_OIF_EN_MIPI_LANES           0x03f2
 198 #define REG_OIF_EN_PACKETS              0x03f4
 199 #define  EN_PACKETS_CSI2                0xc3
 200 #define REG_OIF_CFG_CHG                 0x03f6
 201
 202 /* Auto-algorithms enable mask */
 203 #define REG_DBG_AUTOALG_EN              0x03f8
 204 #define  AALG_ALL_EN                    BIT(0)
 205 #define  AALG_AE_EN                     BIT(1)
 206 #define  AALG_DIVLEI_EN                 BIT(2)
 207 #define  AALG_WB_EN                     BIT(3)
 208 #define  AALG_USE_WB_FOR_ISP            BIT(4)
 209 #define  AALG_FLICKER_EN                BIT(5)
 210 #define  AALG_FIT_EN                    BIT(6)
 211 #define  AALG_WRHW_EN                   BIT(7)
 212
 213 /* Pointers to color correction matrices */
 214 #define REG_PTR_CCM_HORIZON             0x06d0
 215 #define REG_PTR_CCM_INCANDESCENT        0x06d4
 216 #define REG_PTR_CCM_WARM_WHITE          0x06d8
 217 #define REG_PTR_CCM_COOL_WHITE          0x06dc
 218 #define REG_PTR_CCM_DL50                0x06e0
 219 #define REG_PTR_CCM_DL65                0x06e4
 220 #define REG_PTR_CCM_OUTDOOR             0x06ec
 221
 222 #define REG_ARR_CCM(n)                  (0x2800 + 36 * (n))
 223
 224 static const char * const s5k5baf_supply_names[] = {
 225         "vdda",         /* Analog power supply 2.8V (2.6V to 3.0V) */
 226         "vddreg",       /* Regulator input power supply 1.8V (1.7V to 1.9V)
 227                            or 2.8V (2.6V to 3.0) */
 228         "vddio",        /* I/O power supply 1.8V (1.65V to 1.95V)
 229                            or 2.8V (2.5V to 3.1V) */
 230 };
 231 #define S5K5BAF_NUM_SUPPLIES ARRAY_SIZE(s5k5baf_supply_names)
 232
 233 struct s5k5baf_gpio {
 234         int gpio;
 235         int level;
 236 };
 237
 238 enum s5k5baf_gpio_id {
 239         STBY,
 240         RST,
 241         NUM_GPIOS,
 242 };
 243
 244 #define PAD_CIS 0
 245 #define PAD_OUT 1
 246 #define NUM_CIS_PADS 1
 247 #define NUM_ISP_PADS 2
 248
 249 struct s5k5baf_pixfmt {
 250         enum v4l2_mbus_pixelcode code;
 251         u32 colorspace;
 252         /* REG_P_FMT(x) register value */
 253         u16 reg_p_fmt;
 254 };
 255
 256 struct s5k5baf_ctrls {
 257         struct v4l2_ctrl_handler handler;
 258         struct { /* Auto / manual white balance cluster */
 259                 struct v4l2_ctrl *awb;
 260                 struct v4l2_ctrl *gain_red;
 261                 struct v4l2_ctrl *gain_blue;
 262         };
 263         struct { /* Mirror cluster */
 264                 struct v4l2_ctrl *hflip;
 265                 struct v4l2_ctrl *vflip;
 266         };
 267         struct { /* Auto exposure / manual exposure and gain cluster */
 268                 struct v4l2_ctrl *auto_exp;
 269                 struct v4l2_ctrl *exposure;
 270                 struct v4l2_ctrl *gain;
 271         };
 272 };
 273
 274 enum {
 275         S5K5BAF_FW_ID_PATCH,
 276         S5K5BAF_FW_ID_CCM,
 277         S5K5BAF_FW_ID_CIS,
 278 };
 279
 280 struct s5k5baf_fw {
 281         u16 count;
 282         struct {
 283                 u16 id;
 284                 u16 offset;
 285         } seq[0];
 286         u16 data[0];
 287 };
 288
 289 struct s5k5baf {
 290         struct s5k5baf_gpio gpios[NUM_GPIOS];
 291         enum v4l2_mbus_type bus_type;
 292         u8 nlanes;
 293         struct regulator_bulk_data supplies[S5K5BAF_NUM_SUPPLIES];
 294
 295         struct clk *clock;
 296         u32 mclk_frequency;
 297
 298         struct s5k5baf_fw *fw;
 299
 300         struct v4l2_subdev cis_sd;
 301         struct media_pad cis_pad;
 302
 303         struct v4l2_subdev sd;
 304         struct media_pad pads[NUM_ISP_PADS];
 305
 306         /* protects the struct members below */
 307         struct mutex lock;
 308
 309         int error;
 310
 311         struct v4l2_rect crop_sink;
 312         struct v4l2_rect compose;
 313         struct v4l2_rect crop_source;
 314         /* index to s5k5baf_formats array */
 315         int pixfmt;
 316         /* actual frame interval in 100us */
 317         u16 fiv;
 318         /* requested frame interval in 100us */
 319         u16 req_fiv;
 320         /* cache for REG_DBG_AUTOALG_EN register */
 321         u16 auto_alg;
 322
 323         struct s5k5baf_ctrls ctrls;
 324
 325         unsigned int streaming:1;
 326         unsigned int apply_cfg:1;
 327         unsigned int apply_crop:1;
 328         unsigned int valid_auto_alg:1;
 329         unsigned int power;
 330 };
 331
 332 static const struct s5k5baf_pixfmt s5k5baf_formats[] = {
 333         { V4L2_MBUS_FMT_VYUY8_2X8,      V4L2_COLORSPACE_JPEG,   5 },
 334         /* range 16-240 */
 335         { V4L2_MBUS_FMT_VYUY8_2X8,      V4L2_COLORSPACE_REC709, 6 },
 336         { V4L2_MBUS_FMT_RGB565_2X8_BE,  V4L2_COLORSPACE_JPEG,   0 },
 337 };
 338
 339 static struct v4l2_rect s5k5baf_cis_rect = {
 340         0, 0, S5K5BAF_CIS_WIDTH, S5K5BAF_CIS_HEIGHT
 341 };
 342
 343 /* Setfile contains set of I2C command sequences. Each sequence has its ID.
 344  * setfile format:
 345  *      u8 magic[4];
 346  *      u16 count;              number of sequences
 347  *      struct {
 348  *              u16 id;         sequence id
 349  *              u16 offset;     sequence offset in data array
 350  *      } seq[count];
 351  *      u16 data[*];            array containing sequences
 352  *
 353  */
 354 static int s5k5baf_fw_parse(struct device *dev, struct s5k5baf_fw **fw,
 355                             size_t count, const u16 *data)
 356 {
 357         struct s5k5baf_fw *f;
 358         u16 *d, i, *end;
 359         int ret;
 360
 361         if (count < S5K5BAG_FW_TAG_LEN + 1) {
 362                 dev_err(dev, "firmware file too short (%zu)\n", count);
 363                 return -EINVAL;
 364         }
 365
 366         ret = memcmp(data, S5K5BAF_FW_TAG, S5K5BAG_FW_TAG_LEN * sizeof(u16));
 367         if (ret != 0) {
 368                 dev_err(dev, "invalid firmware magic number\n");
 369                 return -EINVAL;
 370         }
 371
 372         data += S5K5BAG_FW_TAG_LEN;
 373         count -= S5K5BAG_FW_TAG_LEN;
 374
 375         d = devm_kzalloc(dev, count * sizeof(u16), GFP_KERNEL);
 376
 377         for (i = 0; i < count; ++i)
 378                 d[i] = le16_to_cpu(data[i]);
 379
 380         f = (struct s5k5baf_fw *)d;
 381         if (count < 1 + 2 * f->count) {
 382                 dev_err(dev, "invalid firmware header (count=%d size=%zu)\n",
 383                         f->count, 2 * (count + S5K5BAG_FW_TAG_LEN));
 384                 return -EINVAL;
 385         }
 386         end = d + count;
 387         d += 1 + 2 * f->count;
 388
 389         for (i = 0; i < f->count; ++i) {
 390                 if (f->seq[i].offset + d <= end)
 391                         continue;
 392                 dev_err(dev, "invalid firmware header (seq=%d)\n", i);
 393                 return -EINVAL;
 394         }
 395
 396         *fw = f;
 397
 398         return 0;
 399 }
 400
 401 static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
 402 {
 403         return &container_of(ctrl->handler, struct s5k5baf, ctrls.handler)->sd;
 404 }
 405
 406 static inline bool s5k5baf_is_cis_subdev(struct v4l2_subdev *sd)
 407 {
 408         return sd->entity.type == MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;
 409 }
 410
 411 static inline struct s5k5baf *to_s5k5baf(struct v4l2_subdev *sd)
 412 {
 413         if (s5k5baf_is_cis_subdev(sd))
 414                 return container_of(sd, struct s5k5baf, cis_sd);
 415         else
 416                 return container_of(sd, struct s5k5baf, sd);
 417 }
 418
 419 static u16 s5k5baf_i2c_read(struct s5k5baf *state, u16 addr)
 420 {
 421         struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
 422         __be16 w, r;
 423         struct i2c_msg msg[] = {
 424                 { .addr = c->addr, .flags = 0,
 425                   .len = 2, .buf = (u8 *)&w },
 426                 { .addr = c->addr, .flags = I2C_M_RD,
 427                   .len = 2, .buf = (u8 *)&r },
 428         };
 429         int ret;
 430
 431         if (state->error)
 432                 return 0;
 433
 434         w = cpu_to_be16(addr);
 435         ret = i2c_transfer(c->adapter, msg, 2);
 436         r = be16_to_cpu(r);
 437
 438         v4l2_dbg(3, debug, c, "i2c_read: 0x%04x : 0x%04x\n", addr, r);
 439
 440         if (ret != 2) {
 441                 v4l2_err(c, "i2c_read: error during transfer (%d)\n", ret);
 442                 state->error = ret;
 443         }
 444         return r;
 445 }
 446
 447 static void s5k5baf_i2c_write(struct s5k5baf *state, u16 addr, u16 val)
 448 {
 449         u8 buf[4] = { addr >> 8, addr & 0xFF, val >> 8, val & 0xFF };
 450         struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
 451         int ret;
 452
 453         if (state->error)
 454                 return;
 455
 456         ret = i2c_master_send(c, buf, 4);
 457         v4l2_dbg(3, debug, c, "i2c_write: 0x%04x : 0x%04x\n", addr, val);
 458
 459         if (ret != 4) {
 460                 v4l2_err(c, "i2c_write: error during transfer (%d)\n", ret);
 461                 state->error = ret;
 462         }
 463 }
 464
 465 static u16 s5k5baf_read(struct s5k5baf *state, u16 addr)
 466 {
 467         s5k5baf_i2c_write(state, REG_CMDRD_ADDR, addr);
 468         return s5k5baf_i2c_read(state, REG_CMD_BUF);
 469 }
 470
 471 static void s5k5baf_write(struct s5k5baf *state, u16 addr, u16 val)
 472 {
 473         s5k5baf_i2c_write(state, REG_CMDWR_ADDR, addr);
 474         s5k5baf_i2c_write(state, REG_CMD_BUF, val);
 475 }
 476
 477 static void s5k5baf_write_arr_seq(struct s5k5baf *state, u16 addr,
 478                                   u16 count, const u16 *seq)
 479 {
 480         struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
 481         __be16 buf[count + 1];
 482         int ret, n;
 483
 484         s5k5baf_i2c_write(state, REG_CMDWR_ADDR, addr);
 485         if (state->error)
 486                 return;
 487
 488         buf[0] = __constant_cpu_to_be16(REG_CMD_BUF);
 489         for (n = 1; n <= count; ++n)
 490                 buf[n] = cpu_to_be16(*seq++);
 491
 492         n *= 2;
 493         ret = i2c_master_send(c, (char *)buf, n);
 494         v4l2_dbg(3, debug, c, "i2c_write_seq(count=%d): %*ph\n", count,
 495                  min(2 * count, 64), seq - count);
 496
 497         if (ret != n) {
 498                 v4l2_err(c, "i2c_write_seq: error during transfer (%d)\n", ret);
 499                 state->error = ret;
 500         }
 501 }
 502
 503 #define s5k5baf_write_seq(state, addr, seq...) \
 504         s5k5baf_write_arr_seq(state, addr, sizeof((char[]){ seq }), \
 505                               (const u16 []){ seq });
 506
 507 /* add items count at the beginning of the list */
 508 #define NSEQ(seq...) sizeof((char[]){ seq }), seq
 509
 510 /*
 511  * s5k5baf_write_nseq() - Writes sequences of values to sensor memory via i2c
 512  * @nseq: sequence of u16 words in format:
 513  *      (N, address, value[1]...value[N-1])*,0
 514  * Ex.:
 515  *      u16 seq[] = { NSEQ(0x4000, 1, 1), NSEQ(0x4010, 640, 480), 0 };
 516  *      ret = s5k5baf_write_nseq(c, seq);
 517  */
 518 static void s5k5baf_write_nseq(struct s5k5baf *state, const u16 *nseq)
 519 {
 520         int count;
 521
 522         while ((count = *nseq++)) {
 523                 u16 addr = *nseq++;
 524                 --count;
 525
 526                 s5k5baf_write_arr_seq(state, addr, count, nseq);
 527                 nseq += count;
 528         }
 529 }
 530
 531 static void s5k5baf_synchronize(struct s5k5baf *state, int timeout, u16 addr)
 532 {
 533         unsigned long end = jiffies + msecs_to_jiffies(timeout);
 534         u16 reg;
 535
 536         s5k5baf_write(state, addr, 1);
 537         do {
 538                 reg = s5k5baf_read(state, addr);
 539                 if (state->error || !reg)
 540                         return;
 541                 usleep_range(5000, 10000);
 542         } while (time_is_after_jiffies(end));
 543
 544         v4l2_err(&state->sd, "timeout on register synchronize (%#x)\n", addr);
 545         state->error = -ETIMEDOUT;
 546 }
 547
 548 static u16 *s5k5baf_fw_get_seq(struct s5k5baf *state, u16 seq_id)
 549 {
 550         struct s5k5baf_fw *fw = state->fw;
 551         u16 *data;
 552         int i;
 553
 554         if (fw == NULL)
 555                 return NULL;
 556
 557         data = fw->data + 2 * fw->count;
 558
 559         for (i = 0; i < fw->count; ++i) {
 560                 if (fw->seq[i].id == seq_id)
 561                         return data + fw->seq[i].offset;
 562         }
 563
 564         return NULL;
 565 }
 566
 567 static void s5k5baf_hw_patch(struct s5k5baf *state)
 568 {
 569         u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_PATCH);
 570
 571         if (seq)
 572                 s5k5baf_write_nseq(state, seq);
 573 }
 574
 575 static void s5k5baf_hw_set_clocks(struct s5k5baf *state)
 576 {
 577         unsigned long mclk = state->mclk_frequency / 1000;
 578         u16 status;
 579         static const u16 nseq_clk_cfg[] = {
 580                 NSEQ(REG_I_USE_NPVI_CLOCKS,
 581                   NPVI_CLOCKS, NMIPI_CLOCKS, 0,
 582                   SCLK_PVI_FREQ / 4, PCLK_MIN_FREQ / 4, PCLK_MAX_FREQ / 4,
 583                   SCLK_MIPI_FREQ / 4, PCLK_MIN_FREQ / 4, PCLK_MAX_FREQ / 4),
 584                 NSEQ(REG_I_USE_REGS_API, 1),
 585                 0
 586         };
 587
 588         s5k5baf_write_seq(state, REG_I_INCLK_FREQ_L, mclk & 0xffff, mclk >> 16);
 589         s5k5baf_write_nseq(state, nseq_clk_cfg);
 590
 591         s5k5baf_synchronize(state, 250, REG_I_INIT_PARAMS_UPDATED);
 592         status = s5k5baf_read(state, REG_I_ERROR_INFO);
 593         if (!state->error && status) {
 594                 v4l2_err(&state->sd, "error configuring PLL (%d)\n", status);
 595                 state->error = -EINVAL;
 596         }
 597 }
 598
 599 /* set custom color correction matrices for various illuminations */
 600 static void s5k5baf_hw_set_ccm(struct s5k5baf *state)
 601 {
 602         u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_CCM);
 603
 604         if (seq)
 605                 s5k5baf_write_nseq(state, seq);
 606 }
 607
 608 /* CIS sensor tuning, based on undocumented android driver code */
 609 static void s5k5baf_hw_set_cis(struct s5k5baf *state)
 610 {
 611         u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_CIS);
 612
 613         if (!seq)
 614                 return;
 615
 616         s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_HW);
 617         s5k5baf_write_nseq(state, seq);
 618         s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_SW);
 619 }
 620
 621 static void s5k5baf_hw_sync_cfg(struct s5k5baf *state)
 622 {
 623         s5k5baf_write(state, REG_G_PREV_CFG_CHG, 1);
 624         if (state->apply_crop) {
 625                 s5k5baf_write(state, REG_G_INPUTS_CHANGE_REQ, 1);
 626                 s5k5baf_write(state, REG_G_PREV_CFG_BYPASS_CHANGED, 1);
 627         }
 628         s5k5baf_synchronize(state, 500, REG_G_NEW_CFG_SYNC);
 629 }
 630 /* Set horizontal and vertical image flipping */
 631 static void s5k5baf_hw_set_mirror(struct s5k5baf *state)
 632 {
 633         u16 flip = state->ctrls.vflip->val | (state->ctrls.vflip->val << 1);
 634
 635         s5k5baf_write(state, REG_P_PREV_MIRROR(0), flip);
 636         if (state->streaming)
 637                 s5k5baf_hw_sync_cfg(state);
 638 }
 639
 640 static void s5k5baf_hw_set_alg(struct s5k5baf *state, u16 alg, bool enable)
 641 {
 642         u16 cur_alg, new_alg;
 643
 644         if (!state->valid_auto_alg)
 645                 cur_alg = s5k5baf_read(state, REG_DBG_AUTOALG_EN);
 646         else
 647                 cur_alg = state->auto_alg;
 648
 649         new_alg = enable ? (cur_alg | alg) : (cur_alg & ~alg);
 650
 651         if (new_alg != cur_alg)
 652                 s5k5baf_write(state, REG_DBG_AUTOALG_EN, new_alg);
 653
 654         if (state->error)
 655                 return;
 656
 657         state->valid_auto_alg = 1;
 658         state->auto_alg = new_alg;
 659 }
 660
 661 /* Configure auto/manual white balance and R/G/B gains */
 662 static void s5k5baf_hw_set_awb(struct s5k5baf *state, int awb)
 663 {
 664         struct s5k5baf_ctrls *ctrls = &state->ctrls;
 665
 666         if (!awb)
 667                 s5k5baf_write_seq(state, REG_SF_RGAIN,
 668                                   ctrls->gain_red->val, 1,
 669                                   S5K5BAF_GAIN_GREEN_DEF, 1,
 670                                   ctrls->gain_blue->val, 1,
 671                                   1);
 672
 673         s5k5baf_hw_set_alg(state, AALG_WB_EN, awb);
 674 }
 675
 676 /* Program FW with exposure time, 'exposure' in us units */
 677 static void s5k5baf_hw_set_user_exposure(struct s5k5baf *state, int exposure)
 678 {
 679         unsigned int time = exposure / 10;
 680
 681         s5k5baf_write_seq(state, REG_SF_USR_EXPOSURE_L,
 682                           time & 0xffff, time >> 16, 1);
 683 }
 684
 685 static void s5k5baf_hw_set_user_gain(struct s5k5baf *state, int gain)
 686 {
 687         s5k5baf_write_seq(state, REG_SF_USR_TOT_GAIN, gain, 1);
 688 }
 689
 690 /* Set auto/manual exposure and total gain */
 691 static void s5k5baf_hw_set_auto_exposure(struct s5k5baf *state, int value)
 692 {
 693         if (value == V4L2_EXPOSURE_AUTO) {
 694                 s5k5baf_hw_set_alg(state, AALG_AE_EN | AALG_DIVLEI_EN, true);
 695         } else {
 696                 unsigned int exp_time = state->ctrls.exposure->val;
 697
 698                 s5k5baf_hw_set_user_exposure(state, exp_time);
 699                 s5k5baf_hw_set_user_gain(state, state->ctrls.gain->val);
 700                 s5k5baf_hw_set_alg(state, AALG_AE_EN | AALG_DIVLEI_EN, false);
 701         }
 702 }
 703
 704 static void s5k5baf_hw_set_anti_flicker(struct s5k5baf *state, int v)
 705 {
 706         if (v == V4L2_CID_POWER_LINE_FREQUENCY_AUTO) {
 707                 s5k5baf_hw_set_alg(state, AALG_FLICKER_EN, true);
 708         } else {
 709                 /* The V4L2_CID_LINE_FREQUENCY control values match
 710                  * the register values */
 711                 s5k5baf_write_seq(state, REG_SF_FLICKER_QUANT, v, 1);
 712                 s5k5baf_hw_set_alg(state, AALG_FLICKER_EN, false);
 713         }
 714 }
 715
 716 static void s5k5baf_hw_set_colorfx(struct s5k5baf *state, int val)
 717 {
 718         static const u16 colorfx[] = {
 719                 [V4L2_COLORFX_NONE] = 0,
 720                 [V4L2_COLORFX_BW] = 1,
 721                 [V4L2_COLORFX_NEGATIVE] = 2,
 722                 [V4L2_COLORFX_SEPIA] = 3,
 723                 [V4L2_COLORFX_SKY_BLUE] = 4,
 724                 [V4L2_COLORFX_SKETCH] = 5,
 725         };
 726
 727         s5k5baf_write(state, REG_G_SPEC_EFFECTS, colorfx[val]);
 728 }
 729
 730 static int s5k5baf_find_pixfmt(struct v4l2_mbus_framefmt *mf)
 731 {
 732         int i, c = -1;
 733
 734         for (i = 0; i < ARRAY_SIZE(s5k5baf_formats); i++) {
 735                 if (mf->colorspace != s5k5baf_formats[i].colorspace)
 736                         continue;
 737                 if (mf->code == s5k5baf_formats[i].code)
 738                         return i;
 739                 if (c < 0)
 740                         c = i;
 741         }
 742         return (c < 0) ? 0 : c;
 743 }
 744
 745 static int s5k5baf_clear_error(struct s5k5baf *state)
 746 {
 747         int ret = state->error;
 748
 749         state->error = 0;
 750         return ret;
 751 }
 752
 753 static int s5k5baf_hw_set_video_bus(struct s5k5baf *state)
 754 {
 755         u16 en_pkts;
 756
 757         if (state->bus_type == V4L2_MBUS_CSI2)
 758                 en_pkts = EN_PACKETS_CSI2;
 759         else
 760                 en_pkts = 0;
 761
 762         s5k5baf_write_seq(state, REG_OIF_EN_MIPI_LANES,
 763                           state->nlanes, en_pkts, 1);
 764
 765         return s5k5baf_clear_error(state);
 766 }
 767
 768 static u16 s5k5baf_get_cfg_error(struct s5k5baf *state)
 769 {
 770         u16 err = s5k5baf_read(state, REG_G_PREV_CFG_ERROR);
 771         if (err)
 772                 s5k5baf_write(state, REG_G_PREV_CFG_ERROR, 0);
 773         return err;
 774 }
 775
 776 static void s5k5baf_hw_set_fiv(struct s5k5baf *state, u16 fiv)
 777 {
 778         s5k5baf_write(state, REG_P_MAX_FR_TIME(0), fiv);
 779         s5k5baf_hw_sync_cfg(state);
 780 }
 781
 782 static void s5k5baf_hw_find_min_fiv(struct s5k5baf *state)
 783 {
 784         u16 err, fiv;
 785         int n;
 786
 787         fiv = s5k5baf_read(state,  REG_G_ACTUAL_P_FR_TIME);
 788         if (state->error)
 789                 return;
 790
 791         for (n = 5; n > 0; --n) {
 792                 s5k5baf_hw_set_fiv(state, fiv);
 793                 err = s5k5baf_get_cfg_error(state);
 794                 if (state->error)
 795                         return;
 796                 switch (err) {
 797                 case CFG_ERROR_RANGE:
 798                         ++fiv;
 799                         break;
 800                 case 0:
 801                         state->fiv = fiv;
 802                         v4l2_info(&state->sd,
 803                                   "found valid frame interval: %d00us\n", fiv);
 804                         return;
 805                 default:
 806                         v4l2_err(&state->sd,
 807                                  "error setting frame interval: %d\n", err);
 808                         state->error = -EINVAL;
 809                 }
 810         };
 811         v4l2_err(&state->sd, "cannot find correct frame interval\n");
 812         state->error = -ERANGE;
 813 }
 814
 815 static void s5k5baf_hw_validate_cfg(struct s5k5baf *state)
 816 {
 817         u16 err;
 818
 819         err = s5k5baf_get_cfg_error(state);
 820         if (state->error)
 821                 return;
 822
 823         switch (err) {
 824         case 0:
 825                 state->apply_cfg = 1;
 826                 return;
 827         case CFG_ERROR_RANGE:
 828                 s5k5baf_hw_find_min_fiv(state);
 829                 if (!state->error)
 830                         state->apply_cfg = 1;
 831                 return;
 832         default:
 833                 v4l2_err(&state->sd,
 834                          "error setting format: %d\n", err);
 835                 state->error = -EINVAL;
 836         }
 837 }
 838
 839 static void s5k5baf_rescale(struct v4l2_rect *r, const struct v4l2_rect *v,
 840                             const struct v4l2_rect *n,
 841                             const struct v4l2_rect *d)
 842 {
 843         r->left = v->left * n->width / d->width;
 844         r->top = v->top * n->height / d->height;
 845         r->width = v->width * n->width / d->width;
 846         r->height = v->height * n->height / d->height;
 847 }
 848
 849 static int s5k5baf_hw_set_crop_rects(struct s5k5baf *state)
 850 {
 851         struct v4l2_rect *p, r;
 852         u16 err;
 853         int ret;
 854
 855         p = &state->crop_sink;
 856         s5k5baf_write_seq(state, REG_G_PREVREQ_IN_WIDTH, p->width, p->height,
 857                           p->left, p->top);
 858
 859         s5k5baf_rescale(&r, &state->crop_source, &state->crop_sink,
 860                         &state->compose);
 861         s5k5baf_write_seq(state, REG_G_PREVZOOM_IN_WIDTH, r.width, r.height,
 862                           r.left, r.top);
 863
 864         s5k5baf_synchronize(state, 500, REG_G_INPUTS_CHANGE_REQ);
 865         s5k5baf_synchronize(state, 500, REG_G_PREV_CFG_BYPASS_CHANGED);
 866         err = s5k5baf_get_cfg_error(state);
 867         ret = s5k5baf_clear_error(state);
 868         if (ret < 0)
 869                 return ret;
 870
 871         switch (err) {
 872         case 0:
 873                 break;
 874         case CFG_ERROR_RANGE:
 875                 /* retry crop with frame interval set to max */
 876                 s5k5baf_hw_set_fiv(state, S5K5BAF_MAX_FR_TIME);
 877                 err = s5k5baf_get_cfg_error(state);
 878                 ret = s5k5baf_clear_error(state);
 879                 if (ret < 0)
 880                         return ret;
 881                 if (err) {
 882                         v4l2_err(&state->sd,
 883                                  "crop error on max frame interval: %d\n", err);
 884                         state->error = -EINVAL;
 885                 }
 886                 s5k5baf_hw_set_fiv(state, state->req_fiv);
 887                 s5k5baf_hw_validate_cfg(state);
 888                 break;
 889         default:
 890                 v4l2_err(&state->sd, "crop error: %d\n", err);
 891                 return -EINVAL;
 892         }
 893
 894         if (!state->apply_cfg)
 895                 return 0;
 896
 897         p = &state->crop_source;
 898         s5k5baf_write_seq(state, REG_P_OUT_WIDTH(0), p->width, p->height);
 899         s5k5baf_hw_set_fiv(state, state->req_fiv);
 900         s5k5baf_hw_validate_cfg(state);
 901
 902         return s5k5baf_clear_error(state);
 903 }
 904
 905 static void s5k5baf_hw_set_config(struct s5k5baf *state)
 906 {
 907         u16 reg_fmt = s5k5baf_formats[state->pixfmt].reg_p_fmt;
 908         struct v4l2_rect *r = &state->crop_source;
 909
 910         s5k5baf_write_seq(state, REG_P_OUT_WIDTH(0),
 911                           r->width, r->height, reg_fmt,
 912                           PCLK_MAX_FREQ >> 2, PCLK_MIN_FREQ >> 2,
 913                           PVI_MASK_MIPI, CLK_MIPI_INDEX,
 914                           FR_RATE_FIXED, FR_RATE_Q_DYNAMIC,
 915                           state->req_fiv, S5K5BAF_MIN_FR_TIME);
 916         s5k5baf_hw_sync_cfg(state);
 917         s5k5baf_hw_validate_cfg(state);
 918 }
 919
 920
 921 static void s5k5baf_hw_set_test_pattern(struct s5k5baf *state, int id)
 922 {
 923         s5k5baf_i2c_write(state, REG_PATTERN_WIDTH, 800);
 924         s5k5baf_i2c_write(state, REG_PATTERN_HEIGHT, 511);
 925         s5k5baf_i2c_write(state, REG_PATTERN_PARAM, 0);
 926         s5k5baf_i2c_write(state, REG_PATTERN_SET, id);
 927 }
 928
 929 static void s5k5baf_gpio_assert(struct s5k5baf *state, int id)
 930 {
 931         struct s5k5baf_gpio *gpio = &state->gpios[id];
 932
 933         gpio_set_value(gpio->gpio, gpio->level);
 934 }
 935
 936 static void s5k5baf_gpio_deassert(struct s5k5baf *state, int id)
 937 {
 938         struct s5k5baf_gpio *gpio = &state->gpios[id];
 939
 940         gpio_set_value(gpio->gpio, !gpio->level);
 941 }
 942
 943 static int s5k5baf_power_on(struct s5k5baf *state)
 944 {
 945         int ret;
 946
 947         ret = regulator_bulk_enable(S5K5BAF_NUM_SUPPLIES, state->supplies);
 948         if (ret < 0)
 949                 goto err;
 950
 951         ret = clk_set_rate(state->clock, state->mclk_frequency);
 952         if (ret < 0)
 953                 goto err_reg_dis;
 954
 955         ret = clk_prepare_enable(state->clock);
 956         if (ret < 0)
 957                 goto err_reg_dis;
 958
 959         v4l2_dbg(1, debug, &state->sd, "clock frequency: %ld\n",
 960                  clk_get_rate(state->clock));
 961
 962         s5k5baf_gpio_deassert(state, STBY);
 963         usleep_range(50, 100);
 964         s5k5baf_gpio_deassert(state, RST);
 965         return 0;
 966
 967 err_reg_dis:
 968         regulator_bulk_disable(S5K5BAF_NUM_SUPPLIES, state->supplies);
 969 err:
 970         v4l2_err(&state->sd, "%s() failed (%d)\n", __func__, ret);
 971         return ret;
 972 }
 973
 974 static int s5k5baf_power_off(struct s5k5baf *state)
 975 {
 976         int ret;
 977
 978         state->streaming = 0;
 979         state->apply_cfg = 0;
 980         state->apply_crop = 0;
 981
 982         s5k5baf_gpio_assert(state, RST);
 983         s5k5baf_gpio_assert(state, STBY);
 984
 985         if (!IS_ERR(state->clock))
 986                 clk_disable_unprepare(state->clock);
 987
 988         ret = regulator_bulk_disable(S5K5BAF_NUM_SUPPLIES,
 989                                         state->supplies);
 990         if (ret < 0)
 991                 v4l2_err(&state->sd, "failed to disable regulators\n");
 992
 993         return 0;
 994 }
 995
 996 static void s5k5baf_hw_init(struct s5k5baf *state)
 997 {
 998         s5k5baf_i2c_write(state, AHB_MSB_ADDR_PTR, PAGE_IF_HW);
 999         s5k5baf_i2c_write(state, REG_CLEAR_HOST_INT, 0);
1000         s5k5baf_i2c_write(state, REG_SW_LOAD_COMPLETE, 1);
1001         s5k5baf_i2c_write(state, REG_CMDRD_PAGE, PAGE_IF_SW);
1002         s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_SW);
1003 }
1004
1005 /*
1006  * V4L2 subdev core and video operations
1007  */
1008
1009 static void s5k5baf_initialize_data(struct s5k5baf *state)
1010 {
1011         state->pixfmt = 0;
1012         state->req_fiv = 10000 / 15;
1013         state->fiv = state->req_fiv;
1014         state->valid_auto_alg = 0;
1015 }
1016
1017 static int s5k5baf_load_setfile(struct s5k5baf *state)
1018 {
1019         struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
1020         const struct firmware *fw;
1021         int ret;
1022
1023         ret = request_firmware(&fw, S5K5BAF_FW_FILENAME, &c->dev);
1024         if (ret < 0) {
1025                 dev_warn(&c->dev, "firmware file (%s) not loaded\n",
1026                          S5K5BAF_FW_FILENAME);
1027                 return ret;
1028         }
1029
1030         ret = s5k5baf_fw_parse(&c->dev, &state->fw, fw->size / 2,
1031                                (u16 *)fw->data);
1032
1033         release_firmware(fw);
1034
1035         return ret;
1036 }
1037
1038 static int s5k5baf_set_power(struct v4l2_subdev *sd, int on)
1039 {
1040         struct s5k5baf *state = to_s5k5baf(sd);
1041         int ret = 0;
1042
1043         mutex_lock(&state->lock);
1044
1045         if (!on != state->power)
1046                 goto out;
1047
1048         if (on) {
1049                 if (state->fw == NULL)
1050                         s5k5baf_load_setfile(state);
1051
1052                 s5k5baf_initialize_data(state);
1053                 ret = s5k5baf_power_on(state);
1054                 if (ret < 0)
1055                         goto out;
1056
1057                 s5k5baf_hw_init(state);
1058                 s5k5baf_hw_patch(state);
1059                 s5k5baf_i2c_write(state, REG_SET_HOST_INT, 1);
1060                 s5k5baf_hw_set_clocks(state);
1061
1062                 ret = s5k5baf_hw_set_video_bus(state);
1063                 if (ret < 0)
1064                         goto out;
1065
1066                 s5k5baf_hw_set_cis(state);
1067                 s5k5baf_hw_set_ccm(state);
1068
1069                 ret = s5k5baf_clear_error(state);
1070                 if (!ret)
1071                         state->power++;
1072         } else {
1073                 s5k5baf_power_off(state);
1074                 state->power--;
1075         }
1076
1077 out:
1078         mutex_unlock(&state->lock);
1079
1080         if (!ret && on)
1081                 ret = v4l2_ctrl_handler_setup(&state->ctrls.handler);
1082
1083         return ret;
1084 }
1085
1086 static void s5k5baf_hw_set_stream(struct s5k5baf *state, int enable)
1087 {
1088         s5k5baf_write_seq(state, REG_G_ENABLE_PREV, enable, 1);
1089 }
1090
1091 static int s5k5baf_s_stream(struct v4l2_subdev *sd, int on)
1092 {
1093         struct s5k5baf *state = to_s5k5baf(sd);
1094         int ret;
1095
1096         mutex_lock(&state->lock);
1097
1098         if (state->streaming == !!on) {
1099                 ret = 0;
1100                 goto out;
1101         }
1102
1103         if (on) {
1104                 s5k5baf_hw_set_config(state);
1105                 ret = s5k5baf_hw_set_crop_rects(state);
1106                 if (ret < 0)
1107                         goto out;
1108                 s5k5baf_hw_set_stream(state, 1);
1109                 s5k5baf_i2c_write(state, 0xb0cc, 0x000b);
1110         } else {
1111                 s5k5baf_hw_set_stream(state, 0);
1112         }
1113         ret = s5k5baf_clear_error(state);
1114         if (!ret)
1115                 state->streaming = !state->streaming;
1116
1117 out:
1118         mutex_unlock(&state->lock);
1119
1120         return ret;
1121 }
1122
1123 static int s5k5baf_g_frame_interval(struct v4l2_subdev *sd,
1124                                    struct v4l2_subdev_frame_interval *fi)
1125 {
1126         struct s5k5baf *state = to_s5k5baf(sd);
1127
1128         mutex_lock(&state->lock);
1129         fi->interval.numerator = state->fiv;
1130         fi->interval.denominator = 10000;
1131         mutex_unlock(&state->lock);
1132
1133         return 0;
1134 }
1135
1136 static void s5k5baf_set_frame_interval(struct s5k5baf *state,
1137                                        struct v4l2_subdev_frame_interval *fi)
1138 {
1139         struct v4l2_fract *i = &fi->interval;
1140
1141         if (fi->interval.denominator == 0)
1142                 state->req_fiv = S5K5BAF_MAX_FR_TIME;
1143         else
1144                 state->req_fiv = clamp_t(u32,
1145                                          i->numerator * 10000 / i->denominator,
1146                                          S5K5BAF_MIN_FR_TIME,
1147                                          S5K5BAF_MAX_FR_TIME);
1148
1149         state->fiv = state->req_fiv;
1150         if (state->apply_cfg) {
1151                 s5k5baf_hw_set_fiv(state, state->req_fiv);
1152                 s5k5baf_hw_validate_cfg(state);
1153         }
1154         *i = (struct v4l2_fract){ state->fiv, 10000 };
1155         if (state->fiv == state->req_fiv)
1156                 v4l2_info(&state->sd, "frame interval changed to %d00us\n",
1157                           state->fiv);
1158 }
1159
1160 static int s5k5baf_s_frame_interval(struct v4l2_subdev *sd,
1161                                    struct v4l2_subdev_frame_interval *fi)
1162 {
1163         struct s5k5baf *state = to_s5k5baf(sd);
1164
1165         mutex_lock(&state->lock);
1166         s5k5baf_set_frame_interval(state, fi);
1167         mutex_unlock(&state->lock);
1168         return 0;
1169 }
1170
1171 /*
1172  * V4L2 subdev pad level and video operations
1173  */
1174 static int s5k5baf_enum_frame_interval(struct v4l2_subdev *sd,
1175                               struct v4l2_subdev_fh *fh,
1176                               struct v4l2_subdev_frame_interval_enum *fie)
1177 {
1178         if (fie->index > S5K5BAF_MAX_FR_TIME - S5K5BAF_MIN_FR_TIME ||
1179             fie->pad != PAD_CIS)
1180                 return -EINVAL;
1181
1182         v4l_bound_align_image(&fie->width, S5K5BAF_WIN_WIDTH_MIN,
1183                               S5K5BAF_CIS_WIDTH, 1,
1184                               &fie->height, S5K5BAF_WIN_HEIGHT_MIN,
1185                               S5K5BAF_CIS_HEIGHT, 1, 0);
1186
1187         fie->interval.numerator = S5K5BAF_MIN_FR_TIME + fie->index;
1188         fie->interval.denominator = 10000;
1189
1190         return 0;
1191 }
1192
1193 static int s5k5baf_enum_mbus_code(struct v4l2_subdev *sd,
1194                                  struct v4l2_subdev_fh *fh,
1195                                  struct v4l2_subdev_mbus_code_enum *code)
1196 {
1197         if (code->pad == PAD_CIS) {
1198                 if (code->index > 0)
1199                         return -EINVAL;
1200                 code->code = V4L2_MBUS_FMT_FIXED;
1201                 return 0;
1202         }
1203
1204         if (code->index >= ARRAY_SIZE(s5k5baf_formats))
1205                 return -EINVAL;
1206
1207         code->code = s5k5baf_formats[code->index].code;
1208         return 0;
1209 }
1210
1211 static int s5k5baf_enum_frame_size(struct v4l2_subdev *sd,
1212                                   struct v4l2_subdev_fh *fh,
1213                                   struct v4l2_subdev_frame_size_enum *fse)
1214 {
1215         int i;
1216
1217         if (fse->index > 0)
1218                 return -EINVAL;
1219
1220         if (fse->pad == PAD_CIS) {
1221                 fse->code = V4L2_MBUS_FMT_FIXED;
1222                 fse->min_width = S5K5BAF_CIS_WIDTH;
1223                 fse->max_width = S5K5BAF_CIS_WIDTH;
1224                 fse->min_height = S5K5BAF_CIS_HEIGHT;
1225                 fse->max_height = S5K5BAF_CIS_HEIGHT;
1226                 return 0;
1227         }
1228
1229         i = ARRAY_SIZE(s5k5baf_formats);
1230         while (--i)
1231                 if (fse->code == s5k5baf_formats[i].code)
1232                         break;
1233         fse->code = s5k5baf_formats[i].code;
1234         fse->min_width = S5K5BAF_WIN_WIDTH_MIN;
1235         fse->max_width = S5K5BAF_CIS_WIDTH;
1236         fse->max_height = S5K5BAF_WIN_HEIGHT_MIN;
1237         fse->min_height = S5K5BAF_CIS_HEIGHT;
1238
1239         return 0;
1240 }
1241
1242 static void s5k5baf_try_cis_format(struct v4l2_mbus_framefmt *mf)
1243 {
1244         mf->width = S5K5BAF_CIS_WIDTH;
1245         mf->height = S5K5BAF_CIS_HEIGHT;
1246         mf->code = V4L2_MBUS_FMT_FIXED;
1247         mf->colorspace = V4L2_COLORSPACE_JPEG;
1248         mf->field = V4L2_FIELD_NONE;
1249 }
1250
1251 static int s5k5baf_try_isp_format(struct v4l2_mbus_framefmt *mf)
1252 {
1253         int pixfmt;
1254
1255         v4l_bound_align_image(&mf->width, S5K5BAF_WIN_WIDTH_MIN,
1256                               S5K5BAF_CIS_WIDTH, 1,
1257                               &mf->height, S5K5BAF_WIN_HEIGHT_MIN,
1258                               S5K5BAF_CIS_HEIGHT, 1, 0);
1259
1260         pixfmt = s5k5baf_find_pixfmt(mf);
1261
1262         mf->colorspace = s5k5baf_formats[pixfmt].colorspace;
1263         mf->code = s5k5baf_formats[pixfmt].code;
1264         mf->field = V4L2_FIELD_NONE;
1265
1266         return pixfmt;
1267 }
1268
1269 static int s5k5baf_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1270                           struct v4l2_subdev_format *fmt)
1271 {
1272         struct s5k5baf *state = to_s5k5baf(sd);
1273         const struct s5k5baf_pixfmt *pixfmt;
1274         struct v4l2_mbus_framefmt *mf;
1275
1276         if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1277                 mf = v4l2_subdev_get_try_format(fh, fmt->pad);
1278                 fmt->format = *mf;
1279                 return 0;
1280         }
1281
1282         mf = &fmt->format;
1283         if (fmt->pad == PAD_CIS) {
1284                 s5k5baf_try_cis_format(mf);
1285                 return 0;
1286         }
1287         mf->field = V4L2_FIELD_NONE;
1288         mutex_lock(&state->lock);
1289         pixfmt = &s5k5baf_formats[state->pixfmt];
1290         mf->width = state->crop_source.width;
1291         mf->height = state->crop_source.height;
1292         mf->code = pixfmt->code;
1293         mf->colorspace = pixfmt->colorspace;
1294         mutex_unlock(&state->lock);
1295
1296         return 0;
1297 }
1298
1299 static int s5k5baf_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1300                           struct v4l2_subdev_format *fmt)
1301 {
1302         struct v4l2_mbus_framefmt *mf = &fmt->format;
1303         struct s5k5baf *state = to_s5k5baf(sd);
1304         const struct s5k5baf_pixfmt *pixfmt;
1305         int ret = 0;
1306
1307         if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1308                 *v4l2_subdev_get_try_format(fh, fmt->pad) = *mf;
1309                 return 0;
1310         }
1311
1312         if (fmt->pad == PAD_CIS) {
1313                 s5k5baf_try_cis_format(mf);
1314                 return 0;
1315         }
1316
1317         mutex_lock(&state->lock);
1318
1319         if (state->streaming) {
1320                 mutex_unlock(&state->lock);
1321                 return -EBUSY;
1322         }
1323
1324         state->pixfmt = s5k5baf_try_isp_format(mf);
1325         pixfmt = &s5k5baf_formats[state->pixfmt];
1326         mf->code = pixfmt->code;
1327         mf->colorspace = pixfmt->colorspace;
1328         mf->width = state->crop_source.width;
1329         mf->height = state->crop_source.height;
1330
1331         mutex_unlock(&state->lock);
1332         return ret;
1333 }
1334
1335 enum selection_rect { R_CIS, R_CROP_SINK, R_COMPOSE, R_CROP_SOURCE, R_INVALID };
1336
1337 static enum selection_rect s5k5baf_get_sel_rect(u32 pad, u32 target)
1338 {
1339         switch (target) {
1340         case V4L2_SEL_TGT_CROP_BOUNDS:
1341                 return pad ? R_COMPOSE : R_CIS;
1342         case V4L2_SEL_TGT_CROP:
1343                 return pad ? R_CROP_SOURCE : R_CROP_SINK;
1344         case V4L2_SEL_TGT_COMPOSE_BOUNDS:
1345                 return pad ? R_INVALID : R_CROP_SINK;
1346         case V4L2_SEL_TGT_COMPOSE:
1347                 return pad ? R_INVALID : R_COMPOSE;
1348         default:
1349                 return R_INVALID;
1350         }
1351 }
1352
1353 static int s5k5baf_is_bound_target(u32 target)
1354 {
1355         return target == V4L2_SEL_TGT_CROP_BOUNDS ||
1356                 target == V4L2_SEL_TGT_COMPOSE_BOUNDS;
1357 }
1358
1359 static int s5k5baf_get_selection(struct v4l2_subdev *sd,
1360                                  struct v4l2_subdev_fh *fh,
1361                                  struct v4l2_subdev_selection *sel)
1362 {
1363         static enum selection_rect rtype;
1364         struct s5k5baf *state = to_s5k5baf(sd);
1365
1366         rtype = s5k5baf_get_sel_rect(sel->pad, sel->target);
1367
1368         switch (rtype) {
1369         case R_INVALID:
1370                 return -EINVAL;
1371         case R_CIS:
1372                 sel->r = s5k5baf_cis_rect;
1373                 return 0;
1374         default:
1375                 break;
1376         }
1377
1378         if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1379                 if (rtype == R_COMPOSE)
1380                         sel->r = *v4l2_subdev_get_try_compose(fh, sel->pad);
1381                 else
1382                         sel->r = *v4l2_subdev_get_try_crop(fh, sel->pad);
1383                 return 0;
1384         }
1385
1386         mutex_lock(&state->lock);
1387         switch (rtype) {
1388         case R_CROP_SINK:
1389                 sel->r = state->crop_sink;
1390                 break;
1391         case R_COMPOSE:
1392                 sel->r = state->compose;
1393                 break;
1394         case R_CROP_SOURCE:
1395                 sel->r = state->crop_source;
1396                 break;
1397         default:
1398                 break;
1399         }
1400         if (s5k5baf_is_bound_target(sel->target)) {
1401                 sel->r.left = 0;
1402                 sel->r.top = 0;
1403         }
1404         mutex_unlock(&state->lock);
1405
1406         return 0;
1407 }
1408
1409 /* bounds range [start, start+len) to [0, max) and aligns to 2 */
1410 static void s5k5baf_bound_range(u32 *start, u32 *len, u32 max)
1411 {
1412         if (*len > max)
1413                 *len = max;
1414         if (*start + *len > max)
1415                 *start = max - *len;
1416         *start &= ~1;
1417         *len &= ~1;
1418         if (*len < S5K5BAF_WIN_WIDTH_MIN)
1419                 *len = S5K5BAF_WIN_WIDTH_MIN;
1420 }
1421
1422 static void s5k5baf_bound_rect(struct v4l2_rect *r, u32 width, u32 height)
1423 {
1424         s5k5baf_bound_range(&r->left, &r->width, width);
1425         s5k5baf_bound_range(&r->top, &r->height, height);
1426 }
1427
1428 static void s5k5baf_set_rect_and_adjust(struct v4l2_rect **rects,
1429                                         enum selection_rect first,
1430                                         struct v4l2_rect *v)
1431 {
1432         struct v4l2_rect *r, *br;
1433         enum selection_rect i = first;
1434
1435         *rects[first] = *v;
1436         do {
1437                 r = rects[i];
1438                 br = rects[i - 1];
1439                 s5k5baf_bound_rect(r, br->width, br->height);
1440         } while (++i != R_INVALID);
1441         *v = *rects[first];
1442 }
1443
1444 static bool s5k5baf_cmp_rect(const struct v4l2_rect *r1,
1445                              const struct v4l2_rect *r2)
1446 {
1447         return !memcmp(r1, r2, sizeof(*r1));
1448 }
1449
1450 static int s5k5baf_set_selection(struct v4l2_subdev *sd,
1451                                  struct v4l2_subdev_fh *fh,
1452                                  struct v4l2_subdev_selection *sel)
1453 {
1454         static enum selection_rect rtype;
1455         struct s5k5baf *state = to_s5k5baf(sd);
1456         struct v4l2_rect **rects;
1457         int ret = 0;
1458
1459         rtype = s5k5baf_get_sel_rect(sel->pad, sel->target);
1460         if (rtype == R_INVALID || s5k5baf_is_bound_target(sel->target))
1461                 return -EINVAL;
1462
1463         /* allow only scaling on compose */
1464         if (rtype == R_COMPOSE) {
1465                 sel->r.left = 0;
1466                 sel->r.top = 0;
1467         }
1468
1469         if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1470                 rects = (struct v4l2_rect * []) {
1471                                 &s5k5baf_cis_rect,
1472                                 v4l2_subdev_get_try_crop(fh, PAD_CIS),
1473                                 v4l2_subdev_get_try_compose(fh, PAD_CIS),
1474                                 v4l2_subdev_get_try_crop(fh, PAD_OUT)
1475                         };
1476                 s5k5baf_set_rect_and_adjust(rects, rtype, &sel->r);
1477                 return 0;
1478         }
1479
1480         rects = (struct v4l2_rect * []) {
1481                         &s5k5baf_cis_rect,
1482                         &state->crop_sink,
1483                         &state->compose,
1484                         &state->crop_source
1485                 };
1486         mutex_lock(&state->lock);
1487         if (state->streaming) {
1488                 /* adjust sel->r to avoid output resolution change */
1489                 if (rtype < R_CROP_SOURCE) {
1490                         if (sel->r.width < state->crop_source.width)
1491                                 sel->r.width = state->crop_source.width;
1492                         if (sel->r.height < state->crop_source.height)
1493                                 sel->r.height = state->crop_source.height;
1494                 } else {
1495                         sel->r.width = state->crop_source.width;
1496                         sel->r.height = state->crop_source.height;
1497                 }
1498         }
1499         s5k5baf_set_rect_and_adjust(rects, rtype, &sel->r);
1500         if (!s5k5baf_cmp_rect(&state->crop_sink, &s5k5baf_cis_rect) ||
1501             !s5k5baf_cmp_rect(&state->compose, &s5k5baf_cis_rect))
1502                 state->apply_crop = 1;
1503         if (state->streaming)
1504                 ret = s5k5baf_hw_set_crop_rects(state);
1505         mutex_unlock(&state->lock);
1506
1507         return ret;
1508 }
1509
1510 static const struct v4l2_subdev_pad_ops s5k5baf_cis_pad_ops = {
1511         .enum_mbus_code         = s5k5baf_enum_mbus_code,
1512         .enum_frame_size        = s5k5baf_enum_frame_size,
1513         .get_fmt                = s5k5baf_get_fmt,
1514         .set_fmt                = s5k5baf_set_fmt,
1515 };
1516
1517 static const struct v4l2_subdev_pad_ops s5k5baf_pad_ops = {
1518         .enum_mbus_code         = s5k5baf_enum_mbus_code,
1519         .enum_frame_size        = s5k5baf_enum_frame_size,
1520         .enum_frame_interval    = s5k5baf_enum_frame_interval,
1521         .get_fmt                = s5k5baf_get_fmt,
1522         .set_fmt                = s5k5baf_set_fmt,
1523         .get_selection          = s5k5baf_get_selection,
1524         .set_selection          = s5k5baf_set_selection,
1525 };
1526
1527 static const struct v4l2_subdev_video_ops s5k5baf_video_ops = {
1528         .g_frame_interval       = s5k5baf_g_frame_interval,
1529         .s_frame_interval       = s5k5baf_s_frame_interval,
1530         .s_stream               = s5k5baf_s_stream,
1531 };
1532
1533 /*
1534  * V4L2 subdev controls
1535  */
1536
1537 static int s5k5baf_s_ctrl(struct v4l2_ctrl *ctrl)
1538 {
1539         struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
1540         struct s5k5baf *state = to_s5k5baf(sd);
1541         int ret;
1542
1543         v4l2_dbg(1, debug, sd, "ctrl: %s, value: %d\n", ctrl->name, ctrl->val);
1544
1545         mutex_lock(&state->lock);
1546
1547         if (state->power == 0)
1548                 goto unlock;
1549
1550         switch (ctrl->id) {
1551         case V4L2_CID_AUTO_WHITE_BALANCE:
1552                 s5k5baf_hw_set_awb(state, ctrl->val);
1553                 break;
1554
1555         case V4L2_CID_BRIGHTNESS:
1556                 s5k5baf_write(state, REG_USER_BRIGHTNESS, ctrl->val);
1557                 break;
1558
1559         case V4L2_CID_COLORFX:
1560                 s5k5baf_hw_set_colorfx(state, ctrl->val);
1561                 break;
1562
1563         case V4L2_CID_CONTRAST:
1564                 s5k5baf_write(state, REG_USER_CONTRAST, ctrl->val);
1565                 break;
1566
1567         case V4L2_CID_EXPOSURE_AUTO:
1568                 s5k5baf_hw_set_auto_exposure(state, ctrl->val);
1569                 break;
1570
1571         case V4L2_CID_HFLIP:
1572                 s5k5baf_hw_set_mirror(state);
1573                 break;
1574
1575         case V4L2_CID_POWER_LINE_FREQUENCY:
1576                 s5k5baf_hw_set_anti_flicker(state, ctrl->val);
1577                 break;
1578
1579         case V4L2_CID_SATURATION:
1580                 s5k5baf_write(state, REG_USER_SATURATION, ctrl->val);
1581                 break;
1582
1583         case V4L2_CID_SHARPNESS:
1584                 s5k5baf_write(state, REG_USER_SHARPBLUR, ctrl->val);
1585                 break;
1586
1587         case V4L2_CID_WHITE_BALANCE_TEMPERATURE:
1588                 s5k5baf_write(state, REG_P_COLORTEMP(0), ctrl->val);
1589                 if (state->apply_cfg)
1590                         s5k5baf_hw_sync_cfg(state);
1591                 break;
1592
1593         case V4L2_CID_TEST_PATTERN:
1594                 s5k5baf_hw_set_test_pattern(state, ctrl->val);
1595                 break;
1596         }
1597 unlock:
1598         ret = s5k5baf_clear_error(state);
1599         mutex_unlock(&state->lock);
1600         return ret;
1601 }
1602
1603 static const struct v4l2_ctrl_ops s5k5baf_ctrl_ops = {
1604         .s_ctrl = s5k5baf_s_ctrl,
1605 };
1606
1607 static const char * const s5k5baf_test_pattern_menu[] = {
1608         "Disabled",
1609         "Blank",
1610         "Bars",
1611         "Gradients",
1612         "Textile",
1613         "Textile2",
1614         "Squares"
1615 };
1616
1617 static int s5k5baf_initialize_ctrls(struct s5k5baf *state)
1618 {
1619         const struct v4l2_ctrl_ops *ops = &s5k5baf_ctrl_ops;
1620         struct s5k5baf_ctrls *ctrls = &state->ctrls;
1621         struct v4l2_ctrl_handler *hdl = &ctrls->handler;
1622         int ret;
1623
1624         ret = v4l2_ctrl_handler_init(hdl, 16);
1625         if (ret < 0) {
1626                 v4l2_err(&state->sd, "cannot init ctrl handler (%d)\n", ret);
1627                 return ret;
1628         }
1629
1630         /* Auto white balance cluster */
1631         ctrls->awb = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_WHITE_BALANCE,
1632                                        0, 1, 1, 1);
1633         ctrls->gain_red = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
1634                                             0, 255, 1, S5K5BAF_GAIN_RED_DEF);
1635         ctrls->gain_blue = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
1636                                              0, 255, 1, S5K5BAF_GAIN_BLUE_DEF);
1637         v4l2_ctrl_auto_cluster(3, &ctrls->awb, 0, false);
1638
1639         ctrls->hflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
1640         ctrls->vflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
1641         v4l2_ctrl_cluster(2, &ctrls->hflip);
1642
1643         ctrls->auto_exp = v4l2_ctrl_new_std_menu(hdl, ops,
1644                                 V4L2_CID_EXPOSURE_AUTO,
1645                                 V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
1646         /* Exposure time: x 1 us */
1647         ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE,
1648                                             0, 6000000U, 1, 100000U);
1649         /* Total gain: 256 <=> 1x */
1650         ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN,
1651                                         0, 256, 1, 256);
1652         v4l2_ctrl_auto_cluster(3, &ctrls->auto_exp, 0, false);
1653
1654         v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_POWER_LINE_FREQUENCY,
1655                                V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
1656                                V4L2_CID_POWER_LINE_FREQUENCY_AUTO);
1657
1658         v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_COLORFX,
1659                                V4L2_COLORFX_SKY_BLUE, ~0x6f, V4L2_COLORFX_NONE);
1660
1661         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_WHITE_BALANCE_TEMPERATURE,
1662                           0, 256, 1, 0);
1663
1664         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION, -127, 127, 1, 0);
1665         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -127, 127, 1, 0);
1666         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -127, 127, 1, 0);
1667         v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SHARPNESS, -127, 127, 1, 0);
1668
1669         v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,
1670                                      ARRAY_SIZE(s5k5baf_test_pattern_menu) - 1,
1671                                      0, 0, s5k5baf_test_pattern_menu);
1672
1673         if (hdl->error) {
1674                 v4l2_err(&state->sd, "error creating controls (%d)\n",
1675                          hdl->error);
1676                 ret = hdl->error;
1677                 v4l2_ctrl_handler_free(hdl);
1678                 return ret;
1679         }
1680
1681         state->sd.ctrl_handler = hdl;
1682         return 0;
1683 }
1684
1685 /*
1686  * V4L2 subdev internal operations
1687  */
1688 static int s5k5baf_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1689 {
1690         struct v4l2_mbus_framefmt *mf;
1691
1692         mf = v4l2_subdev_get_try_format(fh, PAD_CIS);
1693         s5k5baf_try_cis_format(mf);
1694
1695         if (s5k5baf_is_cis_subdev(sd))
1696                 return 0;
1697
1698         mf = v4l2_subdev_get_try_format(fh, PAD_OUT);
1699         mf->colorspace = s5k5baf_formats[0].colorspace;
1700         mf->code = s5k5baf_formats[0].code;
1701         mf->width = s5k5baf_cis_rect.width;
1702         mf->height = s5k5baf_cis_rect.height;
1703         mf->field = V4L2_FIELD_NONE;
1704
1705         *v4l2_subdev_get_try_crop(fh, PAD_CIS) = s5k5baf_cis_rect;
1706         *v4l2_subdev_get_try_compose(fh, PAD_CIS) = s5k5baf_cis_rect;
1707         *v4l2_subdev_get_try_crop(fh, PAD_OUT) = s5k5baf_cis_rect;
1708
1709         return 0;
1710 }
1711
1712 static int s5k5baf_check_fw_revision(struct s5k5baf *state)
1713 {
1714         u16 api_ver = 0, fw_rev = 0, s_id = 0;
1715         int ret;
1716
1717         api_ver = s5k5baf_read(state, REG_FW_APIVER);
1718         fw_rev = s5k5baf_read(state, REG_FW_REVISION) & 0xff;
1719         s_id = s5k5baf_read(state, REG_FW_SENSOR_ID);
1720         ret = s5k5baf_clear_error(state);
1721         if (ret < 0)
1722                 return ret;
1723
1724         v4l2_info(&state->sd, "FW API=%#x, revision=%#x sensor_id=%#x\n",
1725                   api_ver, fw_rev, s_id);
1726
1727         if (api_ver != S5K5BAF_FW_APIVER) {
1728                 v4l2_err(&state->sd, "FW API version not supported\n");
1729                 return -ENODEV;
1730         }
1731
1732         return 0;
1733 }
1734
1735 static int s5k5baf_registered(struct v4l2_subdev *sd)
1736 {
1737         struct s5k5baf *state = to_s5k5baf(sd);
1738         int ret;
1739
1740         ret = v4l2_device_register_subdev(sd->v4l2_dev, &state->cis_sd);
1741         if (ret < 0)
1742                 v4l2_err(sd, "failed to register subdev %s\n",
1743                          state->cis_sd.name);
1744         else
1745                 ret = media_entity_create_link(&state->cis_sd.entity, PAD_CIS,
1746                                                &state->sd.entity, PAD_CIS,
1747                                                MEDIA_LNK_FL_IMMUTABLE |
1748                                                MEDIA_LNK_FL_ENABLED);
1749         return ret;
1750 }
1751
1752 static void s5k5baf_unregistered(struct v4l2_subdev *sd)
1753 {
1754         struct s5k5baf *state = to_s5k5baf(sd);
1755         v4l2_device_unregister_subdev(&state->cis_sd);
1756 }
1757
1758 static const struct v4l2_subdev_ops s5k5baf_cis_subdev_ops = {
1759         .pad    = &s5k5baf_cis_pad_ops,
1760 };
1761
1762 static const struct v4l2_subdev_internal_ops s5k5baf_cis_subdev_internal_ops = {
1763         .open = s5k5baf_open,
1764 };
1765
1766 static const struct v4l2_subdev_internal_ops s5k5baf_subdev_internal_ops = {
1767         .registered = s5k5baf_registered,
1768         .unregistered = s5k5baf_unregistered,
1769         .open = s5k5baf_open,
1770 };
1771
1772 static const struct v4l2_subdev_core_ops s5k5baf_core_ops = {
1773         .s_power = s5k5baf_set_power,
1774         .log_status = v4l2_ctrl_subdev_log_status,
1775 };
1776
1777 static const struct v4l2_subdev_ops s5k5baf_subdev_ops = {
1778         .core = &s5k5baf_core_ops,
1779         .pad = &s5k5baf_pad_ops,
1780         .video = &s5k5baf_video_ops,
1781 };
1782
1783 static int s5k5baf_configure_gpios(struct s5k5baf *state)
1784 {
1785         static const char const *name[] = { "S5K5BAF_STBY", "S5K5BAF_RST" };
1786         struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
1787         struct s5k5baf_gpio *g = state->gpios;
1788         int ret, i;
1789
1790         for (i = 0; i < NUM_GPIOS; ++i) {
1791                 int flags = GPIOF_DIR_OUT;
1792                 if (g[i].level)
1793                         flags |= GPIOF_INIT_HIGH;
1794                 ret = devm_gpio_request_one(&c->dev, g[i].gpio, flags, name[i]);
1795                 if (ret < 0) {
1796                         v4l2_err(c, "failed to request gpio %s\n", name[i]);
1797                         return ret;
1798                 }
1799         }
1800         return 0;
1801 }
1802
1803 static int s5k5baf_parse_gpios(struct s5k5baf_gpio *gpios, struct device *dev)
1804 {
1805         static const char * const names[] = {
1806                 "stbyn-gpios",
1807                 "rstn-gpios",
1808         };
1809         struct device_node *node = dev->of_node;
1810         enum of_gpio_flags flags;
1811         int ret, i;
1812
1813         for (i = 0; i < NUM_GPIOS; ++i) {
1814                 ret = of_get_named_gpio_flags(node, names[i], 0, &flags);
1815                 if (ret < 0) {
1816                         dev_err(dev, "no %s GPIO pin provided\n", names[i]);
1817                         return ret;
1818                 }
1819                 gpios[i].gpio = ret;
1820                 gpios[i].level = !(flags & OF_GPIO_ACTIVE_LOW);
1821         }
1822
1823         return 0;
1824 }
1825
1826 static int s5k5baf_parse_device_node(struct s5k5baf *state, struct device *dev)
1827 {
1828         struct device_node *node = dev->of_node;
1829         struct device_node *node_ep;
1830         struct v4l2_of_endpoint ep;
1831         int ret;
1832
1833         if (!node) {
1834                 dev_err(dev, "no device-tree node provided\n");
1835                 return -EINVAL;
1836         }
1837
1838         ret = of_property_read_u32(node, "clock-frequency",
1839                                    &state->mclk_frequency);
1840         if (ret < 0) {
1841                 state->mclk_frequency = S5K5BAF_DEFAULT_MCLK_FREQ;
1842                 dev_info(dev, "using default %u Hz clock frequency\n",
1843                          state->mclk_frequency);
1844         }
1845
1846         ret = s5k5baf_parse_gpios(state->gpios, dev);
1847         if (ret < 0)
1848                 return ret;
1849
1850         node_ep = v4l2_of_get_next_endpoint(node, NULL);
1851         if (!node_ep) {
1852                 dev_err(dev, "no endpoint defined at node %s\n",
1853                         node->full_name);
1854                 return -EINVAL;
1855         }
1856
1857         v4l2_of_parse_endpoint(node_ep, &ep);
1858         of_node_put(node_ep);
1859         state->bus_type = ep.bus_type;
1860
1861         switch (state->bus_type) {
1862         case V4L2_MBUS_CSI2:
1863                 state->nlanes = ep.bus.mipi_csi2.num_data_lanes;
1864                 break;
1865         case V4L2_MBUS_PARALLEL:
1866                 break;
1867         default:
1868                 dev_err(dev, "unsupported bus in endpoint defined at node %s\n",
1869                         node->full_name);
1870                 return -EINVAL;
1871         }
1872
1873         return 0;
1874 }
1875
1876 static int s5k5baf_configure_subdevs(struct s5k5baf *state,
1877                                      struct i2c_client *c)
1878 {
1879         struct v4l2_subdev *sd;
1880         int ret;
1881
1882         sd = &state->cis_sd;
1883         v4l2_subdev_init(sd, &s5k5baf_cis_subdev_ops);
1884         sd->owner = THIS_MODULE;
1885         v4l2_set_subdevdata(sd, state);
1886         snprintf(sd->name, sizeof(sd->name), "S5K5BAF-CIS %d-%04x",
1887                  i2c_adapter_id(c->adapter), c->addr);
1888
1889         sd->internal_ops = &s5k5baf_cis_subdev_internal_ops;
1890         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1891
1892         state->cis_pad.flags = MEDIA_PAD_FL_SOURCE;
1893         sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;
1894         ret = media_entity_init(&sd->entity, NUM_CIS_PADS, &state->cis_pad, 0);
1895         if (ret < 0)
1896                 goto err;
1897
1898         sd = &state->sd;
1899         v4l2_i2c_subdev_init(sd, c, &s5k5baf_subdev_ops);
1900         snprintf(sd->name, sizeof(sd->name), "S5K5BAF-ISP %d-%04x",
1901                  i2c_adapter_id(c->adapter), c->addr);
1902
1903         sd->internal_ops = &s5k5baf_subdev_internal_ops;
1904         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1905
1906         state->pads[PAD_CIS].flags = MEDIA_PAD_FL_SINK;
1907         state->pads[PAD_OUT].flags = MEDIA_PAD_FL_SOURCE;
1908         sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV;
1909         ret = media_entity_init(&sd->entity, NUM_ISP_PADS, state->pads, 0);
1910
1911         if (!ret)
1912                 return 0;
1913
1914         media_entity_cleanup(&state->cis_sd.entity);
1915 err:
1916         dev_err(&c->dev, "cannot init media entity %s\n", sd->name);
1917         return ret;
1918 }
1919
1920 static int s5k5baf_configure_regulators(struct s5k5baf *state)
1921 {
1922         struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
1923         int ret;
1924         int i;
1925
1926         for (i = 0; i < S5K5BAF_NUM_SUPPLIES; i++)
1927                 state->supplies[i].supply = s5k5baf_supply_names[i];
1928
1929         ret = devm_regulator_bulk_get(&c->dev, S5K5BAF_NUM_SUPPLIES,
1930                                       state->supplies);
1931         if (ret < 0)
1932                 v4l2_err(c, "failed to get regulators\n");
1933         return ret;
1934 }
1935
1936 static int s5k5baf_probe(struct i2c_client *c,
1937                         const struct i2c_device_id *id)
1938 {
1939         struct s5k5baf *state;
1940         int ret;
1941
1942         state = devm_kzalloc(&c->dev, sizeof(*state), GFP_KERNEL);
1943         if (!state)
1944                 return -ENOMEM;
1945
1946         mutex_init(&state->lock);
1947         state->crop_sink = s5k5baf_cis_rect;
1948         state->compose = s5k5baf_cis_rect;
1949         state->crop_source = s5k5baf_cis_rect;
1950
1951         ret = s5k5baf_parse_device_node(state, &c->dev);
1952         if (ret < 0)
1953                 return ret;
1954
1955         ret = s5k5baf_configure_subdevs(state, c);
1956         if (ret < 0)
1957                 return ret;
1958
1959         ret = s5k5baf_configure_gpios(state);
1960         if (ret < 0)
1961                 goto err_me;
1962
1963         ret = s5k5baf_configure_regulators(state);
1964         if (ret < 0)
1965                 goto err_me;
1966
1967         state->clock = devm_clk_get(state->sd.dev, S5K5BAF_CLK_NAME);
1968         if (IS_ERR(state->clock)) {
1969                 ret = -EPROBE_DEFER;
1970                 goto err_me;
1971         }
1972
1973         ret = s5k5baf_power_on(state);
1974         if (ret < 0) {
1975                 ret = -EPROBE_DEFER;
1976                 goto err_me;
1977         }
1978         s5k5baf_hw_init(state);
1979         ret = s5k5baf_check_fw_revision(state);
1980
1981         s5k5baf_power_off(state);
1982         if (ret < 0)
1983                 goto err_me;
1984
1985         ret = s5k5baf_initialize_ctrls(state);
1986         if (ret < 0)
1987                 goto err_me;
1988
1989         ret = v4l2_async_register_subdev(&state->sd);
1990         if (ret < 0)
1991                 goto err_ctrl;
1992
1993         return 0;
1994
1995 err_ctrl:
1996         v4l2_ctrl_handler_free(state->sd.ctrl_handler);
1997 err_me:
1998         media_entity_cleanup(&state->sd.entity);
1999         media_entity_cleanup(&state->cis_sd.entity);
2000         return ret;
2001 }
2002
2003 static int s5k5baf_remove(struct i2c_client *c)
2004 {
2005         struct v4l2_subdev *sd = i2c_get_clientdata(c);
2006         struct s5k5baf *state = to_s5k5baf(sd);
2007
2008         v4l2_async_unregister_subdev(sd);
2009         v4l2_ctrl_handler_free(sd->ctrl_handler);
2010         media_entity_cleanup(&sd->entity);
2011
2012         sd = &state->cis_sd;
2013         v4l2_device_unregister_subdev(sd);
2014         media_entity_cleanup(&sd->entity);
2015
2016         return 0;
2017 }
2018
2019 static const struct i2c_device_id s5k5baf_id[] = {
2020         { S5K5BAF_DRIVER_NAME, 0 },
2021         { },
2022 };
2023 MODULE_DEVICE_TABLE(i2c, s5k5baf_id);
2024
2025 static const struct of_device_id s5k5baf_of_match[] = {
2026         { .compatible = "samsung,s5k5baf" },
2027         { }
2028 };
2029 MODULE_DEVICE_TABLE(of, s5k5baf_of_match);
2030
2031 static struct i2c_driver s5k5baf_i2c_driver = {
2032         .driver = {
2033                 .of_match_table = s5k5baf_of_match,
2034                 .name = S5K5BAF_DRIVER_NAME
2035         },
2036         .probe          = s5k5baf_probe,
2037         .remove         = s5k5baf_remove,
2038         .id_table       = s5k5baf_id,
2039 };
2040
2041 module_i2c_driver(s5k5baf_i2c_driver);
2042
2043 MODULE_DESCRIPTION("Samsung S5K5BAF(X) UXGA camera driver");
2044 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
2045 MODULE_LICENSE("GPL v2");