drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.c

   1 /*
   2  * cxgb4_uld.c:Chelsio Upper Layer Driver Interface for T4/T5/T6 SGE management
   3  *
   4  * Copyright (c) 2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  *
  34  *  Written by: Atul Gupta (atul.gupta@chelsio.com)
  35  *  Written by: Hariprasad Shenai (hariprasad@chelsio.com)
  36  */
  37
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/errno.h>
  41 #include <linux/types.h>
  42 #include <linux/debugfs.h>
  43 #include <linux/export.h>
  44 #include <linux/list.h>
  45 #include <linux/skbuff.h>
  46 #include <linux/pci.h>
  47
  48 #include "cxgb4.h"
  49 #include "cxgb4_uld.h"
  50 #include "t4_regs.h"
  51 #include "t4fw_api.h"
  52 #include "t4_msg.h"
  53
  54 #define for_each_uldrxq(m, i) for (i = 0; i < ((m)->nrxq + (m)->nciq); i++)
  55
  56 static int get_msix_idx_from_bmap(struct adapter *adap)
  57 {
  58         struct uld_msix_bmap *bmap = &adap->msix_bmap_ulds;
  59         unsigned long flags;
  60         unsigned int msix_idx;
  61
  62         spin_lock_irqsave(&bmap->lock, flags);
  63         msix_idx = find_first_zero_bit(bmap->msix_bmap, bmap->mapsize);
  64         if (msix_idx < bmap->mapsize) {
  65                 __set_bit(msix_idx, bmap->msix_bmap);
  66         } else {
  67                 spin_unlock_irqrestore(&bmap->lock, flags);
  68                 return -ENOSPC;
  69         }
  70
  71         spin_unlock_irqrestore(&bmap->lock, flags);
  72         return msix_idx;
  73 }
  74
  75 static void free_msix_idx_in_bmap(struct adapter *adap, unsigned int msix_idx)
  76 {
  77         struct uld_msix_bmap *bmap = &adap->msix_bmap_ulds;
  78         unsigned long flags;
  79
  80         spin_lock_irqsave(&bmap->lock, flags);
  81          __clear_bit(msix_idx, bmap->msix_bmap);
  82         spin_unlock_irqrestore(&bmap->lock, flags);
  83 }
  84
  85 /* Flush the aggregated lro sessions */
  86 static void uldrx_flush_handler(struct sge_rspq *q)
  87 {
  88         struct adapter *adap = q->adap;
  89
  90         if (adap->uld[q->uld].lro_flush)
  91                 adap->uld[q->uld].lro_flush(&q->lro_mgr);
  92 }
  93
  94 /**
  95  *      uldrx_handler - response queue handler for ULD queues
  96  *      @q: the response queue that received the packet
  97  *      @rsp: the response queue descriptor holding the offload message
  98  *      @gl: the gather list of packet fragments
  99  *
 100  *      Deliver an ingress offload packet to a ULD.  All processing is done by
 101  *      the ULD, we just maintain statistics.
 102  */
 103 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
 104                          const struct pkt_gl *gl)
 105 {
 106         struct adapter *adap = q->adap;
 107         struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
 108         int ret;
 109
 110         /* FW can send CPLs encapsulated in a CPL_FW4_MSG */
 111         if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
 112             ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
 113                 rsp += 2;
 114
 115         if (q->flush_handler)
 116                 ret = adap->uld[q->uld].lro_rx_handler(adap->uld[q->uld].handle,
 117                                 rsp, gl, &q->lro_mgr,
 118                                 &q->napi);
 119         else
 120                 ret = adap->uld[q->uld].rx_handler(adap->uld[q->uld].handle,
 121                                 rsp, gl);
 122
 123         if (ret) {
 124                 rxq->stats.nomem++;
 125                 return -1;
 126         }
 127
 128         if (!gl)
 129                 rxq->stats.imm++;
 130         else if (gl == CXGB4_MSG_AN)
 131                 rxq->stats.an++;
 132         else
 133                 rxq->stats.pkts++;
 134         return 0;
 135 }
 136
 137 static int alloc_uld_rxqs(struct adapter *adap,
 138                           struct sge_uld_rxq_info *rxq_info,
 139                           unsigned int nq, unsigned int offset, bool lro)
 140 {
 141         struct sge *s = &adap->sge;
 142         struct sge_ofld_rxq *q = rxq_info->uldrxq + offset;
 143         unsigned short *ids = rxq_info->rspq_id + offset;
 144         unsigned int per_chan = nq / adap->params.nports;
 145         unsigned int bmap_idx = 0;
 146         int i, err, msi_idx;
 147
 148         if (adap->flags & USING_MSIX)
 149                 msi_idx = 1;
 150         else
 151                 msi_idx = -((int)s->intrq.abs_id + 1);
 152
 153         for (i = 0; i < nq; i++, q++) {
 154                 if (msi_idx >= 0) {
 155                         bmap_idx = get_msix_idx_from_bmap(adap);
 156                         msi_idx = adap->msix_info_ulds[bmap_idx].idx;
 157                 }
 158                 err = t4_sge_alloc_rxq(adap, &q->rspq, false,
 159                                        adap->port[i / per_chan],
 160                                        msi_idx,
 161                                        q->fl.size ? &q->fl : NULL,
 162                                        uldrx_handler,
 163                                        lro ? uldrx_flush_handler : NULL,
 164                                        0);
 165                 if (err)
 166                         goto freeout;
 167                 if (msi_idx >= 0)
 168                         rxq_info->msix_tbl[i + offset] = bmap_idx;
 169                 memset(&q->stats, 0, sizeof(q->stats));
 170                 if (ids)
 171                         ids[i] = q->rspq.abs_id;
 172         }
 173         return 0;
 174 freeout:
 175         q = rxq_info->uldrxq + offset;
 176         for ( ; i; i--, q++) {
 177                 if (q->rspq.desc)
 178                         free_rspq_fl(adap, &q->rspq,
 179                                      q->fl.size ? &q->fl : NULL);
 180         }
 181
 182         /* We need to free rxq also in case of ciq allocation failure */
 183         if (offset) {
 184                 q = rxq_info->uldrxq + offset;
 185                 for ( ; i; i--, q++) {
 186                         if (q->rspq.desc)
 187                                 free_rspq_fl(adap, &q->rspq,
 188                                              q->fl.size ? &q->fl : NULL);
 189                 }
 190         }
 191         return err;
 192 }
 193
 194 int setup_sge_queues_uld(struct adapter *adap, unsigned int uld_type, bool lro)
 195 {
 196         struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
 197         int i, ret = 0;
 198
 199         if (adap->flags & USING_MSIX) {
 200                 rxq_info->msix_tbl = kcalloc((rxq_info->nrxq + rxq_info->nciq),
 201                                              sizeof(unsigned short),
 202                                              GFP_KERNEL);
 203                 if (!rxq_info->msix_tbl)
 204                         return -ENOMEM;
 205         }
 206
 207         ret = !(!alloc_uld_rxqs(adap, rxq_info, rxq_info->nrxq, 0, lro) &&
 208                  !alloc_uld_rxqs(adap, rxq_info, rxq_info->nciq,
 209                                  rxq_info->nrxq, lro));
 210
 211         /* Tell uP to route control queue completions to rdma rspq */
 212         if (adap->flags & FULL_INIT_DONE &&
 213             !ret && uld_type == CXGB4_ULD_RDMA) {
 214                 struct sge *s = &adap->sge;
 215                 unsigned int cmplqid;
 216                 u32 param, cmdop;
 217
 218                 cmdop = FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL;
 219                 for_each_port(adap, i) {
 220                         cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
 221                         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
 222                                  FW_PARAMS_PARAM_X_V(cmdop) |
 223                                  FW_PARAMS_PARAM_YZ_V(s->ctrlq[i].q.cntxt_id));
 224                         ret = t4_set_params(adap, adap->mbox, adap->pf,
 225                                             0, 1, &param, &cmplqid);
 226                 }
 227         }
 228         return ret;
 229 }
 230
 231 static void t4_free_uld_rxqs(struct adapter *adap, int n,
 232                              struct sge_ofld_rxq *q)
 233 {
 234         for ( ; n; n--, q++) {
 235                 if (q->rspq.desc)
 236                         free_rspq_fl(adap, &q->rspq,
 237                                      q->fl.size ? &q->fl : NULL);
 238         }
 239 }
 240
 241 void free_sge_queues_uld(struct adapter *adap, unsigned int uld_type)
 242 {
 243         struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
 244
 245         if (adap->flags & FULL_INIT_DONE && uld_type == CXGB4_ULD_RDMA) {
 246                 struct sge *s = &adap->sge;
 247                 u32 param, cmdop, cmplqid = 0;
 248                 int i;
 249
 250                 cmdop = FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL;
 251                 for_each_port(adap, i) {
 252                         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
 253                                  FW_PARAMS_PARAM_X_V(cmdop) |
 254                                  FW_PARAMS_PARAM_YZ_V(s->ctrlq[i].q.cntxt_id));
 255                         t4_set_params(adap, adap->mbox, adap->pf,
 256                                       0, 1, &param, &cmplqid);
 257                 }
 258         }
 259
 260         if (rxq_info->nciq)
 261                 t4_free_uld_rxqs(adap, rxq_info->nciq,
 262                                  rxq_info->uldrxq + rxq_info->nrxq);
 263         t4_free_uld_rxqs(adap, rxq_info->nrxq, rxq_info->uldrxq);
 264         if (adap->flags & USING_MSIX)
 265                 kfree(rxq_info->msix_tbl);
 266 }
 267
 268 int cfg_queues_uld(struct adapter *adap, unsigned int uld_type,
 269                    const struct cxgb4_uld_info *uld_info)
 270 {
 271         struct sge *s = &adap->sge;
 272         struct sge_uld_rxq_info *rxq_info;
 273         int i, nrxq, ciq_size;
 274
 275         rxq_info = kzalloc(sizeof(*rxq_info), GFP_KERNEL);
 276         if (!rxq_info)
 277                 return -ENOMEM;
 278
 279         if (adap->flags & USING_MSIX && uld_info->nrxq > s->nqs_per_uld) {
 280                 i = s->nqs_per_uld;
 281                 rxq_info->nrxq = roundup(i, adap->params.nports);
 282         } else {
 283                 i = min_t(int, uld_info->nrxq,
 284                           num_online_cpus());
 285                 rxq_info->nrxq = roundup(i, adap->params.nports);
 286         }
 287         if (!uld_info->ciq) {
 288                 rxq_info->nciq = 0;
 289         } else  {
 290                 if (adap->flags & USING_MSIX)
 291                         rxq_info->nciq = min_t(int, s->nqs_per_uld,
 292                                                num_online_cpus());
 293                 else
 294                         rxq_info->nciq = min_t(int, MAX_OFLD_QSETS,
 295                                                num_online_cpus());
 296                 rxq_info->nciq = ((rxq_info->nciq / adap->params.nports) *
 297                                   adap->params.nports);
 298                 rxq_info->nciq = max_t(int, rxq_info->nciq,
 299                                        adap->params.nports);
 300         }
 301
 302         nrxq = rxq_info->nrxq + rxq_info->nciq; /* total rxq's */
 303         rxq_info->uldrxq = kcalloc(nrxq, sizeof(struct sge_ofld_rxq),
 304                                    GFP_KERNEL);
 305         if (!rxq_info->uldrxq) {
 306                 kfree(rxq_info);
 307                 return -ENOMEM;
 308         }
 309
 310         rxq_info->rspq_id = kcalloc(nrxq, sizeof(unsigned short), GFP_KERNEL);
 311         if (!rxq_info->rspq_id) {
 312                 kfree(rxq_info->uldrxq);
 313                 kfree(rxq_info);
 314                 return -ENOMEM;
 315         }
 316
 317         for (i = 0; i < rxq_info->nrxq; i++) {
 318                 struct sge_ofld_rxq *r = &rxq_info->uldrxq[i];
 319
 320                 init_rspq(adap, &r->rspq, 5, 1, uld_info->rxq_size, 64);
 321                 r->rspq.uld = uld_type;
 322                 r->fl.size = 72;
 323         }
 324
 325         ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
 326         if (ciq_size > SGE_MAX_IQ_SIZE) {
 327                 dev_warn(adap->pdev_dev, "CIQ size too small for available IQs\n");
 328                 ciq_size = SGE_MAX_IQ_SIZE;
 329         }
 330
 331         for (i = rxq_info->nrxq; i < nrxq; i++) {
 332                 struct sge_ofld_rxq *r = &rxq_info->uldrxq[i];
 333
 334                 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
 335                 r->rspq.uld = uld_type;
 336         }
 337
 338         memcpy(rxq_info->name, uld_info->name, IFNAMSIZ);
 339         adap->sge.uld_rxq_info[uld_type] = rxq_info;
 340
 341         return 0;
 342 }
 343
 344 void free_queues_uld(struct adapter *adap, unsigned int uld_type)
 345 {
 346         struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
 347
 348         kfree(rxq_info->rspq_id);
 349         kfree(rxq_info->uldrxq);
 350         kfree(rxq_info);
 351 }
 352
 353 int request_msix_queue_irqs_uld(struct adapter *adap, unsigned int uld_type)
 354 {
 355         struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
 356         int err = 0;
 357         unsigned int idx, bmap_idx;
 358
 359         for_each_uldrxq(rxq_info, idx) {
 360                 bmap_idx = rxq_info->msix_tbl[idx];
 361                 err = request_irq(adap->msix_info_ulds[bmap_idx].vec,
 362                                   t4_sge_intr_msix, 0,
 363                                   adap->msix_info_ulds[bmap_idx].desc,
 364                                   &rxq_info->uldrxq[idx].rspq);
 365                 if (err)
 366                         goto unwind;
 367         }
 368         return 0;
 369 unwind:
 370         while (--idx >= 0) {
 371                 bmap_idx = rxq_info->msix_tbl[idx];
 372                 free_msix_idx_in_bmap(adap, bmap_idx);
 373                 free_irq(adap->msix_info_ulds[bmap_idx].vec,
 374                          &rxq_info->uldrxq[idx].rspq);
 375         }
 376         return err;
 377 }
 378
 379 void free_msix_queue_irqs_uld(struct adapter *adap, unsigned int uld_type)
 380 {
 381         struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
 382         unsigned int idx, bmap_idx;
 383
 384         for_each_uldrxq(rxq_info, idx) {
 385                 bmap_idx = rxq_info->msix_tbl[idx];
 386
 387                 free_msix_idx_in_bmap(adap, bmap_idx);
 388                 free_irq(adap->msix_info_ulds[bmap_idx].vec,
 389                          &rxq_info->uldrxq[idx].rspq);
 390         }
 391 }
 392
 393 void name_msix_vecs_uld(struct adapter *adap, unsigned int uld_type)
 394 {
 395         struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
 396         int n = sizeof(adap->msix_info_ulds[0].desc);
 397         unsigned int idx, bmap_idx;
 398
 399         for_each_uldrxq(rxq_info, idx) {
 400                 bmap_idx = rxq_info->msix_tbl[idx];
 401
 402                 snprintf(adap->msix_info_ulds[bmap_idx].desc, n, "%s-%s%d",
 403                          adap->port[0]->name, rxq_info->name, idx);
 404         }
 405 }
 406
 407 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
 408 {
 409         if (!q)
 410                 return;
 411
 412         if (q->handler) {
 413                 cxgb_busy_poll_init_lock(q);
 414                 napi_enable(&q->napi);
 415         }
 416         /* 0-increment GTS to start the timer and enable interrupts */
 417         t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
 418                      SEINTARM_V(q->intr_params) |
 419                      INGRESSQID_V(q->cntxt_id));
 420 }
 421
 422 static void quiesce_rx(struct adapter *adap, struct sge_rspq *q)
 423 {
 424         if (q && q->handler) {
 425                 napi_disable(&q->napi);
 426                 local_bh_disable();
 427                 while (!cxgb_poll_lock_napi(q))
 428                         mdelay(1);
 429                 local_bh_enable();
 430         }
 431 }
 432
 433 void enable_rx_uld(struct adapter *adap, unsigned int uld_type)
 434 {
 435         struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
 436         int idx;
 437
 438         for_each_uldrxq(rxq_info, idx)
 439                 enable_rx(adap, &rxq_info->uldrxq[idx].rspq);
 440 }
 441
 442 void quiesce_rx_uld(struct adapter *adap, unsigned int uld_type)
 443 {
 444         struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
 445         int idx;
 446
 447         for_each_uldrxq(rxq_info, idx)
 448                 quiesce_rx(adap, &rxq_info->uldrxq[idx].rspq);
 449 }
 450
 451 static void uld_queue_init(struct adapter *adap, unsigned int uld_type,
 452                            struct cxgb4_lld_info *lli)
 453 {
 454         struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
 455
 456         lli->rxq_ids = rxq_info->rspq_id;
 457         lli->nrxq = rxq_info->nrxq;
 458         lli->ciq_ids = rxq_info->rspq_id + rxq_info->nrxq;
 459         lli->nciq = rxq_info->nciq;
 460 }
 461
 462 int t4_uld_mem_alloc(struct adapter *adap)
 463 {
 464         struct sge *s = &adap->sge;
 465
 466         adap->uld = kcalloc(CXGB4_ULD_MAX, sizeof(*adap->uld), GFP_KERNEL);
 467         if (!adap->uld)
 468                 return -ENOMEM;
 469
 470         s->uld_rxq_info = kzalloc(CXGB4_ULD_MAX *
 471                                   sizeof(struct sge_uld_rxq_info *),
 472                                   GFP_KERNEL);
 473         if (!s->uld_rxq_info)
 474                 goto err_uld;
 475
 476         return 0;
 477 err_uld:
 478         kfree(adap->uld);
 479         return -ENOMEM;
 480 }
 481
 482 void t4_uld_mem_free(struct adapter *adap)
 483 {
 484         struct sge *s = &adap->sge;
 485
 486         kfree(s->uld_rxq_info);
 487         kfree(adap->uld);
 488 }
 489
 490 void t4_uld_clean_up(struct adapter *adap)
 491 {
 492         struct sge_uld_rxq_info *rxq_info;
 493         unsigned int i;
 494
 495         if (!adap->uld)
 496                 return;
 497         for (i = 0; i < CXGB4_ULD_MAX; i++) {
 498                 if (!adap->uld[i].handle)
 499                         continue;
 500                 rxq_info = adap->sge.uld_rxq_info[i];
 501                 if (adap->flags & FULL_INIT_DONE)
 502                         quiesce_rx_uld(adap, i);
 503                 if (adap->flags & USING_MSIX)
 504                         free_msix_queue_irqs_uld(adap, i);
 505                 free_sge_queues_uld(adap, i);
 506                 free_queues_uld(adap, i);
 507         }
 508 }
 509
 510 static void uld_init(struct adapter *adap, struct cxgb4_lld_info *lld)
 511 {
 512         int i;
 513
 514         lld->pdev = adap->pdev;
 515         lld->pf = adap->pf;
 516         lld->l2t = adap->l2t;
 517         lld->tids = &adap->tids;
 518         lld->ports = adap->port;
 519         lld->vr = &adap->vres;
 520         lld->mtus = adap->params.mtus;
 521         lld->ntxq = adap->sge.ofldqsets;
 522         lld->nchan = adap->params.nports;
 523         lld->nports = adap->params.nports;
 524         lld->wr_cred = adap->params.ofldq_wr_cred;
 525         lld->iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A));
 526         lld->iscsi_tagmask = t4_read_reg(adap, ULP_RX_ISCSI_TAGMASK_A);
 527         lld->iscsi_pgsz_order = t4_read_reg(adap, ULP_RX_ISCSI_PSZ_A);
 528         lld->iscsi_llimit = t4_read_reg(adap, ULP_RX_ISCSI_LLIMIT_A);
 529         lld->iscsi_ppm = &adap->iscsi_ppm;
 530         lld->adapter_type = adap->params.chip;
 531         lld->cclk_ps = 1000000000 / adap->params.vpd.cclk;
 532         lld->udb_density = 1 << adap->params.sge.eq_qpp;
 533         lld->ucq_density = 1 << adap->params.sge.iq_qpp;
 534         lld->filt_mode = adap->params.tp.vlan_pri_map;
 535         /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
 536         for (i = 0; i < NCHAN; i++)
 537                 lld->tx_modq[i] = i;
 538         lld->gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A);
 539         lld->db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);
 540         lld->fw_vers = adap->params.fw_vers;
 541         lld->dbfifo_int_thresh = dbfifo_int_thresh;
 542         lld->sge_ingpadboundary = adap->sge.fl_align;
 543         lld->sge_egrstatuspagesize = adap->sge.stat_len;
 544         lld->sge_pktshift = adap->sge.pktshift;
 545         lld->enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
 546         lld->max_ordird_qp = adap->params.max_ordird_qp;
 547         lld->max_ird_adapter = adap->params.max_ird_adapter;
 548         lld->ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
 549         lld->nodeid = dev_to_node(adap->pdev_dev);
 550 }
 551
 552 static void uld_attach(struct adapter *adap, unsigned int uld)
 553 {
 554         void *handle;
 555         struct cxgb4_lld_info lli;
 556
 557         uld_init(adap, &lli);
 558         uld_queue_init(adap, uld, &lli);
 559
 560         handle = adap->uld[uld].add(&lli);
 561         if (IS_ERR(handle)) {
 562                 dev_warn(adap->pdev_dev,
 563                          "could not attach to the %s driver, error %ld\n",
 564                          adap->uld[uld].name, PTR_ERR(handle));
 565                 return;
 566         }
 567
 568         adap->uld[uld].handle = handle;
 569         t4_register_netevent_notifier();
 570
 571         if (adap->flags & FULL_INIT_DONE)
 572                 adap->uld[uld].state_change(handle, CXGB4_STATE_UP);
 573 }
 574
 575 /**
 576  *      cxgb4_register_uld - register an upper-layer driver
 577  *      @type: the ULD type
 578  *      @p: the ULD methods
 579  *
 580  *      Registers an upper-layer driver with this driver and notifies the ULD
 581  *      about any presently available devices that support its type.  Returns
 582  *      %-EBUSY if a ULD of the same type is already registered.
 583  */
 584 int cxgb4_register_uld(enum cxgb4_uld type,
 585                        const struct cxgb4_uld_info *p)
 586 {
 587         int ret = 0;
 588         unsigned int adap_idx = 0;
 589         struct adapter *adap;
 590
 591         if (type >= CXGB4_ULD_MAX)
 592                 return -EINVAL;
 593
 594         mutex_lock(&uld_mutex);
 595         list_for_each_entry(adap, &adapter_list, list_node) {
 596                 if ((type == CXGB4_ULD_CRYPTO && !is_pci_uld(adap)) ||
 597                     (type != CXGB4_ULD_CRYPTO && !is_offload(adap)))
 598                         continue;
 599                 if (type == CXGB4_ULD_ISCSIT && is_t4(adap->params.chip))
 600                         continue;
 601                 ret = cfg_queues_uld(adap, type, p);
 602                 if (ret)
 603                         goto out;
 604                 ret = setup_sge_queues_uld(adap, type, p->lro);
 605                 if (ret)
 606                         goto free_queues;
 607                 if (adap->flags & USING_MSIX) {
 608                         name_msix_vecs_uld(adap, type);
 609                         ret = request_msix_queue_irqs_uld(adap, type);
 610                         if (ret)
 611                                 goto free_rxq;
 612                 }
 613                 if (adap->flags & FULL_INIT_DONE)
 614                         enable_rx_uld(adap, type);
 615                 if (adap->uld[type].add) {
 616                         ret = -EBUSY;
 617                         goto free_irq;
 618                 }
 619                 adap->uld[type] = *p;
 620                 uld_attach(adap, type);
 621                 adap_idx++;
 622         }
 623         mutex_unlock(&uld_mutex);
 624         return 0;
 625
 626 free_irq:
 627         if (adap->flags & FULL_INIT_DONE)
 628                 quiesce_rx_uld(adap, type);
 629         if (adap->flags & USING_MSIX)
 630                 free_msix_queue_irqs_uld(adap, type);
 631 free_rxq:
 632         free_sge_queues_uld(adap, type);
 633 free_queues:
 634         free_queues_uld(adap, type);
 635 out:
 636
 637         list_for_each_entry(adap, &adapter_list, list_node) {
 638                 if ((type == CXGB4_ULD_CRYPTO && !is_pci_uld(adap)) ||
 639                     (type != CXGB4_ULD_CRYPTO && !is_offload(adap)))
 640                         continue;
 641                 if (type == CXGB4_ULD_ISCSIT && is_t4(adap->params.chip))
 642                         continue;
 643                 if (!adap_idx)
 644                         break;
 645                 adap->uld[type].handle = NULL;
 646                 adap->uld[type].add = NULL;
 647                 if (adap->flags & FULL_INIT_DONE)
 648                         quiesce_rx_uld(adap, type);
 649                 if (adap->flags & USING_MSIX)
 650                         free_msix_queue_irqs_uld(adap, type);
 651                 free_sge_queues_uld(adap, type);
 652                 free_queues_uld(adap, type);
 653                 adap_idx--;
 654         }
 655         mutex_unlock(&uld_mutex);
 656         return ret;
 657 }
 658 EXPORT_SYMBOL(cxgb4_register_uld);
 659
 660 /**
 661  *      cxgb4_unregister_uld - unregister an upper-layer driver
 662  *      @type: the ULD type
 663  *
 664  *      Unregisters an existing upper-layer driver.
 665  */
 666 int cxgb4_unregister_uld(enum cxgb4_uld type)
 667 {
 668         struct adapter *adap;
 669
 670         if (type >= CXGB4_ULD_MAX)
 671                 return -EINVAL;
 672
 673         mutex_lock(&uld_mutex);
 674         list_for_each_entry(adap, &adapter_list, list_node) {
 675                 if ((type == CXGB4_ULD_CRYPTO && !is_pci_uld(adap)) ||
 676                     (type != CXGB4_ULD_CRYPTO && !is_offload(adap)))
 677                         continue;
 678                 if (type == CXGB4_ULD_ISCSIT && is_t4(adap->params.chip))
 679                         continue;
 680                 adap->uld[type].handle = NULL;
 681                 adap->uld[type].add = NULL;
 682                 if (adap->flags & FULL_INIT_DONE)
 683                         quiesce_rx_uld(adap, type);
 684                 if (adap->flags & USING_MSIX)
 685                         free_msix_queue_irqs_uld(adap, type);
 686                 free_sge_queues_uld(adap, type);
 687                 free_queues_uld(adap, type);
 688         }
 689         mutex_unlock(&uld_mutex);
 690
 691         return 0;
 692 }
 693 EXPORT_SYMBOL(cxgb4_unregister_uld);