drivers/net/wireless/ath/ath10k/ce.c

   1 /*
   2  * Copyright (c) 2005-2011 Atheros Communications Inc.
   3  * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  */
  17
  18 #include "hif.h"
  19 #include "pci.h"
  20 #include "ce.h"
  21 #include "debug.h"
  22
  23 /*
  24  * Support for Copy Engine hardware, which is mainly used for
  25  * communication between Host and Target over a PCIe interconnect.
  26  */
  27
  28 /*
  29  * A single CopyEngine (CE) comprises two "rings":
  30  *   a source ring
  31  *   a destination ring
  32  *
  33  * Each ring consists of a number of descriptors which specify
  34  * an address, length, and meta-data.
  35  *
  36  * Typically, one side of the PCIe interconnect (Host or Target)
  37  * controls one ring and the other side controls the other ring.
  38  * The source side chooses when to initiate a transfer and it
  39  * chooses what to send (buffer address, length). The destination
  40  * side keeps a supply of "anonymous receive buffers" available and
  41  * it handles incoming data as it arrives (when the destination
  42  * recieves an interrupt).
  43  *
  44  * The sender may send a simple buffer (address/length) or it may
  45  * send a small list of buffers.  When a small list is sent, hardware
  46  * "gathers" these and they end up in a single destination buffer
  47  * with a single interrupt.
  48  *
  49  * There are several "contexts" managed by this layer -- more, it
  50  * may seem -- than should be needed. These are provided mainly for
  51  * maximum flexibility and especially to facilitate a simpler HIF
  52  * implementation. There are per-CopyEngine recv, send, and watermark
  53  * contexts. These are supplied by the caller when a recv, send,
  54  * or watermark handler is established and they are echoed back to
  55  * the caller when the respective callbacks are invoked. There is
  56  * also a per-transfer context supplied by the caller when a buffer
  57  * (or sendlist) is sent and when a buffer is enqueued for recv.
  58  * These per-transfer contexts are echoed back to the caller when
  59  * the buffer is sent/received.
  60  */
  61
  62 static inline void ath10k_ce_dest_ring_write_index_set(struct ath10k *ar,
  63                                                        u32 ce_ctrl_addr,
  64                                                        unsigned int n)
  65 {
  66         ath10k_pci_write32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS, n);
  67 }
  68
  69 static inline u32 ath10k_ce_dest_ring_write_index_get(struct ath10k *ar,
  70                                                       u32 ce_ctrl_addr)
  71 {
  72         return ath10k_pci_read32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS);
  73 }
  74
  75 static inline void ath10k_ce_src_ring_write_index_set(struct ath10k *ar,
  76                                                       u32 ce_ctrl_addr,
  77                                                       unsigned int n)
  78 {
  79         ath10k_pci_write32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS, n);
  80 }
  81
  82 static inline u32 ath10k_ce_src_ring_write_index_get(struct ath10k *ar,
  83                                                      u32 ce_ctrl_addr)
  84 {
  85         return ath10k_pci_read32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS);
  86 }
  87
  88 static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar,
  89                                                     u32 ce_ctrl_addr)
  90 {
  91         return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_SRRI_ADDRESS);
  92 }
  93
  94 static inline void ath10k_ce_src_ring_base_addr_set(struct ath10k *ar,
  95                                                     u32 ce_ctrl_addr,
  96                                                     unsigned int addr)
  97 {
  98         ath10k_pci_write32(ar, ce_ctrl_addr + SR_BA_ADDRESS, addr);
  99 }
 100
 101 static inline void ath10k_ce_src_ring_size_set(struct ath10k *ar,
 102                                                u32 ce_ctrl_addr,
 103                                                unsigned int n)
 104 {
 105         ath10k_pci_write32(ar, ce_ctrl_addr + SR_SIZE_ADDRESS, n);
 106 }
 107
 108 static inline void ath10k_ce_src_ring_dmax_set(struct ath10k *ar,
 109                                                u32 ce_ctrl_addr,
 110                                                unsigned int n)
 111 {
 112         u32 ctrl1_addr = ath10k_pci_read32((ar),
 113                                            (ce_ctrl_addr) + CE_CTRL1_ADDRESS);
 114
 115         ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,
 116                            (ctrl1_addr &  ~CE_CTRL1_DMAX_LENGTH_MASK) |
 117                            CE_CTRL1_DMAX_LENGTH_SET(n));
 118 }
 119
 120 static inline void ath10k_ce_src_ring_byte_swap_set(struct ath10k *ar,
 121                                                     u32 ce_ctrl_addr,
 122                                                     unsigned int n)
 123 {
 124         u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS);
 125
 126         ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,
 127                            (ctrl1_addr & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) |
 128                            CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n));
 129 }
 130
 131 static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar,
 132                                                      u32 ce_ctrl_addr,
 133                                                      unsigned int n)
 134 {
 135         u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS);
 136
 137         ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,
 138                            (ctrl1_addr & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) |
 139                            CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n));
 140 }
 141
 142 static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar,
 143                                                      u32 ce_ctrl_addr)
 144 {
 145         return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_DRRI_ADDRESS);
 146 }
 147
 148 static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar,
 149                                                      u32 ce_ctrl_addr,
 150                                                      u32 addr)
 151 {
 152         ath10k_pci_write32(ar, ce_ctrl_addr + DR_BA_ADDRESS, addr);
 153 }
 154
 155 static inline void ath10k_ce_dest_ring_size_set(struct ath10k *ar,
 156                                                 u32 ce_ctrl_addr,
 157                                                 unsigned int n)
 158 {
 159         ath10k_pci_write32(ar, ce_ctrl_addr + DR_SIZE_ADDRESS, n);
 160 }
 161
 162 static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar,
 163                                                    u32 ce_ctrl_addr,
 164                                                    unsigned int n)
 165 {
 166         u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS);
 167
 168         ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,
 169                            (addr & ~SRC_WATERMARK_HIGH_MASK) |
 170                            SRC_WATERMARK_HIGH_SET(n));
 171 }
 172
 173 static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar,
 174                                                   u32 ce_ctrl_addr,
 175                                                   unsigned int n)
 176 {
 177         u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS);
 178
 179         ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,
 180                            (addr & ~SRC_WATERMARK_LOW_MASK) |
 181                            SRC_WATERMARK_LOW_SET(n));
 182 }
 183
 184 static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar,
 185                                                     u32 ce_ctrl_addr,
 186                                                     unsigned int n)
 187 {
 188         u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS);
 189
 190         ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,
 191                            (addr & ~DST_WATERMARK_HIGH_MASK) |
 192                            DST_WATERMARK_HIGH_SET(n));
 193 }
 194
 195 static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar,
 196                                                    u32 ce_ctrl_addr,
 197                                                    unsigned int n)
 198 {
 199         u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS);
 200
 201         ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,
 202                            (addr & ~DST_WATERMARK_LOW_MASK) |
 203                            DST_WATERMARK_LOW_SET(n));
 204 }
 205
 206 static inline void ath10k_ce_copy_complete_inter_enable(struct ath10k *ar,
 207                                                         u32 ce_ctrl_addr)
 208 {
 209         u32 host_ie_addr = ath10k_pci_read32(ar,
 210                                              ce_ctrl_addr + HOST_IE_ADDRESS);
 211
 212         ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,
 213                            host_ie_addr | HOST_IE_COPY_COMPLETE_MASK);
 214 }
 215
 216 static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar,
 217                                                         u32 ce_ctrl_addr)
 218 {
 219         u32 host_ie_addr = ath10k_pci_read32(ar,
 220                                              ce_ctrl_addr + HOST_IE_ADDRESS);
 221
 222         ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,
 223                            host_ie_addr & ~HOST_IE_COPY_COMPLETE_MASK);
 224 }
 225
 226 static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar,
 227                                                     u32 ce_ctrl_addr)
 228 {
 229         u32 host_ie_addr = ath10k_pci_read32(ar,
 230                                              ce_ctrl_addr + HOST_IE_ADDRESS);
 231
 232         ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,
 233                            host_ie_addr & ~CE_WATERMARK_MASK);
 234 }
 235
 236 static inline void ath10k_ce_error_intr_enable(struct ath10k *ar,
 237                                                u32 ce_ctrl_addr)
 238 {
 239         u32 misc_ie_addr = ath10k_pci_read32(ar,
 240                                              ce_ctrl_addr + MISC_IE_ADDRESS);
 241
 242         ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,
 243                            misc_ie_addr | CE_ERROR_MASK);
 244 }
 245
 246 static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar,
 247                                                      u32 ce_ctrl_addr,
 248                                                      unsigned int mask)
 249 {
 250         ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IS_ADDRESS, mask);
 251 }
 252
 253
 254 /*
 255  * Guts of ath10k_ce_send, used by both ath10k_ce_send and
 256  * ath10k_ce_sendlist_send.
 257  * The caller takes responsibility for any needed locking.
 258  */
 259 static int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
 260                                  void *per_transfer_context,
 261                                  u32 buffer,
 262                                  unsigned int nbytes,
 263                                  unsigned int transfer_id,
 264                                  unsigned int flags)
 265 {
 266         struct ath10k *ar = ce_state->ar;
 267         struct ath10k_ce_ring *src_ring = ce_state->src_ring;
 268         struct ce_desc *desc, *sdesc;
 269         unsigned int nentries_mask = src_ring->nentries_mask;
 270         unsigned int sw_index = src_ring->sw_index;
 271         unsigned int write_index = src_ring->write_index;
 272         u32 ctrl_addr = ce_state->ctrl_addr;
 273         u32 desc_flags = 0;
 274         int ret = 0;
 275
 276         if (nbytes > ce_state->src_sz_max)
 277                 ath10k_warn("%s: send more we can (nbytes: %d, max: %d)\n",
 278                             __func__, nbytes, ce_state->src_sz_max);
 279
 280         ret = ath10k_pci_wake(ar);
 281         if (ret)
 282                 return ret;
 283
 284         if (unlikely(CE_RING_DELTA(nentries_mask,
 285                                    write_index, sw_index - 1) <= 0)) {
 286                 ret = -EIO;
 287                 goto exit;
 288         }
 289
 290         desc = CE_SRC_RING_TO_DESC(src_ring->base_addr_owner_space,
 291                                    write_index);
 292         sdesc = CE_SRC_RING_TO_DESC(src_ring->shadow_base, write_index);
 293
 294         desc_flags |= SM(transfer_id, CE_DESC_FLAGS_META_DATA);
 295
 296         if (flags & CE_SEND_FLAG_GATHER)
 297                 desc_flags |= CE_DESC_FLAGS_GATHER;
 298         if (flags & CE_SEND_FLAG_BYTE_SWAP)
 299                 desc_flags |= CE_DESC_FLAGS_BYTE_SWAP;
 300
 301         sdesc->addr   = __cpu_to_le32(buffer);
 302         sdesc->nbytes = __cpu_to_le16(nbytes);
 303         sdesc->flags  = __cpu_to_le16(desc_flags);
 304
 305         *desc = *sdesc;
 306
 307         src_ring->per_transfer_context[write_index] = per_transfer_context;
 308
 309         /* Update Source Ring Write Index */
 310         write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
 311
 312         /* WORKAROUND */
 313         if (!(flags & CE_SEND_FLAG_GATHER))
 314                 ath10k_ce_src_ring_write_index_set(ar, ctrl_addr, write_index);
 315
 316         src_ring->write_index = write_index;
 317 exit:
 318         ath10k_pci_sleep(ar);
 319         return ret;
 320 }
 321
 322 int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
 323                    void *per_transfer_context,
 324                    u32 buffer,
 325                    unsigned int nbytes,
 326                    unsigned int transfer_id,
 327                    unsigned int flags)
 328 {
 329         struct ath10k *ar = ce_state->ar;
 330         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 331         int ret;
 332
 333         spin_lock_bh(&ar_pci->ce_lock);
 334         ret = ath10k_ce_send_nolock(ce_state, per_transfer_context,
 335                                     buffer, nbytes, transfer_id, flags);
 336         spin_unlock_bh(&ar_pci->ce_lock);
 337
 338         return ret;
 339 }
 340
 341 int ath10k_ce_sendlist_send(struct ath10k_ce_pipe *ce_state,
 342                             void *per_transfer_context,
 343                             unsigned int transfer_id,
 344                             u32 paddr, unsigned int nbytes,
 345                             u32 flags)
 346 {
 347         struct ath10k_ce_ring *src_ring = ce_state->src_ring;
 348         struct ath10k *ar = ce_state->ar;
 349         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 350         unsigned int nentries_mask = src_ring->nentries_mask;
 351         unsigned int sw_index;
 352         unsigned int write_index;
 353         int delta, ret = -ENOMEM;
 354
 355         spin_lock_bh(&ar_pci->ce_lock);
 356
 357         sw_index = src_ring->sw_index;
 358         write_index = src_ring->write_index;
 359
 360         delta = CE_RING_DELTA(nentries_mask, write_index, sw_index - 1);
 361
 362         if (delta >= 1) {
 363                 ret = ath10k_ce_send_nolock(ce_state, per_transfer_context,
 364                                             paddr, nbytes,
 365                                             transfer_id, flags);
 366                 if (ret)
 367                         ath10k_warn("CE send failed: %d\n", ret);
 368         }
 369
 370         spin_unlock_bh(&ar_pci->ce_lock);
 371
 372         return ret;
 373 }
 374
 375 int ath10k_ce_recv_buf_enqueue(struct ath10k_ce_pipe *ce_state,
 376                                void *per_recv_context,
 377                                u32 buffer)
 378 {
 379         struct ath10k_ce_ring *dest_ring = ce_state->dest_ring;
 380         u32 ctrl_addr = ce_state->ctrl_addr;
 381         struct ath10k *ar = ce_state->ar;
 382         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 383         unsigned int nentries_mask = dest_ring->nentries_mask;
 384         unsigned int write_index;
 385         unsigned int sw_index;
 386         int ret;
 387
 388         spin_lock_bh(&ar_pci->ce_lock);
 389         write_index = dest_ring->write_index;
 390         sw_index = dest_ring->sw_index;
 391
 392         ret = ath10k_pci_wake(ar);
 393         if (ret)
 394                 goto out;
 395
 396         if (CE_RING_DELTA(nentries_mask, write_index, sw_index - 1) > 0) {
 397                 struct ce_desc *base = dest_ring->base_addr_owner_space;
 398                 struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, write_index);
 399
 400                 /* Update destination descriptor */
 401                 desc->addr    = __cpu_to_le32(buffer);
 402                 desc->nbytes = 0;
 403
 404                 dest_ring->per_transfer_context[write_index] =
 405                                                         per_recv_context;
 406
 407                 /* Update Destination Ring Write Index */
 408                 write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
 409                 ath10k_ce_dest_ring_write_index_set(ar, ctrl_addr, write_index);
 410                 dest_ring->write_index = write_index;
 411                 ret = 0;
 412         } else {
 413                 ret = -EIO;
 414         }
 415         ath10k_pci_sleep(ar);
 416
 417 out:
 418         spin_unlock_bh(&ar_pci->ce_lock);
 419
 420         return ret;
 421 }
 422
 423 /*
 424  * Guts of ath10k_ce_completed_recv_next.
 425  * The caller takes responsibility for any necessary locking.
 426  */
 427 static int ath10k_ce_completed_recv_next_nolock(struct ath10k_ce_pipe *ce_state,
 428                                                 void **per_transfer_contextp,
 429                                                 u32 *bufferp,
 430                                                 unsigned int *nbytesp,
 431                                                 unsigned int *transfer_idp,
 432                                                 unsigned int *flagsp)
 433 {
 434         struct ath10k_ce_ring *dest_ring = ce_state->dest_ring;
 435         unsigned int nentries_mask = dest_ring->nentries_mask;
 436         unsigned int sw_index = dest_ring->sw_index;
 437
 438         struct ce_desc *base = dest_ring->base_addr_owner_space;
 439         struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, sw_index);
 440         struct ce_desc sdesc;
 441         u16 nbytes;
 442
 443         /* Copy in one go for performance reasons */
 444         sdesc = *desc;
 445
 446         nbytes = __le16_to_cpu(sdesc.nbytes);
 447         if (nbytes == 0) {
 448                 /*
 449                  * This closes a relatively unusual race where the Host
 450                  * sees the updated DRRI before the update to the
 451                  * corresponding descriptor has completed. We treat this
 452                  * as a descriptor that is not yet done.
 453                  */
 454                 return -EIO;
 455         }
 456
 457         desc->nbytes = 0;
 458
 459         /* Return data from completed destination descriptor */
 460         *bufferp = __le32_to_cpu(sdesc.addr);
 461         *nbytesp = nbytes;
 462         *transfer_idp = MS(__le16_to_cpu(sdesc.flags), CE_DESC_FLAGS_META_DATA);
 463
 464         if (__le16_to_cpu(sdesc.flags) & CE_DESC_FLAGS_BYTE_SWAP)
 465                 *flagsp = CE_RECV_FLAG_SWAPPED;
 466         else
 467                 *flagsp = 0;
 468
 469         if (per_transfer_contextp)
 470                 *per_transfer_contextp =
 471                         dest_ring->per_transfer_context[sw_index];
 472
 473         /* sanity */
 474         dest_ring->per_transfer_context[sw_index] = NULL;
 475
 476         /* Update sw_index */
 477         sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
 478         dest_ring->sw_index = sw_index;
 479
 480         return 0;
 481 }
 482
 483 int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state,
 484                                   void **per_transfer_contextp,
 485                                   u32 *bufferp,
 486                                   unsigned int *nbytesp,
 487                                   unsigned int *transfer_idp,
 488                                   unsigned int *flagsp)
 489 {
 490         struct ath10k *ar = ce_state->ar;
 491         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 492         int ret;
 493
 494         spin_lock_bh(&ar_pci->ce_lock);
 495         ret = ath10k_ce_completed_recv_next_nolock(ce_state,
 496                                                    per_transfer_contextp,
 497                                                    bufferp, nbytesp,
 498                                                    transfer_idp, flagsp);
 499         spin_unlock_bh(&ar_pci->ce_lock);
 500
 501         return ret;
 502 }
 503
 504 int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state,
 505                                void **per_transfer_contextp,
 506                                u32 *bufferp)
 507 {
 508         struct ath10k_ce_ring *dest_ring;
 509         unsigned int nentries_mask;
 510         unsigned int sw_index;
 511         unsigned int write_index;
 512         int ret;
 513         struct ath10k *ar;
 514         struct ath10k_pci *ar_pci;
 515
 516         dest_ring = ce_state->dest_ring;
 517
 518         if (!dest_ring)
 519                 return -EIO;
 520
 521         ar = ce_state->ar;
 522         ar_pci = ath10k_pci_priv(ar);
 523
 524         spin_lock_bh(&ar_pci->ce_lock);
 525
 526         nentries_mask = dest_ring->nentries_mask;
 527         sw_index = dest_ring->sw_index;
 528         write_index = dest_ring->write_index;
 529         if (write_index != sw_index) {
 530                 struct ce_desc *base = dest_ring->base_addr_owner_space;
 531                 struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, sw_index);
 532
 533                 /* Return data from completed destination descriptor */
 534                 *bufferp = __le32_to_cpu(desc->addr);
 535
 536                 if (per_transfer_contextp)
 537                         *per_transfer_contextp =
 538                                 dest_ring->per_transfer_context[sw_index];
 539
 540                 /* sanity */
 541                 dest_ring->per_transfer_context[sw_index] = NULL;
 542
 543                 /* Update sw_index */
 544                 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
 545                 dest_ring->sw_index = sw_index;
 546                 ret = 0;
 547         } else {
 548                 ret = -EIO;
 549         }
 550
 551         spin_unlock_bh(&ar_pci->ce_lock);
 552
 553         return ret;
 554 }
 555
 556 /*
 557  * Guts of ath10k_ce_completed_send_next.
 558  * The caller takes responsibility for any necessary locking.
 559  */
 560 static int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state,
 561                                                 void **per_transfer_contextp,
 562                                                 u32 *bufferp,
 563                                                 unsigned int *nbytesp,
 564                                                 unsigned int *transfer_idp)
 565 {
 566         struct ath10k_ce_ring *src_ring = ce_state->src_ring;
 567         u32 ctrl_addr = ce_state->ctrl_addr;
 568         struct ath10k *ar = ce_state->ar;
 569         unsigned int nentries_mask = src_ring->nentries_mask;
 570         unsigned int sw_index = src_ring->sw_index;
 571         struct ce_desc *sdesc, *sbase;
 572         unsigned int read_index;
 573         int ret;
 574
 575         if (src_ring->hw_index == sw_index) {
 576                 /*
 577                  * The SW completion index has caught up with the cached
 578                  * version of the HW completion index.
 579                  * Update the cached HW completion index to see whether
 580                  * the SW has really caught up to the HW, or if the cached
 581                  * value of the HW index has become stale.
 582                  */
 583
 584                 ret = ath10k_pci_wake(ar);
 585                 if (ret)
 586                         return ret;
 587
 588                 src_ring->hw_index =
 589                         ath10k_ce_src_ring_read_index_get(ar, ctrl_addr);
 590                 src_ring->hw_index &= nentries_mask;
 591
 592                 ath10k_pci_sleep(ar);
 593         }
 594
 595         read_index = src_ring->hw_index;
 596
 597         if ((read_index == sw_index) || (read_index == 0xffffffff))
 598                 return -EIO;
 599
 600         sbase = src_ring->shadow_base;
 601         sdesc = CE_SRC_RING_TO_DESC(sbase, sw_index);
 602
 603         /* Return data from completed source descriptor */
 604         *bufferp = __le32_to_cpu(sdesc->addr);
 605         *nbytesp = __le16_to_cpu(sdesc->nbytes);
 606         *transfer_idp = MS(__le16_to_cpu(sdesc->flags),
 607                            CE_DESC_FLAGS_META_DATA);
 608
 609         if (per_transfer_contextp)
 610                 *per_transfer_contextp =
 611                         src_ring->per_transfer_context[sw_index];
 612
 613         /* sanity */
 614         src_ring->per_transfer_context[sw_index] = NULL;
 615
 616         /* Update sw_index */
 617         sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
 618         src_ring->sw_index = sw_index;
 619
 620         return 0;
 621 }
 622
 623 /* NB: Modeled after ath10k_ce_completed_send_next */
 624 int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
 625                                void **per_transfer_contextp,
 626                                u32 *bufferp,
 627                                unsigned int *nbytesp,
 628                                unsigned int *transfer_idp)
 629 {
 630         struct ath10k_ce_ring *src_ring;
 631         unsigned int nentries_mask;
 632         unsigned int sw_index;
 633         unsigned int write_index;
 634         int ret;
 635         struct ath10k *ar;
 636         struct ath10k_pci *ar_pci;
 637
 638         src_ring = ce_state->src_ring;
 639
 640         if (!src_ring)
 641                 return -EIO;
 642
 643         ar = ce_state->ar;
 644         ar_pci = ath10k_pci_priv(ar);
 645
 646         spin_lock_bh(&ar_pci->ce_lock);
 647
 648         nentries_mask = src_ring->nentries_mask;
 649         sw_index = src_ring->sw_index;
 650         write_index = src_ring->write_index;
 651
 652         if (write_index != sw_index) {
 653                 struct ce_desc *base = src_ring->base_addr_owner_space;
 654                 struct ce_desc *desc = CE_SRC_RING_TO_DESC(base, sw_index);
 655
 656                 /* Return data from completed source descriptor */
 657                 *bufferp = __le32_to_cpu(desc->addr);
 658                 *nbytesp = __le16_to_cpu(desc->nbytes);
 659                 *transfer_idp = MS(__le16_to_cpu(desc->flags),
 660                                                 CE_DESC_FLAGS_META_DATA);
 661
 662                 if (per_transfer_contextp)
 663                         *per_transfer_contextp =
 664                                 src_ring->per_transfer_context[sw_index];
 665
 666                 /* sanity */
 667                 src_ring->per_transfer_context[sw_index] = NULL;
 668
 669                 /* Update sw_index */
 670                 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
 671                 src_ring->sw_index = sw_index;
 672                 ret = 0;
 673         } else {
 674                 ret = -EIO;
 675         }
 676
 677         spin_unlock_bh(&ar_pci->ce_lock);
 678
 679         return ret;
 680 }
 681
 682 int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
 683                                   void **per_transfer_contextp,
 684                                   u32 *bufferp,
 685                                   unsigned int *nbytesp,
 686                                   unsigned int *transfer_idp)
 687 {
 688         struct ath10k *ar = ce_state->ar;
 689         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 690         int ret;
 691
 692         spin_lock_bh(&ar_pci->ce_lock);
 693         ret = ath10k_ce_completed_send_next_nolock(ce_state,
 694                                                    per_transfer_contextp,
 695                                                    bufferp, nbytesp,
 696                                                    transfer_idp);
 697         spin_unlock_bh(&ar_pci->ce_lock);
 698
 699         return ret;
 700 }
 701
 702 /*
 703  * Guts of interrupt handler for per-engine interrupts on a particular CE.
 704  *
 705  * Invokes registered callbacks for recv_complete,
 706  * send_complete, and watermarks.
 707  */
 708 void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
 709 {
 710         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 711         struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];
 712         u32 ctrl_addr = ce_state->ctrl_addr;
 713         int ret;
 714
 715         ret = ath10k_pci_wake(ar);
 716         if (ret)
 717                 return;
 718
 719         spin_lock_bh(&ar_pci->ce_lock);
 720
 721         /* Clear the copy-complete interrupts that will be handled here. */
 722         ath10k_ce_engine_int_status_clear(ar, ctrl_addr,
 723                                           HOST_IS_COPY_COMPLETE_MASK);
 724
 725         spin_unlock_bh(&ar_pci->ce_lock);
 726
 727         if (ce_state->recv_cb)
 728                 ce_state->recv_cb(ce_state);
 729
 730         if (ce_state->send_cb)
 731                 ce_state->send_cb(ce_state);
 732
 733         spin_lock_bh(&ar_pci->ce_lock);
 734
 735         /*
 736          * Misc CE interrupts are not being handled, but still need
 737          * to be cleared.
 738          */
 739         ath10k_ce_engine_int_status_clear(ar, ctrl_addr, CE_WATERMARK_MASK);
 740
 741         spin_unlock_bh(&ar_pci->ce_lock);
 742         ath10k_pci_sleep(ar);
 743 }
 744
 745 /*
 746  * Handler for per-engine interrupts on ALL active CEs.
 747  * This is used in cases where the system is sharing a
 748  * single interrput for all CEs
 749  */
 750
 751 void ath10k_ce_per_engine_service_any(struct ath10k *ar)
 752 {
 753         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 754         int ce_id, ret;
 755         u32 intr_summary;
 756
 757         ret = ath10k_pci_wake(ar);
 758         if (ret)
 759                 return;
 760
 761         intr_summary = CE_INTERRUPT_SUMMARY(ar);
 762
 763         for (ce_id = 0; intr_summary && (ce_id < ar_pci->ce_count); ce_id++) {
 764                 if (intr_summary & (1 << ce_id))
 765                         intr_summary &= ~(1 << ce_id);
 766                 else
 767                         /* no intr pending on this CE */
 768                         continue;
 769
 770                 ath10k_ce_per_engine_service(ar, ce_id);
 771         }
 772
 773         ath10k_pci_sleep(ar);
 774 }
 775
 776 /*
 777  * Adjust interrupts for the copy complete handler.
 778  * If it's needed for either send or recv, then unmask
 779  * this interrupt; otherwise, mask it.
 780  *
 781  * Called with ce_lock held.
 782  */
 783 static void ath10k_ce_per_engine_handler_adjust(struct ath10k_ce_pipe *ce_state,
 784                                                 int disable_copy_compl_intr)
 785 {
 786         u32 ctrl_addr = ce_state->ctrl_addr;
 787         struct ath10k *ar = ce_state->ar;
 788         int ret;
 789
 790         ret = ath10k_pci_wake(ar);
 791         if (ret)
 792                 return;
 793
 794         if ((!disable_copy_compl_intr) &&
 795             (ce_state->send_cb || ce_state->recv_cb))
 796                 ath10k_ce_copy_complete_inter_enable(ar, ctrl_addr);
 797         else
 798                 ath10k_ce_copy_complete_intr_disable(ar, ctrl_addr);
 799
 800         ath10k_ce_watermark_intr_disable(ar, ctrl_addr);
 801
 802         ath10k_pci_sleep(ar);
 803 }
 804
 805 void ath10k_ce_disable_interrupts(struct ath10k *ar)
 806 {
 807         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 808         int ce_id, ret;
 809
 810         ret = ath10k_pci_wake(ar);
 811         if (ret)
 812                 return;
 813
 814         for (ce_id = 0; ce_id < ar_pci->ce_count; ce_id++) {
 815                 struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];
 816                 u32 ctrl_addr = ce_state->ctrl_addr;
 817
 818                 ath10k_ce_copy_complete_intr_disable(ar, ctrl_addr);
 819         }
 820         ath10k_pci_sleep(ar);
 821 }
 822
 823 void ath10k_ce_send_cb_register(struct ath10k_ce_pipe *ce_state,
 824                                 void (*send_cb)(struct ath10k_ce_pipe *),
 825                                 int disable_interrupts)
 826 {
 827         struct ath10k *ar = ce_state->ar;
 828         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 829
 830         spin_lock_bh(&ar_pci->ce_lock);
 831         ce_state->send_cb = send_cb;
 832         ath10k_ce_per_engine_handler_adjust(ce_state, disable_interrupts);
 833         spin_unlock_bh(&ar_pci->ce_lock);
 834 }
 835
 836 void ath10k_ce_recv_cb_register(struct ath10k_ce_pipe *ce_state,
 837                                 void (*recv_cb)(struct ath10k_ce_pipe *))
 838 {
 839         struct ath10k *ar = ce_state->ar;
 840         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 841
 842         spin_lock_bh(&ar_pci->ce_lock);
 843         ce_state->recv_cb = recv_cb;
 844         ath10k_ce_per_engine_handler_adjust(ce_state, 0);
 845         spin_unlock_bh(&ar_pci->ce_lock);
 846 }
 847
 848 static int ath10k_ce_init_src_ring(struct ath10k *ar,
 849                                    unsigned int ce_id,
 850                                    struct ath10k_ce_pipe *ce_state,
 851                                    const struct ce_attr *attr)
 852 {
 853         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 854         struct ath10k_ce_ring *src_ring;
 855         unsigned int nentries = attr->src_nentries;
 856         unsigned int ce_nbytes;
 857         u32 ctrl_addr = ath10k_ce_base_address(ce_id);
 858         dma_addr_t base_addr;
 859         char *ptr;
 860
 861         nentries = roundup_pow_of_two(nentries);
 862
 863         if (ce_state->src_ring) {
 864                 WARN_ON(ce_state->src_ring->nentries != nentries);
 865                 return 0;
 866         }
 867
 868         ce_nbytes = sizeof(struct ath10k_ce_ring) + (nentries * sizeof(void *));
 869         ptr = kzalloc(ce_nbytes, GFP_KERNEL);
 870         if (ptr == NULL)
 871                 return -ENOMEM;
 872
 873         ce_state->src_ring = (struct ath10k_ce_ring *)ptr;
 874         src_ring = ce_state->src_ring;
 875
 876         ptr += sizeof(struct ath10k_ce_ring);
 877         src_ring->nentries = nentries;
 878         src_ring->nentries_mask = nentries - 1;
 879
 880         src_ring->sw_index = ath10k_ce_src_ring_read_index_get(ar, ctrl_addr);
 881         src_ring->sw_index &= src_ring->nentries_mask;
 882         src_ring->hw_index = src_ring->sw_index;
 883
 884         src_ring->write_index =
 885                 ath10k_ce_src_ring_write_index_get(ar, ctrl_addr);
 886         src_ring->write_index &= src_ring->nentries_mask;
 887
 888         src_ring->per_transfer_context = (void **)ptr;
 889
 890         /*
 891          * Legacy platforms that do not support cache
 892          * coherent DMA are unsupported
 893          */
 894         src_ring->base_addr_owner_space_unaligned =
 895                 pci_alloc_consistent(ar_pci->pdev,
 896                                      (nentries * sizeof(struct ce_desc) +
 897                                       CE_DESC_RING_ALIGN),
 898                                      &base_addr);
 899         if (!src_ring->base_addr_owner_space_unaligned) {
 900                 kfree(ce_state->src_ring);
 901                 ce_state->src_ring = NULL;
 902                 return -ENOMEM;
 903         }
 904
 905         src_ring->base_addr_ce_space_unaligned = base_addr;
 906
 907         src_ring->base_addr_owner_space = PTR_ALIGN(
 908                         src_ring->base_addr_owner_space_unaligned,
 909                         CE_DESC_RING_ALIGN);
 910         src_ring->base_addr_ce_space = ALIGN(
 911                         src_ring->base_addr_ce_space_unaligned,
 912                         CE_DESC_RING_ALIGN);
 913
 914         /*
 915          * Also allocate a shadow src ring in regular
 916          * mem to use for faster access.
 917          */
 918         src_ring->shadow_base_unaligned =
 919                 kmalloc((nentries * sizeof(struct ce_desc) +
 920                          CE_DESC_RING_ALIGN), GFP_KERNEL);
 921         if (!src_ring->shadow_base_unaligned) {
 922                 pci_free_consistent(ar_pci->pdev,
 923                                     (nentries * sizeof(struct ce_desc) +
 924                                      CE_DESC_RING_ALIGN),
 925                                     src_ring->base_addr_owner_space,
 926                                     src_ring->base_addr_ce_space);
 927                 kfree(ce_state->src_ring);
 928                 ce_state->src_ring = NULL;
 929                 return -ENOMEM;
 930         }
 931
 932         src_ring->shadow_base = PTR_ALIGN(
 933                         src_ring->shadow_base_unaligned,
 934                         CE_DESC_RING_ALIGN);
 935
 936         ath10k_ce_src_ring_base_addr_set(ar, ctrl_addr,
 937                                          src_ring->base_addr_ce_space);
 938         ath10k_ce_src_ring_size_set(ar, ctrl_addr, nentries);
 939         ath10k_ce_src_ring_dmax_set(ar, ctrl_addr, attr->src_sz_max);
 940         ath10k_ce_src_ring_byte_swap_set(ar, ctrl_addr, 0);
 941         ath10k_ce_src_ring_lowmark_set(ar, ctrl_addr, 0);
 942         ath10k_ce_src_ring_highmark_set(ar, ctrl_addr, nentries);
 943
 944         ath10k_dbg(ATH10K_DBG_BOOT,
 945                    "boot ce src ring id %d entries %d base_addr %p\n",
 946                    ce_id, nentries, src_ring->base_addr_owner_space);
 947
 948         return 0;
 949 }
 950
 951 static int ath10k_ce_init_dest_ring(struct ath10k *ar,
 952                                     unsigned int ce_id,
 953                                     struct ath10k_ce_pipe *ce_state,
 954                                     const struct ce_attr *attr)
 955 {
 956         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
 957         struct ath10k_ce_ring *dest_ring;
 958         unsigned int nentries = attr->dest_nentries;
 959         unsigned int ce_nbytes;
 960         u32 ctrl_addr = ath10k_ce_base_address(ce_id);
 961         dma_addr_t base_addr;
 962         char *ptr;
 963
 964         nentries = roundup_pow_of_two(nentries);
 965
 966         if (ce_state->dest_ring) {
 967                 WARN_ON(ce_state->dest_ring->nentries != nentries);
 968                 return 0;
 969         }
 970
 971         ce_nbytes = sizeof(struct ath10k_ce_ring) + (nentries * sizeof(void *));
 972         ptr = kzalloc(ce_nbytes, GFP_KERNEL);
 973         if (ptr == NULL)
 974                 return -ENOMEM;
 975
 976         ce_state->dest_ring = (struct ath10k_ce_ring *)ptr;
 977         dest_ring = ce_state->dest_ring;
 978
 979         ptr += sizeof(struct ath10k_ce_ring);
 980         dest_ring->nentries = nentries;
 981         dest_ring->nentries_mask = nentries - 1;
 982
 983         dest_ring->sw_index = ath10k_ce_dest_ring_read_index_get(ar, ctrl_addr);
 984         dest_ring->sw_index &= dest_ring->nentries_mask;
 985         dest_ring->write_index =
 986                 ath10k_ce_dest_ring_write_index_get(ar, ctrl_addr);
 987         dest_ring->write_index &= dest_ring->nentries_mask;
 988
 989         dest_ring->per_transfer_context = (void **)ptr;
 990
 991         /*
 992          * Legacy platforms that do not support cache
 993          * coherent DMA are unsupported
 994          */
 995         dest_ring->base_addr_owner_space_unaligned =
 996                 pci_alloc_consistent(ar_pci->pdev,
 997                                      (nentries * sizeof(struct ce_desc) +
 998                                       CE_DESC_RING_ALIGN),
 999                                      &base_addr);
1000         if (!dest_ring->base_addr_owner_space_unaligned) {
1001                 kfree(ce_state->dest_ring);
1002                 ce_state->dest_ring = NULL;
1003                 return -ENOMEM;
1004         }
1005
1006         dest_ring->base_addr_ce_space_unaligned = base_addr;
1007
1008         /*
1009          * Correctly initialize memory to 0 to prevent garbage
1010          * data crashing system when download firmware
1011          */
1012         memset(dest_ring->base_addr_owner_space_unaligned, 0,
1013                nentries * sizeof(struct ce_desc) + CE_DESC_RING_ALIGN);
1014
1015         dest_ring->base_addr_owner_space = PTR_ALIGN(
1016                         dest_ring->base_addr_owner_space_unaligned,
1017                         CE_DESC_RING_ALIGN);
1018         dest_ring->base_addr_ce_space = ALIGN(
1019                         dest_ring->base_addr_ce_space_unaligned,
1020                         CE_DESC_RING_ALIGN);
1021
1022         ath10k_ce_dest_ring_base_addr_set(ar, ctrl_addr,
1023                                           dest_ring->base_addr_ce_space);
1024         ath10k_ce_dest_ring_size_set(ar, ctrl_addr, nentries);
1025         ath10k_ce_dest_ring_byte_swap_set(ar, ctrl_addr, 0);
1026         ath10k_ce_dest_ring_lowmark_set(ar, ctrl_addr, 0);
1027         ath10k_ce_dest_ring_highmark_set(ar, ctrl_addr, nentries);
1028
1029         ath10k_dbg(ATH10K_DBG_BOOT,
1030                    "boot ce dest ring id %d entries %d base_addr %p\n",
1031                    ce_id, nentries, dest_ring->base_addr_owner_space);
1032
1033         return 0;
1034 }
1035
1036 static struct ath10k_ce_pipe *ath10k_ce_init_state(struct ath10k *ar,
1037                                              unsigned int ce_id,
1038                                              const struct ce_attr *attr)
1039 {
1040         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1041         struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];
1042         u32 ctrl_addr = ath10k_ce_base_address(ce_id);
1043
1044         spin_lock_bh(&ar_pci->ce_lock);
1045
1046         ce_state->ar = ar;
1047         ce_state->id = ce_id;
1048         ce_state->ctrl_addr = ctrl_addr;
1049         ce_state->attr_flags = attr->flags;
1050         ce_state->src_sz_max = attr->src_sz_max;
1051
1052         spin_unlock_bh(&ar_pci->ce_lock);
1053
1054         return ce_state;
1055 }
1056
1057 /*
1058  * Initialize a Copy Engine based on caller-supplied attributes.
1059  * This may be called once to initialize both source and destination
1060  * rings or it may be called twice for separate source and destination
1061  * initialization. It may be that only one side or the other is
1062  * initialized by software/firmware.
1063  */
1064 struct ath10k_ce_pipe *ath10k_ce_init(struct ath10k *ar,
1065                                 unsigned int ce_id,
1066                                 const struct ce_attr *attr)
1067 {
1068         struct ath10k_ce_pipe *ce_state;
1069         u32 ctrl_addr = ath10k_ce_base_address(ce_id);
1070         int ret;
1071
1072         ret = ath10k_pci_wake(ar);
1073         if (ret)
1074                 return NULL;
1075
1076         ce_state = ath10k_ce_init_state(ar, ce_id, attr);
1077         if (!ce_state) {
1078                 ath10k_err("Failed to initialize CE state for ID: %d\n", ce_id);
1079                 return NULL;
1080         }
1081
1082         if (attr->src_nentries) {
1083                 ret = ath10k_ce_init_src_ring(ar, ce_id, ce_state, attr);
1084                 if (ret) {
1085                         ath10k_err("Failed to initialize CE src ring for ID: %d (%d)\n",
1086                                    ce_id, ret);
1087                         ath10k_ce_deinit(ce_state);
1088                         return NULL;
1089                 }
1090         }
1091
1092         if (attr->dest_nentries) {
1093                 ret = ath10k_ce_init_dest_ring(ar, ce_id, ce_state, attr);
1094                 if (ret) {
1095                         ath10k_err("Failed to initialize CE dest ring for ID: %d (%d)\n",
1096                                    ce_id, ret);
1097                         ath10k_ce_deinit(ce_state);
1098                         return NULL;
1099                 }
1100         }
1101
1102         /* Enable CE error interrupts */
1103         ath10k_ce_error_intr_enable(ar, ctrl_addr);
1104
1105         ath10k_pci_sleep(ar);
1106
1107         return ce_state;
1108 }
1109
1110 void ath10k_ce_deinit(struct ath10k_ce_pipe *ce_state)
1111 {
1112         struct ath10k *ar = ce_state->ar;
1113         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1114
1115         if (ce_state->src_ring) {
1116                 kfree(ce_state->src_ring->shadow_base_unaligned);
1117                 pci_free_consistent(ar_pci->pdev,
1118                                     (ce_state->src_ring->nentries *
1119                                      sizeof(struct ce_desc) +
1120                                      CE_DESC_RING_ALIGN),
1121                                     ce_state->src_ring->base_addr_owner_space,
1122                                     ce_state->src_ring->base_addr_ce_space);
1123                 kfree(ce_state->src_ring);
1124         }
1125
1126         if (ce_state->dest_ring) {
1127                 pci_free_consistent(ar_pci->pdev,
1128                                     (ce_state->dest_ring->nentries *
1129                                      sizeof(struct ce_desc) +
1130                                      CE_DESC_RING_ALIGN),
1131                                     ce_state->dest_ring->base_addr_owner_space,
1132                                     ce_state->dest_ring->base_addr_ce_space);
1133                 kfree(ce_state->dest_ring);
1134         }
1135
1136         ce_state->src_ring = NULL;
1137         ce_state->dest_ring = NULL;
1138 }