Merge tag 'drm-intel-next-fixes-2015-04-25' of git://anongit.freedesktop.org/drm...

three fixes for i915.

* tag 'drm-intel-next-fixes-2015-04-25' of git://anongit.freedesktop.org/drm-intel:
  drm/i915: vlv: fix save/restore of GFX_MAX_REQ_COUNT reg
  drm/i915: Workaround to avoid lite restore with HEAD==TAIL
  drm/i915: cope with large i2c transfers

diff --combined drivers/gpu/drm/i915/i915_drv.c
index c24c3f1,9cc953e..c302ffb
--- 1/drivers/gpu/drm/i915/i915_drv.c
--- 2/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@@ -1038,7 -1038,7 +1038,7 @@@ static void vlv_save_gunit_s0ix_state(s
                s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
  
        s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
-       s->gfx_max_req_count    = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
+       s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
  
        s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
        s->ecochk               = I915_READ(GAM_ECOCHK);
@@@ -1091,7 -1091,6 +1091,7 @@@
        /* Gunit-Display CZ domain, 0x182028-0x1821CF */
        s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
        s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
 +      s->pcbr                 = I915_READ(VLV_PCBR);
        s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
  
        /*
@@@ -1120,7 -1119,7 +1120,7 @@@ static void vlv_restore_gunit_s0ix_stat
                I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
  
        I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
-       I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
+       I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
  
        I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
        I915_WRITE(GAM_ECOCHK,          s->ecochk);
@@@ -1186,7 -1185,6 +1186,7 @@@
        /* Gunit-Display CZ domain, 0x182028-0x1821CF */
        I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
        I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
 +      I915_WRITE(VLV_PCBR,                    s->pcbr);
        I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
  }
  
@@@ -1195,7 -1193,19 +1195,7 @@@ int vlv_force_gfx_clock(struct drm_i915
        u32 val;
        int err;
  
 -      val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
 -      WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
 -
  #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
 -      /* Wait for a previous force-off to settle */
 -      if (force_on) {
 -              err = wait_for(!COND, 20);
 -              if (err) {
 -                      DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
 -                                I915_READ(VLV_GTLC_SURVIVABILITY_REG));
 -                      return err;
 -              }
 -      }
  
        val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
        val &= ~VLV_GFX_CLK_FORCE_ON_BIT;