ARM: dts: am335x: Provide NAND ready pin
authorRoger Quadros <rogerq@ti.com>
Thu, 7 Apr 2016 10:25:39 +0000 (13:25 +0300)
committerTony Lindgren <tony@atomide.com>
Tue, 12 Apr 2016 21:32:02 +0000 (14:32 -0700)
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.

For NAND we don't use GPMC wait pin monitoring but
get the NAND Ready/Busy# status using GPIOlib.
GPMC driver provides the WAIT0 pin status over GPIOlib.

Read speed increases from 7869 KiB/ to 8875 KiB/s
and write speed was unchanged at 5100 KiB/s.

Measured using mtd_speedtest.ko on am335x-evm.

Cc: Teresa Remmet <t.remmet@phytec.de>
Cc: Ilya Ledvich <ilya@compulab.co.il>
Cc: Yegor Yefremov <yegorslists@googlemail.com>
Cc: Rostislav Lisovy <lisovy@gmail.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/boot/dts/am335x-baltos-ir5221.dts
arch/arm/boot/dts/am335x-chilisom.dtsi
arch/arm/boot/dts/am335x-cm-t335.dts
arch/arm/boot/dts/am335x-evm.dts
arch/arm/boot/dts/am335x-igep0033.dtsi
arch/arm/boot/dts/am335x-phycore-som.dtsi

index f2ad35e..c743d5d 100644 (file)
                interrupt-parent = <&gpmc>;
                interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                             <1 IRQ_TYPE_NONE>; /* termcount */
+               rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
                nand-bus-width = <8>;
                ti,nand-ecc-opt = "bch8";
                ti,nand-xfer-type = "polled";
index 95461a2..e48c282 100644 (file)
                interrupt-parent = <&gpmc>;
                interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                             <1 IRQ_TYPE_NONE>; /* termcount */
+               rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
                ti,nand-ecc-opt = "bch8";
                ti,elm-id = <&elm>;
                nand-bus-width = <8>;
index e835644..817b1de 100644 (file)
@@ -411,6 +411,7 @@ status = "okay";
                interrupt-parent = <&gpmc>;
                interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                             <1 IRQ_TYPE_NONE>; /* termcount */
+               rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
                ti,nand-ecc-opt = "bch8";
                ti,elm-id = <&elm>;
                nand-bus-width = <8>;
index 28b9162..516673b 100644 (file)
                interrupt-parent = <&gpmc>;
                interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                             <1 IRQ_TYPE_NONE>; /* termcount */
+               rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
                ti,nand-ecc-opt = "bch8";
                ti,elm-id = <&elm>;
                nand-bus-width = <8>;
index 6c3a9bf..df63484 100644 (file)
                interrupt-parent = <&gpmc>;
                interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                             <1 IRQ_TYPE_NONE>; /* termcount */
+               rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
                nand-bus-width = <8>;
                ti,nand-ecc-opt = "bch8";
                gpmc,device-width = <1>;
index d4b7f3b..86f7731 100644 (file)
                interrupt-parent = <&gpmc>;
                interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                             <1 IRQ_TYPE_NONE>; /* termcount */
+               rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
                nand-bus-width = <8>;
                ti,nand-ecc-opt = "bch8";
                gpmc,device-nand = "true";