ARM: dts: r8a7792: initial SoC device tree

The initial R8A7792 SoC device tree including CPU cores, GIC, timer, SYSC,
and the required  clock descriptions.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
new file mode 100644 (file)
index 0000000..33f2362
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -0,0 +1,170 @@
+/*
+ * Device Tree Source for the r8a7792 SoC
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/clock/r8a7792-clock.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a7792-sysc.h>
+
+/ {
+       compatible = "renesas,r8a7792";
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <0>;
+                       clock-frequency = <1000000000>;
+                       clocks = <&cpg_clocks R8A7792_CLK_Z>;
+                       power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
+                       next-level-cache = <&L2_CA15>;
+               };
+
+               L2_CA15: cache-controller@0 {
+                       compatible = "cache";
+                       reg = <0>;
+                       cache-unified;
+                       cache-level = <2>;
+                       power-domains = <&sysc R8A7792_PD_CA15_SCU>;
+               };
+       };
+
+       soc {
+               compatible = "simple-bus";
+               interrupt-parent = <&gic>;
+
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               gic: interrupt-controller@f1001000 {
+                       compatible = "arm,gic-400";
+                       #interrupt-cells = <3>;
+                       interrupt-controller;
+                       reg = <0 0xf1001000 0 0x1000>,
+                             <0 0xf1002000 0 0x1000>,
+                             <0 0xf1004000 0 0x2000>,
+                             <0 0xf1006000 0 0x2000>;
+                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+                                     IRQ_TYPE_LEVEL_HIGH)>;
+               };
+
+               timer {
+                       compatible = "arm,armv7-timer";
+                       interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+                                     IRQ_TYPE_LEVEL_LOW)>,
+                                    <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+                                     IRQ_TYPE_LEVEL_LOW)>,
+                                    <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+                                     IRQ_TYPE_LEVEL_LOW)>,
+                                    <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+                                     IRQ_TYPE_LEVEL_LOW)>;
+               };
+
+               sysc: system-controller@e6180000 {
+                       compatible = "renesas,r8a7792-sysc";
+                       reg = <0 0xe6180000 0 0x0200>;
+                       #power-domain-cells = <1>;
+               };
+
+               /* Special CPG clocks */
+               cpg_clocks: cpg_clocks@e6150000 {
+                       compatible = "renesas,r8a7792-cpg-clocks",
+                                    "renesas,rcar-gen2-cpg-clocks";
+                       reg = <0 0xe6150000 0 0x1000>;
+                       clocks = <&extal_clk>;
+                       #clock-cells = <1>;
+                       clock-output-names = "main", "pll0", "pll1", "pll3",
+                                            "lb", "qspi", "z", "adsp";
+                       #power-domain-cells = <0>;
+               };
+
+               /* Fixed factor clocks */
+               zs_clk: zs {
+                       compatible = "fixed-factor-clock";
+                       clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+                       #clock-cells = <0>;
+                       clock-div = <6>;
+                       clock-mult = <1>;
+               };
+               p_clk: p {
+                       compatible = "fixed-factor-clock";
+                       clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+                       #clock-cells = <0>;
+                       clock-div = <24>;
+                       clock-mult = <1>;
+               };
+               cp_clk: cp {
+                       compatible = "fixed-factor-clock";
+                       clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+                       #clock-cells = <0>;
+                       clock-div = <48>;
+                       clock-mult = <1>;
+               };
+
+               /* Gate clocks */
+               mstp2_clks: mstp2_clks@e6150138 {
+                       compatible = "renesas,r8a7792-mstp-clocks",
+                                    "renesas,cpg-mstp-clocks";
+                       reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+                       clocks = <&zs_clk>, <&zs_clk>;
+                       #clock-cells = <1>;
+                       clock-indices = <
+                               R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
+                       >;
+                       clock-output-names = "sys-dmac1", "sys-dmac0";
+               };
+               mstp4_clks: mstp4_clks@e6150140 {
+                       compatible = "renesas,r8a7792-mstp-clocks",
+                                    "renesas,cpg-mstp-clocks";
+                       reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
+                       clocks = <&cp_clk>;
+                       #clock-cells = <1>;
+                       clock-indices = <R8A7792_CLK_IRQC>;
+                       clock-output-names = "irqc";
+               };
+               mstp7_clks: mstp7_clks@e615014c {
+                       compatible = "renesas,r8a7792-mstp-clocks",
+                                    "renesas,cpg-mstp-clocks";
+                       reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+                       clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
+                                <&p_clk>, <&p_clk>;
+                       #clock-cells = <1>;
+                       clock-indices = <
+                               R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
+                               R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
+                               R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
+                       >;
+                       clock-output-names = "hscif1", "hscif0", "scif3",
+                                            "scif2", "scif1", "scif0";
+               };
+       };
+
+       /* External root clock */
+       extal_clk: extal {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board. */
+               clock-frequency = <0>;
+       };
+
+       /* External SCIF clock */
+       scif_clk: scif {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board. */
+               clock-frequency = <0>;
+       };
+};