PCI: rockchip: Fix wrong transmitted FTS count

If the expected number of FTS aren't received by RC when exiting from L0s,
the LTSSM will fall into recover state, which means it will need to send TS
for retraining which makes the latency of exiting from L0s a little longer
than expected.  This issue is caused by an incorrect reset value of FTS
count on PLC1 register (offset 0x4).  The expected value for Gen1/2 should
be more than 240 and we may leave a little margin here.  Fix this before
starting Gen1 training which will make TS1 contain the correct FTS count.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 43b765e..b8c82fc 100644 (file)
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -95,6 +95,10 @@
 #define   PCIE_CORE_PL_CONF_SPEED_MASK         0x00000018
 #define   PCIE_CORE_PL_CONF_LANE_MASK          0x00000006
 #define   PCIE_CORE_PL_CONF_LANE_SHIFT         1
+#define PCIE_CORE_CTRL_PLC1            (PCIE_CORE_CTRL_MGMT_BASE + 0x004)
+#define   PCIE_CORE_CTRL_PLC1_FTS_MASK         GENMASK(23, 8)
+#define   PCIE_CORE_CTRL_PLC1_FTS_SHIFT                8
+#define   PCIE_CORE_CTRL_PLC1_FTS_CNT          0xffff
 #define PCIE_CORE_TXCREDIT_CFG1                (PCIE_CORE_CTRL_MGMT_BASE + 0x020)
 #define   PCIE_CORE_TXCREDIT_CFG1_MUI_MASK     0xFFFF0000
 #define   PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT    16
@@ -486,6 +490,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
        status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
        rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
 
+       /* Fix the transmitted FTS count desired to exit from L0s. */
+       status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
+       status = (status & PCIE_CORE_CTRL_PLC1_FTS_MASK) |
+                (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
+       rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
+
        /* Enable Gen1 training */
        rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
                            PCIE_CLIENT_CONFIG);